KR101642930B1 - Nonvolatile memory device having a dummy cell and program method thereof - Google Patents

Abstract

The present invention relates to a non-volatile memory device comprising dummy cells. A nonvolatile memory device according to an exemplary embodiment of the present invention includes a dummy cell connected to a dummy bit line, a page buffer connected to the dummy bit line, and a program memory having a lower program state than the highest program state, And a control logic to load dummy data into a page buffer coupled to the dummy bit line to be programmed into the page buffer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device having a dummy cell,

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a method of programming the same.

In general, a semiconductor memory device is divided into a volatile semiconductor memory device and a non-volatile semiconductor memory device. The volatile semiconductor memory device has a drawback that the read and write speed is fast but the stored contents are lost when the external power supply is cut off. On the other hand, the nonvolatile semiconductor memory device preserves its contents even if the external power supply is interrupted. Therefore, the nonvolatile semiconductor memory device is used to store contents to be stored regardless of whether power is supplied or not. Nonvolatile semiconductor memory devices include, but are not limited to, a mask read-only memory (MROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM) Erasable programmable read-only memory (EEPROM), and the like.

Generally, MROM, PROM, and EPROM are not easy to erase and write on the system itself, and therefore it is not easy for general users to update their memory contents. On the other hand, since EEPROM can be electrically erased and written, application to system programming and auxiliary memory devices that require continuous updating is expanding. In particular, flash EEPROM (hereinafter, referred to as flash memory) has a higher integration density than conventional EEPROMs, which is very advantageous for application as a large capacity auxiliary memory device. Among the flash EEPROMs, NAND-type flash EEPROMs (hereinafter referred to as NAND type flash memories) have a very high integration degree compared to other flash EEPROMs.

A flash memory device based on the EEPROM technology described above can store a large amount of information. And flash memory devices can read stored information at any time. With the demand for higher capacity for flash memory devices, the degree of integration of memory cells is increasing. Or, efforts have been made to store multi-bit data in one memory cell for high capacity.

Also, as the capacity of the memory cell increases, the influence of the interference generated between the memory cells on the performance increases. Interference between memory cells and dummy cells, or between bit lines and dummy bit lines, will affect the reliability of the data.

The present invention provides a nonvolatile memory device that blocks the influence of interference caused by a dummy string and a method of programming the same.

According to an aspect of the present invention, there is provided a nonvolatile memory device including: a dummy cell connected to a dummy bit line; a page buffer connected to the dummy bit line; And control logic for loading the dummy data into a page buffer connected to the dummy bit line such that the dummy cell is programmed to a program state lower than the highest program state and higher than the erase state during program operation.

According to another aspect of the present invention, there is provided a method of programming a nonvolatile memory device, comprising: loading dummy data into a page buffer connected to a dummy bit line; And programming a dummy cell connected to the dummy bit line, wherein the dummy data is data for programming the dummy cell to a program state lower than the highest program state and higher than the erase state.

According to the embodiments of the present invention, it is possible to prevent interference due to the dummy bit lines and the dummy cells, thereby providing a non-volatile memory device having high reliability.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

Hereinafter, a NAND type flash memory device is used as an example of a nonvolatile memory device for explaining features and functions of the present invention. However, those skilled in the art will readily appreciate other advantages and capabilities of the present invention in accordance with the teachings herein. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, or the like can be used as a storage medium, and the present invention can be applied to a memory system in which heterogeneous memory devices are mixed. Further, the present invention may be implemented or applied through other embodiments. Moreover, the detailed description can be modified or changed in accordance with the viewpoint and use without departing from the scope of the present invention, technical idea and other objects.

FIG. 1 is a view showing a threshold voltage distribution of dummy cells according to an embodiment of the present invention. Referring to FIG. The threshold voltage distribution of a two-bit MLC (2-bit Multi-level Cell) is illustratively illustrated to illustrate features of the present invention.

In the case of a 2-bit MLC, memory cells storing data are programmed into one of four program states (E0, P1, P2, P3). That is, the threshold voltage of the memory cells is included in one of the four program states (E0, P1, P2, P3) by the program. During the erase operation, the threshold voltage of the programmed memory cells shifts to the erase state E0. According to an embodiment of the present invention, the threshold voltage of the dummy cells is included in either the shaded erase state E0 or the program states P1 and P2. During the erase operation, the threshold voltage of the dummy cells shifts to the hatched erase state E0. However, when the normal memory cells of the same page are programmed, the dummy cells can be programmed into one of the shaded program states P1 and P2.

In a non-volatile memory device, adjacent memory cells having different threshold voltages have mutual influences. That is, the floating gates of adjacent memory cells having different threshold voltages may interfere with each other or receive each other. Examples of interference include program disturbance and lateral charge spreading. The threshold voltage of the memory cell may increase or decrease in an unintended direction depending on the interference between the adjacent cells. Particularly, this interference phenomenon is conspicuous between the memory cell programmed in the erase state E0 and the memory cell programmed in the program state P3 having the highest threshold voltage among the memory cells.

In a nonvolatile memory device including dummy cells, a problem of interference due to dummy cells arises. The dummy cells connected in series are connected between the selection transistors SST and GST. The dummy cells and the selection transistors (SST, GST) constitute one dummy string. The dummy string is then connected to the dummy bit line. A normal string (a cell string in which valid data is stored) may be formed adjacent to the dummy string. The memory cells included in the normal string and the dummy cells included in the dummy string may interfere with each other.

The dummy bit line may be set to be connected to a Pocket P-Well (PPW), or to remain in a floating state. When the dummy bit line is connected to the pocket P-well PPW, the dummy cells will be programmed during program operation. However, the program verification operation for the dummy cells may not be provided. Therefore, program inhibit is not set even after programmed with the appropriate voltage. In this case, the dummy cells may be programmed to the highest state (e.g., P3) or higher and the program state (P3 ') higher than the highest state. Also, when the dummy cells are electrically floated, the dummy cells are not programmed but are subject to repeated erase. The threshold voltage of the dummy cells can be shifted to the under-ground state (E0 ') when exposed to iterative erase.

However, according to the embodiment of the present invention, the threshold voltage of the dummy cells is distributed in the erase state E0 and the program states P1 and P2. Therefore, it is possible to prevent interference between all cells, such as program disturb and side charge leakage. Here, for convenience of description, a 2-bit MLC is illustrated as an example, but the same technical features as the present invention can be applied to a 3-bit or more MLC.

2 is a block diagram illustrating a non-volatile memory device 100 in accordance with an embodiment of the present invention. Referring to FIG. 2, a non-volatile memory device 100 includes a cell array 110, a decoder 120, a page buffer 130, and control logic 140. In particular, the page buffer 130 includes a second page buffer 132 coupled to the dummy bit line.

The cell array 110 may include a plurality of memory blocks. In Fig. 2, one memory block is shown as an example. Each memory block may be composed of a plurality of pages. And each page (e.g., 115) may be comprised of a plurality of memory cells. In the nonvolatile memory device 100, an erase operation is performed on a memory block basis, and a write or read operation can be performed on a page-by-page basis. The cell array 110 may include dummy cells. The dummy cells are connected to the dummy bit lines DBL0, DBL1 and DBL2. Valid data is not stored in dummy cells.

The cell array 110 has a cell string structure. One cell string includes a string selection transistor SST connected to a string selection line SSL, a plurality of memory cells connected to a plurality of word lines WL0 to WL31, and a ground selection line GSL Selection Line (GST). The string selection transistor SST is connected to the bit line BL and the ground selection transistor GST is connected to the common source line CSL.

A plurality of memory cells may be connected to one word line (e.g., WL1). The set of memory cells connected to one word line and programmed at the same time is commonly referred to as a page. For example, when programming one page 115, the program voltage Vpgm and the verify voltage may alternately be provided to the word line WL1. During the program operation, the program data is supplied to the bit lines connected to the selected page 115. For verification operations, the bit lines connected to each of the memory cells of the selected page 115 are precharged. Then, a voltage change of the precharged bit line is detected. The success or failure of programming the memory cells is determined based on the detected voltage change of the bit line.

Decoder 120 is coupled to cell array 110 via select lines SSL and GSL or word lines WL0 through WL31. In a program or read operation, the decoder 120 receives an address and selects one of the word lines (e.g., WL1). On the other hand, the decoder 120 transfers the voltage required for the program or read operation to the selected word line WL1 or the unselected word line (except WL1).

The page buffer 130 is connected to the cell array 110 through the bit lines BL0 to BLn-1 and the dummy bit lines DBL0, DBL1 and DBL2. The page buffer 130 includes a first page buffer 131 connected to the bit lines BL0 to BLn-1. The first page buffer 131 transfers data (Data) in the program operation to the selection page 115. When the program is verified, the first page buffer 131 transfers the data sensed through the bit lines BL0 to BLn-1 to the control logic 140. [ The first page buffer 131 reads data from the selected page 115 at the time of a read operation and outputs data Data to the outside.

The second page buffer 132 is connected to the dummy bit lines DBL0, DBL1 and DBL2. The second page buffer 132 biases the dummy bit lines DBL0, DBL1 and DBL2 during a program operation. The dummy cells included in the selection page 115 will be programmed to one of the program states P1 and P2 by the bias of the dummy bit lines DBL0, DBL1 and DBL2. The second page buffer 132 transfers the dummy data to the control logic 140 through the dummy bit lines DBL0, DBL1 and DBL2. In a read operation, the read operation of the second page buffer 132 may be inactivated.

The control logic 140 may control operations such as programming, reading, erasing, etc. of the non-volatile memory device 100. For example, during program operation, the control logic 140 may control the decoder 120 to provide a program voltage to the selected word line. The control logic 140 may control the page buffer 130 so that the program data is provided to the selected page 115. [

In particular, the control logic 140 controls the first page buffer 131 and the second page buffer 132 to transfer data to the bit lines BL0 to BLn-1 and the dummy bit lines DBL0, DBL1, 132). In a program verify operation, the control logic 140 controls the first page buffer 131 and the second page buffer 132 to sense normal memory cells and dummy cells included in the select page 115. [ The verification data sensed from the first page buffer 131 and the second page buffer 132 are transmitted to the control logic 140 again. The control logic 140 determines pass / fail for the selected page 115 with reference to the transmitted verification data.

The nonvolatile memory device 100 according to the embodiment of the present invention programs dummy cells into program states P1 and P2 during a program operation. As a result, the nonvolatile memory device 100 according to the embodiment of the present invention can reduce the interference phenomenon by the dummy cells exposed to the repeated erase. That is, the problem that the dummy cells are not programmed and is exposed to the repeated erase and moves to the over-erased state (E0 ') can be prevented. The nonvolatile memory device 100 according to the embodiment of the present invention can block a program operation and a program state or a problem programmed in the most significant state P3. Through the second page buffer 132 connected to the dummy bit line, the interference of the dummy cells on adjacent normal cells can be blocked.

3 is a simplified illustration of a cell array 110 and page buffer 130 of a non-volatile memory device 100 (see FIG. 2). The first page buffer 131 includes page buffer circuits PB0 and PB1 connected to bit lines BL0 and BL1 of normal cell strings. The second page buffer 132 is connected to the dummy bit line DBL0 connected to the dummy cell string. The page buffer circuits PB1 and PB1 included in the first page buffer 131 and the page buffer circuit DPB0 included in the second page buffer 132 may be structurally identical.

In the program operation, the power supply voltage Vcc is used as the string selection line SSL, the ground voltage (or 0 V) is used as the ground selection line GSL, and the source line voltage V _CSL is used as the common source line CSL 2V) may be provided. Then, the page buffer circuit PB0 applies the ground voltage (or 0V) to the program bit line (BL0). The page buffer circuit PB1 applies the power supply voltage Vcc to the program inhibited bit line BL1. Also, the page buffer circuit DPB0 applies a ground voltage (0V) to the dummy bit line DBL0. In this state, the pass voltage Vpass or the program voltage Vpgm is applied to the word lines.

Then, the memory cell MC0 selected by the page buffer circuit PB0 will be programmed to one of the program states P1, P2, and P3. On the other hand, the selected memory cell MC1 will remain in the previous state. The selected dummy cell DMC0 can be programmed to any one of the program states P1 and P2 under the control of the page buffer circuit DPB0.

The page buffer circuits PB0 and PB1 described above can receive program data from the outside. Program data may be provided to the page buffer circuits PB0 and PB1 through an input / output bus (I / O bus). In addition, the page buffer circuits PB0 and PB1 may transmit the sensed data through the bit lines BL0 and BL1 to the control logic 140 (see FIG. 2) during program verification.

On the other hand, the page buffer circuit DPB0 loads the dummy data provided from the control logic 140 or the fuse option (not shown) into the internal latches. The page buffer circuit DPB0 biases the dummy bit line DBL0 according to the loaded dummy data. The page buffer circuit DPB0 transfers the data sensed through the dummy bit line DBL0 to the control logic 140 during program verification.

In the erase operation, the word lines are biased to 0V and the selection lines (SSL, GSL) are electrically floating. Then, the bit lines BL0, BL1, DBL0 and the common source line CSL are biased in a floating state. When the erase voltage Verase is provided to the pocket P-well PPW in the above-described bias state, the dummy cells in the block or the normal memory cells are erased.

In the read operation, the selected read voltage Vrd is provided for the selected word line, and the unselected read voltage Vread is provided for the unselected word lines and the selected lines SSL and GSL. Then, the common source line CSL and the dummy bit line can be biased to 0V. The bit lines will be sensed in this bias state. However, the data of the dummy cell sensed through the dummy bit line DBL0 is not related to the data requested to be written externally. Therefore, the dummy data sensed from the dummy cells can be set not to be output to the outside of the nonvolatile memory device 100. [

4 is a flowchart showing a programming method of the nonvolatile memory device 100 shown in FIG. During program operation, the dummy cells may be programmed by the page buffer connected to the dummy bit line.

When the program operation is started, program data and dummy data will be loaded into the first page buffer 131 and the second page buffer 132 under the control of the control logic 140 (see FIG. 1). Dummy data is a logical value for programming the dummy cells into program states (e.g., P1, P2) that are lower than the program state (P3 ') or the highest state (P3). This data load operation is shown in step S110.

In step S120, normal memory cells and dummy cells are programmed in the bias state shown in FIG. The normal memory cells may be programmed in one of the program states P1, P2, and P3. However, the dummy memory cells will be programmed to one of the program states P1 and P2. If it is a 3-bit MLC, the dummy memory cells will have seven program states P1 to P7. The dummy memory cells may be programmed to be programmed in any one of the program states P1 to P6. Here, the program state P7 corresponds to the highest threshold voltage distribution among the program states P1 to P7.

If it is a 4-bit MLC, the dummy memory cells may have fifteen program states P1 to P15. The dummy cells may be programmed to be programmed in any one of the program states P1 to P14. Here, the program state P15 corresponds to the highest threshold voltage distribution among the program states P1 to P15. The program state (Pn, n is a natural number) in which the dummy cells are programmed may be set to a state capable of minimizing interference to neighboring normal memory cells.

In step S130, a verify read procedure is performed on the programmed normal memory cells and the dummy cells. The word line of the selected page is provided with a verify voltage. The first page buffer 131 and the second page buffer 132 sense the connected bit lines, respectively. The sensed data is temporarily stored in the first page buffer 131 and the second page buffer 132 and transferred to the control logic 140.

In step S140, it is determined whether or not the memory cells sensed by the verify read operation are programmed. If any of the selected memory cells (normal memory cell and dummy cell) is determined to be a program fail, the procedure moves to step S120 for reprogramming the selected page. However, if all of the selected memory cells (normal memory cell and dummy cell) are determined to be a program fail, the overall program operation is terminated.

5 is a table briefly showing an example in which dummy cells are programmed by the program procedures of FIG. Here, program steps will be described as an example of a 2-bit MLC in order to explain features of the present invention.

In the program phase of the first page (or LSB page), the normal memory cells can be programmed to the erase state E0 or the program state P2 '. The erase state E0 represents the threshold voltage distribution of the program inhibited memory cells of the normal memory cells. During a program operation, a power supply voltage (Vcc) may be applied to a bit line of program inhibited memory cells. The program state P2 'represents the target distribution of the memory cells to be programmed among the normal memory cells. During program operation, the ground voltage (0V) will be applied to the bit lines of the memory cells programmed in these program states (P2 ').

On the other hand, in the program phase of the first page (or LSB page), all the dummy cells are biased by program inhibition. That is, in the program phase of the first page (or LSB page), the second page buffer 132 will apply the power supply voltage Vcc to the dummy bit line. To this end, the logic '1' may be loaded into the page buffer circuits of the second page buffer 132 at the program phase of the first page (or LSB page). Depending on the program result of the first page (or LSB page), the dummy cells will remain in the erase state E0.

In the program phase of the second page (or MSB page), normal memory cells can be programmed in either the erase state E0 or the program states P1, P2, P3. On the other hand, in the program stage of the second page (or MSB page), all of the dummy cells are programmed in the program state P1. That is, in the programming phase of the second page (or MSB page), the second page buffer 132 will apply the ground voltage (0V) to the dummy bit lines. To this end, a logic '0' may be loaded into the page buffer circuits of the second page buffer 132 at the program phase of the second page (or MSB page). All dummy cells are programmed in the program state (P1) according to the program result of the second page (or MSB page).

If all the dummy cells are programmed in the program state P1, the interference received by the dummy cells and the adjacent normal memory cells can be significantly reduced.

6 is a table briefly showing another embodiment in which dummy cells are programmed by the program procedures of FIG.

In the program phase of the first page (or LSB page), the normal memory cells can be programmed to the erase state E0 or the program state P2 '. The erase state E0 represents the threshold voltage distribution of the program inhibited memory cells of the normal memory cells. During a program operation, a power supply voltage (Vcc) may be applied to a bit line of program inhibited memory cells. The program state P2 'represents the target distribution of the memory cells to be programmed among the normal memory cells. During program operation, the ground voltage (0V) will be applied to the bit lines of the memory cells programmed in these program states (P2 ').

On the other hand, in the program phase of the first page (or LSB page), all the dummy cells are programmed to the program state P2 '. That is, in the programming phase of the first page (or LSB page), the second page buffer 132 will apply a ground voltage (0V) to the dummy bit line. To this end, a logic '0' may be loaded into the page buffer circuits of the second page buffer 132 at the program phase of the first page (or LSB page).

In the program phase of the second page (or MSB page), normal memory cells can be programmed in either the erase state E0 or the program states P1, P2, P3. On the other hand, in the program phase of the second page (or MSB page), all of the dummy cells are programmed in the program state P2.

The embodiments described in FIGS. 5 and 6 are examples for showing the program timing of the dummy cells in the program operation of the MLC. That is, in FIG. 5, an example in which the dummy cells are programmed in the target state during the program operation of the MSB page has been described. On the other hand, in Fig. 6, an example in which the dummy cells are programmed to the target state during the program operation of the LSB page has been described. The programming method of the dummy cells described in FIGS. 5 and 6 is merely an example for explaining the technical features of the present invention. That is, the technical features of the present invention can be equally applied to 3-bit or more MLCs.

FIG. 7 is a state diagram illustrating a transition of a state of dummy cells according to an embodiment of the present invention. Referring to FIG. Referring to FIG. 7, the dummy cells of the nonvolatile memory device 100 are blocked from repetitive erasing. Here, iterative erasing means that the dummy cells are continuously exposed only to the block erasing operation. Therefore, the phenomenon that the dummy cells are erased in the under-erased state 160 can be originally blocked. That is, for example, in the charge trapping type flash memory, excessive holes may be injected into the charge trap layer of the dummy cells to block the phenomenon of affecting the charge trap layer of adjacent normal memory cells. Moreover, although not shown, the phenomenon that the dummy cells are programmed in the highest state (e.g., P3) or in the over-programmed state may also be blocked.

In the nonvolatile memory device 100 according to the embodiment of the present invention, a state transition occurs only in the dummy cells between the erase state E0 and the program states P1 and P2. The state transition between the dead-time program-erase state of such a dummy cell is indicated by an identification code 150.

The embodiments described above can be applied or modified to various memory devices including dummy cells. For example, the present invention can be applied to a semiconductor memory device formed in three dimensions. That is, the dummy cells may be controlled based on the above-described embodiment even in a semiconductor memory structure in which a cell string is formed in a vertical structure.

8 is a block diagram illustrating a solid state disk (SSD) including a nonvolatile memory device according to an embodiment of the present invention. Referring to FIG. 8, the SSD system 1000 includes a host 1100 and an SSD 1200. The SSD 1200 includes an SSD controller 1210, a buffer memory 1220, and a non-volatile memory device 1230.

The SSD controller 1210 provides a physical connection between the host 1100 and the SSD 1200. That is, the SSD controller 1210 provides interfacing with the SSD 1200 in response to the bus format of the host 1100. In particular, the SSD controller 1210 decodes the instruction provided from the host 1100. [ Depending on the decoded result, the SSD controller 1210 accesses the non-volatile memory device 1230. (PCI) express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), and the like are used as the bus format of the host 1100. [ And the like.

In the buffer memory 1220, write data provided from the host 1100 or data read from the nonvolatile memory device 1230 are temporarily stored. When data existing in the nonvolatile memory device 1230 is cached at the time of the read request of the host 1100, the buffer memory 1220 supports the cache function of providing the cached data directly to the host 1100 . Generally, the data transfer rate by the host 1100 in the bus format (e.g., SATA or SAS) is much faster than the transfer rate of the memory channel of the SSD 1200. That is, when the interface speed of the host 1100 is much higher, performance degradation caused by speed difference can be minimized by providing a buffer memory 1220 of a large capacity.

The buffer memory 1220 may be provided to a synchronous DRAM (DRAM) to provide sufficient buffering in the SSD 1200 used as a large capacity auxiliary storage device. However, it will be apparent to those skilled in the art that the buffer memory 1220 is not limited to the disclosure herein.

The nonvolatile memory device 1230 is provided as a storage medium of the SSD 1200. For example, the non-volatile memory device 1230 may be provided as a NAND-type Flash memory having a large storage capacity. The non-volatile memory device 1230 may be comprised of a plurality of memory devices. In this case, each memory device is connected to the SSD controller 1210 on a channel-by-channel basis. Although the nonvolatile memory device 1230 has been described as a storage medium by way of example of a NAND flash memory, it may be composed of other nonvolatile memory devices. For example, PRAM, MRAM, ReRAM, FRAM, NOR flash memory, or the like may be used as a storage medium, and a memory system in which heterogeneous memory devices are mixed can be applied. And a volatile memory device (for example, a DRAM) as a storage medium.

In FIG. 8, at least one non-volatile memory device 1230 may include the non-volatile memory device 100 shown in FIG.

9 is a block diagram briefly showing a memory system 2000 according to the present invention. Referring to FIG. 9, a memory system 2000 according to the present invention includes a non-volatile memory device 2200 and a memory controller 2100.

The non-volatile memory device 2200 can be any of the non-volatile memory devices 200 shown in FIG. 2 described above. The memory controller 2100 will be configured to control the non-volatile memory device 2200. The combination of the nonvolatile memory device 2200 and the memory controller 2100 may be provided as a memory card or an SSD. The SRAM 2110 is used as an operation memory of the processing unit 2120. The host interface 2130 has a data exchange protocol of the host connected to the memory system 2000. The error correction block 2140 detects and corrects errors contained in the data read from the nonvolatile memory device 2200. The memory interface 2150 interfaces with the non-volatile memory device 2200 of the present invention. The processing unit 2120 performs all control operations for data exchange of the memory controller 2100. Although it is not shown in the drawing, the memory system 2000 according to the present invention can be further provided with a ROM (not shown) or the like for storing code data for interfacing with a host, To those who have learned. The non-volatile memory device 2200 may be provided in a multi-chip package comprising a plurality of flash memory chips. The memory system 2000 of the present invention can be provided as a highly reliable storage medium with a low probability of occurrence of errors. In particular, the flash memory device of the present invention can be provided in a memory system such as an SSD which has been actively studied recently. In this case, the memory controller 2100 may be configured to communicate with an external (e.g., host) through one of a variety of interface protocols such as USB, MMC, PCI-E, SAS, SATA, PATA, SCSI, ESDI, . The memory controller 2100 may further include a configuration for performing a random operation.

 10, a computing system 3000 including a non-volatile memory device 3120 in accordance with the present invention is schematically illustrated. The computing system 3000 according to the present invention includes a modem 3500 electrically coupled to the system bus 3600, a RAM 3300, a user interface 3400, a baseband chipset, Memory system 3100. < / RTI > The memory system 3100 will be configured substantially the same as that shown in FIG. If the computing system 3000 according to the present invention is a mobile device, a battery (not shown) for supplying the operating voltage of the computing system 3000 will additionally be provided. Although it is not shown in the drawing, the computing system 3000 according to the present invention can be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, It is obvious to those who have acquired common knowledge. The memory system 3100 can constitute, for example, a solid state drive (SSD) using nonvolatile memory for storing data. Alternatively, the memory system 3100 may be provided as a fusion flash memory (e.g., a one-nAND flash memory).

Further, the flash memory device or memory system according to the present invention can be mounted in various types of packages. For example, the flash memory device or the memory system according to the present invention may be implemented as a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

As described above, an optimal embodiment has been disclosed in the drawings and specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

FIG. 1 illustrates a threshold voltage distribution of dummy cells according to an embodiment of the present invention; FIG.

2 is a block diagram illustrating a non-volatile memory device according to an embodiment of the present invention;

Figure 3 is a circuit diagram showing the cell array and page buffer of Figure 2;

4 is a flowchart showing a programming method of the present invention;

5 is a table showing a program procedure according to an embodiment of the present invention;

FIG. 6 is a table showing a program procedure according to another embodiment of the present invention; FIG.

Figure 7 is a diagram illustrating an example of the effect of the present invention;

8 is a block diagram illustrating a solid state drive (SSD) including a non-volatile memory device in accordance with an embodiment of the present invention;

Figure 9 is a block diagram illustrating a memory system including a non-volatile memory device in accordance with an embodiment of the present invention; And

10 is a block diagram illustrating a computing system including a non-volatile memory device of the present invention.

Claims (9)

A dummy cell connected to the dummy bit line; A page buffer coupled to the dummy bit line; And And control logic to load dummy data into a page buffer coupled to the dummy bit line such that the dummy cell is programmed to a program state that is lower than the highest program state and higher than the erase state during program operation, In an erase operation, a page buffer coupled to the dummy bit line maintains the dummy bit line in a floating state. The method according to claim 1, Wherein the dummy data is generated in the control logic. The method according to claim 1, Wherein during a program operation, a page buffer coupled to the dummy bit line senses the dummy bit line to verify that the dummy cell is programmed in the program state. The method of claim 3, Wherein the control logic determines whether the dummy cell is programmed in the program state by referring to the sensing result output from the page buffer connected to the dummy bit line. 5. The method of claim 4, Wherein the control logic terminates the program operation of the dummy cell when it is determined that the dummy cell is programmed in the program state. The method according to claim 1, And in a read operation, the data output from the page buffer connected to the dummy bit line is blocked. delete A program method for a non-volatile memory device comprising: Loading dummy data into a page buffer connected to a dummy bit line; And Programming a dummy cell coupled to the dummy bit line, Wherein the dummy data is data for programming the dummy cell to a dummy program state lower than the highest program state and higher than the erase state, Wherein the program operation of the dummy cell is terminated when it is determined that the dummy cell is programmed in the dummy program state. 9. The method of claim 8, Wherein the dummy data is generated and provided inside the nonvolatile memory device.

Images