JP2010008522A5 - - Google Patents
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- JP2010008522A5 JP2010008522A5 JP2008165202A JP2008165202A JP2010008522A5 JP 2010008522 A5 JP2010008522 A5 JP 2010008522A5 JP 2008165202 A JP2008165202 A JP 2008165202A JP 2008165202 A JP2008165202 A JP 2008165202A JP 2010008522 A5 JP2010008522 A5 JP 2010008522A5
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- Prior art keywords
- transistor
- signal
- drive
- type transistor
- display device
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- 238000005070 sampling Methods 0.000 claims 10
- 239000003990 capacitor Substances 0.000 claims 9
- 230000000875 corresponding Effects 0.000 claims 4
- 238000011105 stabilization Methods 0.000 claims 4
- 230000001276 controlling effect Effects 0.000 claims 2
- 230000000087 stabilizing Effects 0.000 claims 1
Claims (6)
前記サンプリングトランジスタを順次制御することで前記画素回路を走査して前記保持容量に映像信号の信号振幅に応じた情報を書き込むための書込走査パルスを同一行の前記サンプリングトランジスタの制御入力端に共通に供給する書込走査部、前記書込走査部での前記走査に合わせて映像信号を同一列の前記サンプリングトランジスタの信号入力端に共通に供給する水平駆動部を具備し、各信号のタイミング制御により前記駆動電流を一定に維持する駆動信号一定化回路が機能するように構成された制御部と
を備え、
前記サンプリングトランジスタは、p型トランジスタとn型トランジスタがトランスファーゲートを構成するように並列接続されており、
前記駆動信号一定化回路は、前記制御部の制御の元で、前記駆動トランジスタの移動度に対する補正分を前記保持容量に書き込まれる信号に加える移動度補正機能を実現するように構成されており、
前記書込走査部は、前記移動度補正動作の開始において同一行のそれぞれの前記p型トランジスタと前記n型トランジスタに供給される各信号電位に対する各オンタイミングのズレ量の小さい方が先にオンするように制御する、および/または、前記移動度補正動作の終了において同一行のそれぞれの前記p型トランジスタと前記n型トランジスタに供給される各信号電位に対する各オフタイミングのズレ量の小さい方が後にオフするように制御する
ことを特徴とする表示装置。 A driving transistor that generates a driving current, a holding capacitor that holds information according to the signal amplitude of a video signal, an electro-optic element disposed on the output end side of the driving transistor, and information that corresponds to the signal amplitude in the holding capacitor And a pixel circuit that emits light from the electro-optic element when the drive transistor generates a drive current based on the information held in the storage capacitor and flows it through the electro-optic element. A pixel array unit,
A write scan pulse for scanning the pixel circuit by sequentially controlling the sampling transistors and writing information corresponding to the signal amplitude of the video signal to the storage capacitor is common to the control input terminals of the sampling transistors in the same row. And a horizontal driving unit for commonly supplying a video signal to the signal input terminals of the sampling transistors in the same column in accordance with the scanning in the writing scanning unit. And a control unit configured to function as a drive signal stabilization circuit that maintains the drive current constant.
The sampling transistor is connected in parallel so that a p-type transistor and an n-type transistor constitute a transfer gate,
The drive signal stabilization circuit is configured to realize a mobility correction function for adding a correction amount for the mobility of the drive transistor to a signal written to the storage capacitor under the control of the control unit,
The writing scanning unit is turned on first when the shift amount of each ON timing with respect to each signal potential supplied to each of the p-type transistor and the n-type transistor in the same row at the start of the mobility correction operation is smaller. And / or at the end of the mobility correction operation, the smaller the offset amount of each off timing with respect to each signal potential supplied to each of the p-type transistor and the n-type transistor in the same row, A display device that is controlled to be turned off later.
ことを特徴とする請求項1に記載の表示装置。 When the mobility correction operation period is defined by a period from when the sampling transistor is turned on to when it is turned off, the writing scanning unit is configured to start the mobility correction operation at each p of the same row. Control is performed such that the one with the smaller shift amount of each on timing with respect to each signal potential supplied to the n-type transistor and the n-type transistor is turned on first, and at the end of the mobility correction operation, 2. The display device according to claim 1, wherein the display device is controlled so that the one with the smaller shift amount of each off timing with respect to each signal potential supplied to the p-type transistor and the n-type transistor is turned off later.
各行の前記サンプリングトランジスタを順番にオン/オフ制御するための基準となるシフトパルスを生成するシフトレジスタ部、
前記シフトレジスタ部から出力されたシフトパルスを共通に使用して、当該シフトパルスと前記ズレ量を規定する前記p型トランジスタ用の制御パルスとの間でゲート処理することで前記p型トランジスタをオン/オフ制御するための第1の書込駆動パルスを生成する第1の出力ゲート部、および前記シフトパルスと前記ズレ量を規定する前記n型トランジスタ用の制御パルスとの間でゲート処理することで前記n型トランジスタをオン/オフ制御するための第2の書込駆動パルスを生成する第2の出力ゲート部
を有することを特徴とする請求項1または請求項2に記載の表示装置。 The writing scanning unit
A shift register unit that generates a shift pulse serving as a reference for sequentially turning on and off the sampling transistors in each row;
The shift pulse output from the shift register unit is commonly used, and the p-type transistor is turned on by performing gate processing between the shift pulse and the control pulse for the p-type transistor that defines the shift amount. Gate processing between the shift pulse and the control pulse for the n-type transistor that defines the shift amount, and a first output gate section for generating a first write drive pulse for off / off control The display device according to claim 1, further comprising: a second output gate unit that generates a second write drive pulse for controlling on / off of the n-type transistor.
前記水平駆動部は、基準電位と信号電位で切り替わる映像信号を前記サンプリングトランジスタの信号入力端に供給するものであり、
前記駆動信号一定化回路は、前記書込走査部、前記水平駆動部、および前記駆動走査部の制御の元で、前記第1電位に対応する電圧が前記駆動トランジスタの前記電源供給端に供給されかつ映像信号における基準電位が前記サンプリングトランジスタの信号入力端に供給されている時間帯で前記サンプリングトランジスタを導通させることで前記駆動トランジスタの閾値電圧に対応する電圧を前記保持容量に保持させる閾値補正機能を実現するように構成されたものである
ことを特徴とする請求項1に記載の表示装置。 A drive scanning unit configured to switch a first potential used to flow a drive current to the electro-optic element and a second potential different from the first potential and supply the first potential to a power supply end of the drive transistor; In addition,
The horizontal drive unit supplies a video signal switched between a reference potential and a signal potential to a signal input terminal of the sampling transistor,
The driving signal stabilizing circuit supplies a voltage corresponding to the first potential to the power supply terminal of the driving transistor under the control of the writing scanning unit, the horizontal driving unit, and the driving scanning unit. And a threshold correction function for holding the voltage corresponding to the threshold voltage of the drive transistor in the holding capacitor by conducting the sampling transistor in a time zone in which a reference potential in the video signal is supplied to the signal input terminal of the sampling transistor. The display device according to claim 1, wherein the display device is configured to realize the following.
ことを特徴とする請求項1に記載の表示装置。 The drive signal stabilization circuit includes a threshold correction function for holding a voltage corresponding to the threshold voltage of the drive transistor in the holding capacitor, and a signal amplitude to the holding capacitor by conducting the sampling transistor after the threshold correction operation. The display device according to claim 1, wherein the display device is configured to realize the mobility correction function when writing information according to the function.
ことを特徴とする請求項1に記載の表示装置。 The drive signal stabilization circuit is configured to realize a bootstrap function by connecting the storage capacitor between a control input terminal of the drive transistor and the drive current output terminal. The display device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008165202A JP2010008522A (en) | 2008-06-25 | 2008-06-25 | Display apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008165202A JP2010008522A (en) | 2008-06-25 | 2008-06-25 | Display apparatus |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010008522A JP2010008522A (en) | 2010-01-14 |
JP2010008522A5 true JP2010008522A5 (en) | 2011-06-23 |
Family
ID=41589152
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2008165202A Pending JP2010008522A (en) | 2008-06-25 | 2008-06-25 | Display apparatus |
Country Status (1)
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JP (1) | JP2010008522A (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5548503B2 (en) * | 2010-03-31 | 2014-07-16 | 株式会社ジャパンディスプレイ | Active matrix display device |
JP6755689B2 (en) | 2016-03-30 | 2020-09-16 | 株式会社Joled | Display device |
JP6706971B2 (en) | 2016-06-02 | 2020-06-10 | 株式会社Joled | Display device |
KR102004359B1 (en) * | 2018-10-19 | 2019-07-29 | 주식회사 사피엔반도체 | Micro Display |
US20220190097A1 (en) * | 2019-04-26 | 2022-06-16 | Sharp Kabushiki Kaisha | Display device |
CN112116896B (en) * | 2020-10-20 | 2021-12-03 | 武汉华星光电半导体显示技术有限公司 | Pixel driving circuit |
CN112185297B (en) * | 2020-10-26 | 2023-12-05 | 京东方科技集团股份有限公司 | Gate driving unit, gate driving method, gate driving circuit and display device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0693622B2 (en) * | 1985-12-25 | 1994-11-16 | 株式会社日立製作所 | Analog switch circuit |
JPH11305741A (en) * | 1998-04-16 | 1999-11-05 | Matsushita Electric Ind Co Ltd | Driving method for active matrix liquid crystal display device |
JP3659247B2 (en) * | 2002-11-21 | 2005-06-15 | セイコーエプソン株式会社 | Driving circuit, electro-optical device, and driving method |
JP2008083107A (en) * | 2006-09-26 | 2008-04-10 | Sony Corp | Display device |
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- 2008-06-25 JP JP2008165202A patent/JP2010008522A/en active Pending
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