JP2010003889A - Semiconductor device, semiconductor integrated circuit device for plasma display driving using the same, and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a lateral IGBT (Insulated Gate Bipolar Transistor) which is formed on an SOI substrate and is large in current density. <P>SOLUTION: In a lateral IGBT structure which has an emitter terminal composed of two or more second conductivity type base layers for one collector terminal, a second conductivity type base layer in an emitter region is covered with a first conductivity type layer having higher density than a drift layer, a gate electrode between two adjacent emitters has a width L1 of ≤4 μm, and further an emitter-electrode lead-out opening between two adjacent gate electrodes has a width L2 of ≤3 μm. Consequently, while a breakdown voltage is maintained, a first conductivity type layer is made high in density to improve the current density. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as an insulated gate bipolar transistor (hereinafter referred to as IGBT), a semiconductor integrated circuit for driving a plasma display using the semiconductor device, and a plasma display device.

  In recent years, high-breakdown-voltage power ICs using SOI substrates have been actively developed because of their small device isolation region and parasitic transistor-free characteristics. The high breakdown voltage power IC to which the present invention is mainly applied is for a plasma display driving semiconductor IC, and the breakdown voltage is 200V class. In the development of this high withstand voltage power IC, improvement of output characteristics of a high withstand voltage output device that directly drives a load is indispensable from the viewpoint of performance improvement and chip size reduction. However, in a lateral IGBT mainly used as an output device of a power IC using an SOI substrate, an emitter / gate region and a collector region are formed in the same plane, so that an area that can be substantially energized is reduced. The current capacity per element area is reduced. In addition, since the lateral IGBT has a large current component in the lateral IGBT, there is a problem that latch-up is likely to occur and the stable operation region of the element is narrow. In consideration of this problem, a lateral IGBT has been developed that increases the current capacity per unit area and has a wide safe operation area.

  From the viewpoint of improving the output of the lateral IGBT, for example, in Patent Document 1, the width L1 of the gate electrode between two adjacent emitters is increased to reduce the resistance between the two adjacent emitters, and the output current It has been proposed to increase the density.

  On the other hand, regarding the improvement of the output of the lateral IGBT, the present inventors have filed an application as Japanese Patent Application No. 2007-108802. The lateral IGBT according to this patent application improves the current density by adopting a configuration as shown in FIG.

  In FIG. 9, a p base region 2 is selectively formed in the surface layer of an n-type semiconductor substrate 1, two n emitter regions 4 are formed in a part of the surface layer of the p base region 2, and the two n A p contact region 3 is formed between the emitter regions 4 so as to partially overlap the n emitter region 4. An n buffer region 9 is selectively formed on the surface exposed portion of the n-type substrate 1 where the p base region 2 is not formed, and a p collector region 10 is formed on the surface layer of the n buffer region 9. A gate electrode 6 connected to the G terminal via the gate oxide film 5 is provided on the surface of the channel region 14 in the surface layer of the p base region 2. Also, an emitter electrode 7 is provided in common contact with the surfaces of the n emitter region 4 and the p contact region 3, and a collector electrode 11 is provided on the surface of the p collector region 10, which are respectively connected to the E terminal and the C terminal. Connected. An oxide film 16 is buried between the n-type substrate 1 and the support substrate 17 of the SOI substrate. In the figure, the right half of the lateral IGBT centering on the left end a-a ′ is shown.

  This structure is characterized in that an n layer 18 having a higher concentration than that of the n-type semiconductor substrate 1 is newly formed so as to cover the p base region in the central portion of the element. In this IGBT, the resistance of the silicon layer between the high-concentration first conductivity type layer 18 covering the newly added emitter region and the buried oxide film 16 is reduced. As a result, a current can flow in the emitter / gate region far from the collector region without increasing the voltage drop, and the current density is improved as compared with the conventional structure.

Japanese Patent No. 3,522,983

  However, in the IGBT having the structure shown in FIG. 9, when the concentration of the n-type impurity in the n-layer 18 having a higher concentration than that of the n-type semiconductor substrate 1 exceeds a certain concentration, the breakdown voltage sharply decreases. There is a limit to improving the current density.

  An object of the present invention is to further improve the output current density in a semiconductor device such as a lateral IGBT.

  In one aspect of the present invention, the second conductivity type base region including the first conductivity type emitter region selectively formed in the surface layer of one main surface of the first conductivity type semiconductor substrate, A gate electrode formed on the conductive type base region via an insulating film, and a second conductive type collector region, and two or more second conductive types between two adjacent second conductive type collector regions In a semiconductor device in which a base region is sandwiched, a first conductivity type that is higher in concentration than the first conductivity type semiconductor substrate between two or more second conductivity type base regions and below these second conductivity type base regions. In addition to forming the region, the width of the gate electrode formed so as to communicate between the two adjacent second conductivity type base regions via the insulating film is 4 μm or less.

  In a preferred embodiment of the present invention, in a lateral IGBT having a withstand voltage of 200 V class, a gate located between two adjacent emitters that becomes a breakdown voltage breakdown point when the n-type impurity concentration of the high-concentration n layer 18 exceeds a certain concentration. In order to alleviate the electric field in the silicon region immediately below the electrode, the width of the gate electrode between two adjacent emitters is reduced.

  In a preferred embodiment of the present invention, in addition to the above, the volume of the high-concentration first conductivity type layer surrounding the p base region is reduced by narrowing the opening width between two adjacent gate electrodes for extracting the emitter electrode. Decrease.

  In a specific embodiment, the width of the gate electrode between two adjacent emitters is set to 4 μm or less, or in addition to that, the opening width for emitter extraction between two adjacent gate electrodes is set to 3 μm or less. Features.

  According to a preferred embodiment of the present invention, a semiconductor device such as a lateral IGBT can increase the impurity concentration of the high-concentration first conductivity type layer that maintains the breakdown voltage, thereby further improving the output current density. it can.

  According to a preferred embodiment of the present invention, n impurities in a high-concentration n region surrounding a p base region can be reduced, and fixation of a potential distribution in the p base region and the n region surrounding the p base region due to depletion is lower. It is possible to reduce the electric field in the silicon region directly under the gate electrode, which occurs due to voltage.

  In addition, by narrowing the emitter extraction opening width between two adjacent gate electrodes, the current path to the collector is shortened and the emitter region is downsized. An electric field is easily applied to a far channel region. For this reason, in addition to the effect of increasing the concentration of the high concentration n layer, the output current density can be improved.

  By improving the current density of the lateral IGBT, a semiconductor integrated circuit for driving a plasma display that requires a high breakdown voltage and a large current can be realized with a smaller chip size.

  Further, even when the output current density is improved by reducing the channel region by suppressing thermal diffusion, the volume of the n region surrounding the p base region is increased. Challenges arise. The present invention is also effective as a solution in that case.

  Other objects and features of the present invention will be clarified in the embodiments described below.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention for improving the performance of a lateral IGBT, improving the output characteristics of a high breakdown voltage power IC, and reducing the chip size will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is a partial cross-sectional structure diagram showing an IGBT according to an embodiment of the present invention. This IGBT has a structure centered on a broken line a-a 'at the left end of the figure, and only the right half is shown.

  In FIG. 1, a p base region 2 is selectively formed on the surface layer of an n-type semiconductor substrate 1. Two n emitter regions 4 are formed in part of the surface layer of the p base region 2, and the p contact region 3 is partially overlapped with the n emitter region 4 between the two n emitter regions 4. Is formed. An n buffer region 9 is selectively formed on the surface exposed portion of the n-type substrate 1 where the p base region 2 is not formed, and a p collector region 10 is formed on the surface layer of the n buffer region 9. A gate electrode 6 connected to the gate (G) terminal via the gate oxide film 5 is provided on the surface of the channel region 14 in the surface layer of the p base region 2. Further, an emitter electrode 7 is provided in common contact with the surfaces of the n emitter region 4 and the p contact region 3, and a collector electrode 11 is provided on the surface of the p collector region 10, which are respectively an emitter (E) terminal, Connected to the collector (C) terminal. An oxide film 16 is buried between the n-type substrate 1 and the support substrate 17 of the SOI substrate. In addition, an n layer 18 having a higher concentration than that of the n-type semiconductor substrate 1 is newly formed so as to cover the p base region in the central portion of the element. As shown in FIG. 1, there are a plurality of p base regions 2, which are separated by an n-type silicon region under the gate electrode 6.

  In this embodiment, the width L1 of the gate electrode between two adjacent emitters of a 200V class IGBT is set to 4 μm or less, or in addition to that, an opening for extracting an emitter electrode between two adjacent gate electrodes is provided. The width L2 is 3 μm or less.

  In the above-described lateral IGBT having a withstand voltage of 200 V in FIG. 9, the phenomenon that the withstand voltage rapidly decreases when the n-type impurity concentration of the high-concentration n layer 18 exceeds a certain concentration has been described. In this lateral IGBT, it was found from the results of device simulation that the breakdown point is in the silicon region immediately below the gate electrode between two adjacent emitters.

  FIG. 2 is a potential distribution diagram in the off state of the semiconductor device of FIG. 9 and shows a breakdown point when the breakdown voltage does not decrease due to the n-type impurity concentration of the high concentration n layer 18. Here, the breakdown point is shown when 0 V is applied to the emitter and gate and 250 V is applied to the collector, and the breakdown point corresponds to a portion where the equipotential lines under the collector are dense (dotted circles in the figure).

  FIG. 3 is a potential distribution diagram in an off state when the n-type impurity concentration of the high-concentration n layer 18 is increased until the breakdown voltage is lowered in the semiconductor device of FIG. 9, and shows the breakdown point in that case. Yes. In FIG. 3, 0 V is applied to the emitter and the gate, and 100 V is applied to the collector, and the electric field in the silicon region immediately below the gate between the two adjacent emitters (broken line in the figure) is the strongest. This is the yield point. As a method of relaxing the electric field in the silicon region directly under the gate electrode between the two adjacent emitters, the interval between the p base regions 2 is narrowed to make it more concave. That is, by narrowing the width of the gate electrode 6 between two adjacent emitter electrodes, the potential fluctuation in the region sandwiched between the two adjacent p base regions 2 can be moderated. Further, when a positive voltage is applied from zero to the collector, the n region surrounding the p base region 2 is depleted in the process of increasing the voltage, and the potential distribution of the p base region 2 and the n region surrounding it is substantially fixed. Most of the collector voltage rise thereafter is applied to the silicon region between the p base region 2 and the p region 10 on the collector side. By fixing the potential distribution of the p base region 2 and the n region 18 surrounding the p base region 2 at a lower voltage, the electric field of the silicon region immediately below the gate electrode between the two adjacent emitters can be reduced. Is possible.

  To summarize the above embodiment, the second conductivity type base region 2 including the first conductivity type emitter region 4 inside selectively formed in the surface layer of one main surface of the first conductivity type semiconductor substrate 1. A gate electrode 6 formed on the second conductivity type base region 2 with an insulating film 5 interposed therebetween, and a second conductivity type collector region 10, and two adjacent second conductivity type collector regions. In the semiconductor device in which two or more second conductivity type base regions 2 are sandwiched between 10, between two or more of the second conductivity type base regions 2 and below these second conductivity type base regions 2. A first conductivity type region 18 having a higher concentration than the first conductivity type semiconductor substrate 1 is formed, and two adjacent second conductivity type base regions 2 are formed to communicate with each other through the insulating film 5. The length of the formed gate electrode 6 is 4 μm or less Characterized in that it was.

  In this embodiment, the width L1 of the gate electrode between two adjacent emitter electrodes is narrowed, and the width L2 of the opening for leading the emitter electrode 7 between the two adjacent gate electrodes 6 is narrowed. Yes. As a result, the volume of the n region surrounding the p base region 2 is reduced, the amount of n-type impurities in the n region surrounding the p base region 2 is reduced, and depletion is performed at a lower collector voltage. As a result, the n-type impurity concentration of the high-concentration n layer 18 can be increased while maintaining the breakdown voltage, and the output current density can be improved.

  FIG. 4 is a characteristic comparison diagram of the semiconductor device according to FIG. 9 and the semiconductor device according to one embodiment of the present invention. 9 shows the results of device simulation of the structure 0 of the lateral IGBT of FIG. 9 with L1 = 6 μm and L2 = 4 μm and the structure 1 of the lateral IGBT of FIG. 1 with L1 = 4 μm and L2 = 4 μm. FIG. 4 is a graph comparing the breakdown voltage and the output current density for the structures 0 and 1 with the n-type impurity concentration implanted to form the high-concentration n layer 18 as a variable (horizontal axis). The limit of the n-type impurity concentration holding the breakdown voltage of the structure 0 is a broken line A, and the limit of the n-type impurity concentration holding the breakdown voltage of the structure 1 is a broken line B. White circles and black circles are displayed at the intersections with the output current density lines corresponding to the broken lines A and B.

  As is clear from FIG. 4, by changing the structure of the lateral IGBT from structure 0 to structure 1, the n-type impurity concentration capable of maintaining the withstand voltage increases, and accordingly, the output current density is improved from the white circle value to the black circle value. Can be made.

  As disclosed in Patent Document 1, there is an idea that by increasing the gate width L1 between two adjacent emitters, the resistance between the two adjacent emitters is lowered and the output current density is improved. . However, in the IGBT having the high-concentration n layer 18, from the viewpoint of improving the trade-off point between the withstand voltage and the output current performance, in the embodiment of the present invention, the width L1 of the gate electrode between the two adjacent emitter electrodes. Alternatively, the width L2 of the opening for extracting the emitter electrode between two adjacent gate electrodes is reduced.

  FIG. 5 is a characteristic comparison diagram of semiconductor devices according to two embodiments of the present invention. Here, by reducing the volume of the n region surrounding the p base region 2, the amount of n-type impurities in the n region surrounding the p base region 2 is reduced. With this method, in addition to the gate electrode width L1 being narrowed, the structure 2 (L1 = 4 μm, L2 = 3 μm) in which the emitter electrode opening width L2 between two adjacent gate electrodes is also narrowed is described. The simulated results are shown in comparison with the structure 1 results.

  Similar to the description of FIG. 4 in which both dimensions L1 and L2 are narrowed, by using structure 2, the limit of the n-type impurity concentration for maintaining the withstand voltage increases from the broken line B to the broken line C, and the output current density is a black circle value. Can be improved to a white circle value.

  From FIG. 4 and FIG. 5, comparing structure 0 and structure 1, the output current density increases by about 40%, and comparing structure 0 and structure 2 increases the output current density by about 60%. . In addition, the output current density is improved more than twice as compared with the case where no additional n-type impurity is implanted into the region n.

  Thus, by improving the current density of the lateral IGBT, a semiconductor integrated circuit for driving a plasma display that requires a high breakdown voltage and a large current can be realized with a smaller chip size.

  FIG. 6 shows a configuration example of an output stage circuit of a plasma display driving semiconductor integrated circuit device to which a lateral IGBT according to an embodiment of the present invention is applied. The output stage circuit 22 has a configuration in which IGBTs 19 and 20 according to an embodiment of the present invention are connected to each other between a power source VH and a ground GND, and a connection point between the IGBTs 19 and 20 is an output terminal HVO. The IGBTs 19 and 20 are ON / OFF controlled by the output stage control circuit 21 to set the output terminal HVO to the voltage levels of VH and GND or a high impedance state.

  FIG. 7 shows a configuration example of a semiconductor integrated circuit device for driving a plasma display to which a lateral IGBT according to an embodiment of the present invention is applied. The plasma display driving semiconductor integrated circuit device 27 includes a shift register circuit 23, a latch circuit 24, a selector 25, and an output stage circuit 26. In the shift register circuit, the control signal input from the terminal DATA is shifted in synchronization with the clock signal input to the terminal CLK. Further, by combining the terminals OC1 and OC2 connected to the selector, all the output terminals are set to the VH level, the GND voltage level, the high impedance state, and the data output state from the latch.

  FIG. 8 is a configuration example of a plasma display device using a semiconductor integrated circuit device for driving a plasma display using a semiconductor device according to an embodiment of the present invention. By configuring the circuit as shown in FIG. 8, the light emitting unit of the plasma display device can be controlled. The semiconductor integrated circuit device according to the embodiment of the present invention can reduce the cost of the plasma display device.

1 is a cross-sectional structure diagram showing a first embodiment of a semiconductor device according to the present invention. It is an electric potential distribution figure in the OFF state of a semiconductor device by prior application technology. FIG. 6 is a potential distribution diagram in an off state when the n-type impurity concentration of the high-concentration n layer is increased until breakdown voltage reduction occurs in the semiconductor device according to the prior application technique. FIG. 6 is a characteristic comparison diagram of a semiconductor device according to an embodiment of the present invention and a prior application technique. It is a characteristic comparison figure of the semiconductor device by two Examples of this invention. It is a structural example of the output stage circuit of the semiconductor integrated circuit device for a plasma display drive using the semiconductor device by one Example of this invention. It is a structural example of the semiconductor integrated circuit device for a plasma display drive using the semiconductor device by one Example of this invention. 1 is a configuration example of a plasma display device using a semiconductor integrated circuit device for driving a plasma display using a semiconductor device according to an embodiment of the present invention. It is sectional structure drawing which shows the semiconductor device by a prior application technique.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate, 2 ... p base region, 3 ... p contact region, 4 ... n emitter region, 5 ... Gate oxide film, 6 ... Gate electrode, 7 ... Emitter electrode, 8 ... Emitter gate region, 9 ... n buffer region, 10 ... p collector region, 11 ... collector electrode, 12 ... collector region, 13 ... drift region, 14 ... channel region, 15 ... region between adjacent emitter and gate regions, 16 ... oxide film of SOI substrate, DESCRIPTION OF SYMBOLS 17 ... Support substrate of SOI substrate, 18 ... N layer, 19 ... Output stage element, 20 ... Output stage element, 21 ... Output stage control circuit, 22 ... Output stage circuit, 23 ... Shift register circuit, 24 ... Latch circuit, 25 ... Selector circuit, 26 ... Semiconductor integrated circuit for driving plasma display.

Claims (4)

In the surface layer of one main surface of the semiconductor substrate of the first conductivity type,
A second conductivity type base region including a first conductivity type emitter region in the selectively formed interior;
A gate electrode formed on the second conductivity type base region via an insulating film; and a second conductivity type collector region, and two or more second conductivity type collector regions between two adjacent second conductivity type collector regions. In a semiconductor device in which a two-conductivity type base region is sandwiched,
Forming a first conductivity type region having a concentration higher than that of the first conductivity type semiconductor substrate between two or more of the second conductivity type base regions and below the second conductivity type base regions;
A semiconductor device, wherein a width of a gate electrode formed so as to communicate between two adjacent second conductivity type base regions through the insulating film is 4 μm or less.   2. The semiconductor device according to claim 1, wherein an emitter electrode is drawn from a gap between the two adjacent gate electrodes, and the gap between the two adjacent gate electrodes is 3 μm or less.   A semiconductor integrated circuit device for driving a plasma display, comprising the semiconductor device according to claim 1.   A plasma display apparatus comprising the semiconductor integrated circuit device for driving a plasma display according to claim 3.

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