JP2010002549A - Driving device for liquid crystal display panel, driving circuit for liquid crystal display panel, liquid crystal display device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving device for a liquid crystal display panel which suppresses occurrence of display defects when operating the liquid crystal display panel by using a plurality of sample hold drivers (SHDs), which are the driver circuits, and to provide an liquid crystal display device and an electronic apparatus provided with the liquid crystal display panel. <P>SOLUTION: Each of the SHDs 12a to 12d includes: an image signal output section for outputting an image signal to be applied to each pixel electrode of a liquid crystal display panel 13 to the liquid crystal display panel 13; and a reference voltage creation section for creating a reference voltage Vcom to be applied on an opposing electrode of the liquid crystal display panel 13. The reference voltage Vcom created by one driving circuit SHD 12a in the reference voltages Vcom created by a plurality of SHDs 12a to 12d, is applied on the opposing electrode of a liquid crystal panel 13. When the reference voltage Vcom is a threshold voltage or more, output of image signals Vsig1 to Vsig48 is started from each image signal output section of SHDs 12a to 12d. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a liquid crystal display panel drive device, a liquid crystal display panel drive circuit, a liquid crystal display device including the same, and an electronic apparatus. More specifically, the present invention relates to a liquid crystal display panel drive circuit that simultaneously writes video signals to a plurality of pixel electrodes of a liquid crystal display panel, a liquid crystal display panel drive device including the same, a liquid crystal display device including the same, and an electronic apparatus.

  Conventionally, as a display element, a liquid crystal display device (Liquid crystal display) having a liquid crystal display panel in which a plurality of pixels composed of a liquid crystal cell in which a liquid crystal layer is provided between a pixel electrode and a counter electrode is arranged in a matrix is widely used. It has been.

  In this liquid crystal display device, gradation display in a pixel is realized by applying a predetermined value (for example, 5.5 V) or less between a pixel electrode and a counter electrode of a liquid crystal display panel. That is, the video signal Vsig corresponding to the gradation of the image is applied to the pixel electrode, and the reference voltage Vcom is applied to the counter electrode to perform writing to the pixel, thereby displaying an image on each pixel.

  In general, the writing speed to each pixel is not so fast that the input video signal Vsig can be sequentially written for each dot (one pixel), so the video signal Vsig is written in parallel in a plurality of pixels in the horizontal direction. A method is employed (see, for example, Patent Document 1). In this type of liquid crystal display device, in order to write a video signal in parallel to a plurality of pixels of a liquid crystal display panel, a sample-and-hold that converts a video signal input sequentially in time series into a parallel signal for a plurality of pixels A driver (hereinafter also referred to as “SHD”) is used.

  Hereinafter, a conventional liquid crystal display device employing a multiple pixel simultaneous writing method will be described with reference to the drawings. FIG. 12 is a schematic diagram for explaining a conventional liquid crystal display device adopting a multi-pixel simultaneous writing method, FIG. 13 is an explanatory diagram of a conventional method for controlling the rise of a video signal and a reference voltage, and FIG. 14 is a conventional liquid crystal display device. It is a figure which shows the relationship between the video signal of a display apparatus, and a reference voltage.

  As shown in FIG. 12, a conventional liquid crystal display device 200 includes a data processing / timing signal generation circuit (hereinafter referred to as “DSD / TG”) 201, a sample-and-hold driver (SHD) 202, and an N-phase liquid crystal. And a display panel 203.

  The video signal DA generated by the DSD / TG 201 is input to the SHD 202. In the SHD 202, the video signal DA that is sequentially input in time series is subjected to parallel processing and developed into the N phase to generate the video signals Vsig1 to VsigN and the reference voltage Vcom. The video signals Vsig1 to VsigN generated by the SHD 202 are applied to each pixel electrode of the N-phase liquid crystal display panel 203, and the reference voltage Vcom generated by the SHD 202 is applied to the counter electrode of the N-phase liquid crystal display panel 203, thereby The video signal is written to the.

  Here, it is assumed that the liquid crystal display panel 203 of the liquid crystal display device 200 shown in FIG. 12 is a 12-phase development 12-phase liquid crystal display panel, and the SHD 202 is a 12-phase development sample-hold driver. At this time, when the video signal DA input from the DSD / TG 201 is sampled and held in the SHD 202, parallel processing is performed to convert it into 12 parallel video signals Vsig1 to Vsig12 so that the same timing is obtained for 12 pixels. To do. Thus, the video signal DA is input to the liquid crystal display panel 203 in a state of being converted into 12 parallel video signals Vsig1 to Vsig12, so that the video signals are written in parallel to 12 signal lines in a time corresponding to 12 pixels. Yes.

  By the way, in the liquid crystal display panel, the load of the counter electrode is larger than the load of the pixel electrode. In general, a capacitor (10 μF in the example shown in FIG. 12) is added to the reference voltage Vcom for driving the counter electrode in order to suppress the voltage fluctuation. Therefore, when the power to the liquid crystal display device 200 is turned on (when the power is turned on), the rise time of the reference voltage Vcom is later than the rise time of the video signal Vsig input to the liquid crystal display panel. As described above, when the rise time of the reference voltage Vcom is slower than the video signal Vsig, a large voltage is applied to the liquid crystal of the pixel, and a display defect called a stripe domain occurs.

  As a countermeasure against such a stripe domain, for example, the following Patent Document 2 proposes a method for controlling the rise of the video signal Vsig and the reference voltage Vcom. That is, as shown in FIG. 13, the timing of outputting the video signal Vsig is delayed by a predetermined time Ts (Vsig ′ → Vsig), thereby suppressing the occurrence of a potential difference from the reference voltage Vcom. However, with this measure, it is necessary to accurately grasp the rising time constants of the video signal Vsig and the reference voltage Vcom that differ depending on the load of the liquid crystal display panel. Therefore, it is necessary to grasp the rise time constant according to the liquid crystal display panel, which leads to an increase in development cost.

Therefore, in the conventional SHD 202, as shown in FIG. 14, after the power is turned on (see timing t11), the voltage of the reference voltage Vcom applied to the counter electrode of the liquid crystal display panel 203 is monitored. The SHD 202 controls to output the video signal Vsig when the reference voltage Vcom exceeds a preset threshold voltage Vr (for example, 6.5 V) (see timing at t12).
JP 2007-279171 A JP 2003-280612 A

  However, when the liquid crystal display panel is operated using a plurality of conventional SHDs, the following problems occur. FIG. 15 is a configuration diagram of a liquid crystal display device that operates a liquid crystal display panel using a plurality of conventional SHDs, and FIG. 16 is a diagram showing a relationship between a video signal and a reference voltage of the liquid crystal display device shown in FIG.

  For example, as shown in FIG. 15, when 48 Vsig1 to Vsig48 are input from four SHDs 212a to 212d to the liquid crystal display panel 213, only the output of one SHD 212a is input to the liquid crystal display panel 213 for the reference voltage Vcom. It will be.

  At this time, since each SHD controls the output of the video signal Vsig when the reference voltage Vcom generated by each exceeds the threshold voltage, if the rising of the reference voltage Vcom generated by each SHD is different, the stripe domain is changed. May occur. In particular, in the configuration shown in FIG. 15, since the counter electrode of the liquid crystal display panel 213 is connected as a load only to the output of the SHD 212a, the rise of the reference voltage Vcom of the SHD 212b to SHD 212d is faster than that of the SHD 212a. As a result, a voltage difference increases between the reference voltage Vcom applied to the liquid crystal display panel 213 and the voltages Vsig13 to Vsig48 output from the SHDs 212b to SHD212d, and a stripe domain may occur.

  Therefore, capacitors C10a to C10d (for example, 10 μF) having a capacity load sufficiently larger than the load of the counter electrode of the liquid crystal display panel 213 are connected to the Vcom terminals of the SHDs 212a to 212d, respectively, so that the rise of each reference voltage Vcom is shifted. Suppressed.

  However, since the capacitors C10a to C10d require a large capacity (for example, 10 μF), there are problems such as generation of extra component costs and expansion of the circuit mounting area.

  In addition, since the capacitors have capacity variations due to individual differences and temperatures, for example, as shown in FIG. 16, the rising of the reference voltage Vcom occurs between the SHDs 212a to 212d. At this time, for example, video signals Vsig37 to Vsig48 are output from the SHD 212d (see timing t22) before the reference voltage Vcom of the SHD 212a rises to the threshold voltage Vr. At this time, since the reference voltage Vcom (reference voltage Vcom of the SHD 212a) input to the liquid crystal display panel 213 is not a sufficient voltage, a large potential difference is generated between the video signals Vsig25 to Vsig48, and stripe domains are formed. May occur.

  Accordingly, in order to solve such a problem, the invention according to claim 1 is a driving device for a liquid crystal display panel provided with a plurality of driving circuits for simultaneously writing video signals to a plurality of pixel electrodes of the liquid crystal display panel. A circuit for outputting a video signal to be applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line; and generating a reference voltage to be applied to the counter electrode of the liquid crystal display panel. A reference voltage generated by one drive circuit among reference voltages generated by the plurality of drive circuits is applied to the counter electrode of the liquid crystal display panel, and the applied reference voltage is a threshold voltage. When it becomes above, the output of the said video signal is started from the video signal output part of each said drive circuit.

  According to a second aspect of the present invention, in the liquid crystal display panel driving device according to the first aspect, each of the driving circuits inputs a reference voltage generated by a reference voltage generating unit of the internal or other driving circuit. An input terminal; and a voltage comparison unit that compares the reference voltage input to the input terminal with the threshold voltage, and the video signal when the reference voltage input to the input terminal is equal to or higher than the threshold voltage. The output of the video signal is started from the output unit.

  According to a third aspect of the present invention, in the liquid crystal display panel driving device according to the first aspect, each of the driving circuits compares the reference voltage generated by the reference voltage generating unit with the threshold voltage. A comparison unit, an input terminal for inputting a comparison result of a voltage comparison unit of another drive circuit, a first mode that operates based on a comparison result by an internal voltage comparison unit, and an operation based on an input to the input terminal And a mode setting unit for setting the second mode to output the video signal from the video signal output unit based on a detection result of an internal voltage comparison unit when the first mode is set. When the second mode is set, the video signal output unit starts to output the video signal based on the input to the input terminal.

  According to a fourth aspect of the present invention, in the liquid crystal display panel driving device according to any one of the first to third aspects, each of the video signal output units has a reference voltage applied to the liquid crystal display panel. A predetermined DC voltage is output to the liquid crystal display panel through the signal line until the threshold voltage is exceeded.

  According to a fifth aspect of the present invention, in the liquid crystal display panel driving device according to any one of the first to third aspects, each of the video signal output units has a reference voltage applied to the liquid crystal display panel. The reference voltage is output to the liquid crystal display panel through the signal line until the threshold voltage is exceeded.

  The invention according to claim 6 is a liquid crystal display device comprising a liquid crystal display panel and a plurality of drive circuits for simultaneously writing video signals to a plurality of pixel electrodes of the liquid crystal display panel. A video signal output unit that outputs a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line; a reference voltage generation unit that generates a reference voltage applied to the counter electrode of the liquid crystal display panel; A reference voltage generated by one drive circuit among the reference voltages generated by the plurality of drive circuits is applied to the counter electrode of the liquid crystal display panel, and the applied reference voltage is equal to or higher than a threshold voltage. Output of the video signal is started from the video signal output unit of each drive circuit.

  According to a seventh aspect of the present invention, there is provided an electronic apparatus including a liquid crystal display device having the liquid crystal display panel and a plurality of drive circuits for simultaneously writing video signals to a plurality of pixel electrodes of the liquid crystal display panel. The drive circuit includes: a video signal output unit that outputs a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line; and a reference that generates a reference voltage applied to the counter electrode of the liquid crystal display panel. A reference voltage generated by one drive circuit among the reference voltages generated by the plurality of drive circuits is applied to the counter electrode of the liquid crystal display panel, and the applied reference voltage is When the voltage becomes equal to or higher than the threshold voltage, the output of the video signal is started from the video signal output unit of each drive circuit.

  According to an eighth aspect of the present invention, in the liquid crystal display panel drive circuit, a video signal output unit that outputs a video signal to be applied to the plurality of pixel electrodes to the liquid crystal display panel through a signal line, and the liquid crystal A reference voltage generating unit that generates a reference voltage to be applied to the counter electrode of the display panel, and the reference voltage applied to the liquid crystal display panel is input when the reference voltage is generated by the reference voltage generating unit; When the reference voltage applied to the liquid crystal display panel is a reference voltage generated by another device, the input terminal for inputting the voltage, and the voltage for comparing the voltage input to the input terminal with a preset threshold voltage A comparison unit, and when the voltage input to the input terminal becomes equal to or higher than the threshold voltage, the video signal output unit starts outputting the video signal.

  According to a ninth aspect of the present invention, in the liquid crystal display panel drive circuit, a video signal output unit that outputs a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel through a signal line; and the liquid crystal A reference voltage generation unit that generates a reference voltage to be applied to the counter electrode of the display panel, a voltage comparison unit that compares the reference voltage generated by the reference voltage generation unit with a preset threshold voltage, and voltages of other drive circuits An input terminal that inputs an output of the comparison unit, a first mode that operates based on an input to the input terminal, and a second mode that operates based on an output from a reference voltage generation unit of another drive circuit are set. A mode setting unit, and when the first mode is set, the video signal output unit starts to output the video signal based on the detection result of the voltage comparison unit and sets the second mode. The When and is for starting the output of the video signal from the video signal output unit based on the input to the input terminal.

  According to the present invention, a reference voltage generated by one drive circuit is applied to the counter electrode of the liquid crystal display panel, and when the applied reference voltage is equal to or higher than a threshold voltage, an output of a video signal from each drive circuit is performed. Start. Therefore, the voltage difference between the reference voltage input to the liquid crystal display panel and various signals can be suppressed, and the occurrence of stripe domains can be prevented.

  Hereinafter, some embodiments of the present invention will be described with reference to the drawings.

[1. First Embodiment]
First, the liquid crystal display device of the first embodiment will be described. FIG. 1 is a schematic configuration diagram of a liquid crystal display device 1 according to the first embodiment, and FIG. 2 is a diagram illustrating a relationship between a video signal and a reference voltage of the liquid crystal display device 1 according to the first embodiment.

  As shown in FIG. 1, the liquid crystal display device 1 of the first embodiment includes a data processing / timing signal generation circuit (DSD / TG) 11 and a plurality of sample and hold drivers (hereinafter referred to as “SHD”). 12a to 12d and a liquid crystal display panel 13 are provided. A device having at least SHDs 12a to 12d corresponds to an example of a liquid crystal display panel driving device of the present invention, and each SHD 12a to 12d corresponds to an example of a liquid crystal display panel driving circuit or a driving circuit of the present invention.

  The DSD / TG 11 is a circuit that generates video signals DA1 to DA4 and outputs the video signals DA1 to DA4 to the SHDs 12a to 12d, respectively.

  The SHDs 12a to 12d perform parallel processing on the video signals DA1 to DA4 that are sequentially input from the DSD / TG 11, and generate the video signal Vsig developed in 12 phases, and the video signal Vsig is transmitted via the signal line. Output to the liquid crystal display panel 13. Further, the SHDs 12a to 12d generate a reference voltage Vcom (7V in this case) to be supplied to the counter electrode of the liquid crystal display panel 13, and output the reference voltage Vcom from the VcomOUT terminal to the liquid crystal display panel 13 through a signal line.

  The SHD 12a generates video signals Vsig1 to Vsig12 from DA1, and the SHD 12b generates video signals Vsig13 to Vsig24 from DA2. The SHD 12c generates video signals Vsig25 to Vsig36 from DA3, and the SHD12d generates video signals Vsig37 to Vsig48 from DA4.

  As described above, each of the SHDs 12a to 12d applies the video signal applied to the pixel electrode of the liquid crystal display panel 13 to the liquid crystal display panel 13 via the signal line, and applies to the counter electrode of the liquid crystal display panel 13. Functions as a reference voltage generation unit that generates a reference voltage Vcom to be used.

  The liquid crystal display panel 13 is a 48-phase liquid crystal display panel (LCD) in which a plurality of pixels composed of a liquid crystal cell in which a liquid crystal layer is provided between a pixel electrode and a counter electrode are arranged in a matrix and 48 pixels can be written simultaneously. It is. The video signals Vsig1 to Vsig48 generated by the SHDs 12a to 12d are simultaneously applied to the pixel electrodes of 48 pixels through 48 signal lines to perform simultaneous writing to the 48 pixels.

  Further, the reference voltage Vcom is input to the counter electrode of the liquid crystal display panel 13 from the VcomOUT terminal of one SHD 12a through one signal line. Further, the VcomIN terminal of the other SHD12b to SHD12d is connected to the VcomOUT terminal of the SHD12a, and the reference voltage Vcom generated by the SHD12a is input to the SHD12b to SHD12d. Note that the capacitor C1 is connected to the VcomOUT terminal of the SHD 12a. The capacitor C1 is a capacitor for adjusting the timing of outputting the video signals Vsig1 to 48 from the SHDs 12a to 12d and suppressing the voltage fluctuation of the VcomOUT terminal. .

  Here, each of the SHDs 12a to 12d is provided with a voltage comparison unit that compares the voltage at the VcomIN terminal with a threshold voltage Vr, which will be described later, and the video signal when the voltage at the VcomIN terminal becomes equal to or higher than the threshold voltage Vr. The output of Vsig is started.

  The reference voltage Vcom generated by the SHD 12a and input to the liquid crystal display panel 13 is applied to the VcomIN terminals of the SHDs 12a to 12d.

  Therefore, when the reference voltage Vcom input to the liquid crystal display panel 13 is lower than the threshold voltage Vr, the video signals Vsig1 to Vsig48 are not output from the SHDs 12a to 12d.

  As a result, application of a large voltage to the liquid crystal of the pixels of the liquid crystal display panel 13 can be suppressed, and the occurrence of stripe domains can be prevented.

  In addition, since it is not necessary to connect a capacitor having a large capacity to the VcomOUT terminals of the SHDs 12a to 12d, problems such as variations in capacitor capacity, generation of extra component costs, and an increase in circuit mounting area can be avoided.

  Hereinafter, a specific configuration of the SHDs 12a to 12d will be specifically described with reference to FIG. FIG. 3 is a block diagram of a sample and hold driver (SHD). Since the SHDs 12a to 12d have the same configuration, the configuration of the SHD 12a will be described as an example here. Further, the description will focus on the part related to the characteristic part of the functions of the SHD 12a.

  As shown in FIG. 3, the SHD 12a includes a sample hold decoder circuit 20, a Vsig halftone data generation circuit 21, a Vsig-DAC input selection circuit 22, a Vsig-DAC circuit 23, and a Vsig alternating circuit 24 (video). Corresponding to an example of a signal output unit).

  The sample hold decoder 20 receives the serial digital video signal DA1 [11: 0] from the DSD / TG 11 and develops it into 12 parallel data (12-phase development). The sample hold decoder circuit 20 outputs the 12-phase expanded data to the Vsig-DAC input selection circuit 22 at a timing based on a control signal (not shown).

  Also, the Vsig halftone data generation circuit 21 generates halftone data (here, data corresponding to 5 V as the voltage value of the video signal Vsig), and Vsig− at a timing based on a control signal (not shown). The data is output to the DAC input selection circuit 22.

  The Vsig-DAC input selection circuit 22 receives data output from the sample hold decoder circuit 20 and halftone data from the Vsig halftone data generation circuit 21 based on a status signal St output from a Vcom voltage comparison circuit 52 described later. Select one of these. Then, the Vsig-DAC input selection circuit 22 outputs the data thus selected to the Vsig-DAC circuit 23.

  The Vsig-DAC circuit 23 converts the data output from the Vsig-DAC input selection circuit 22 into an analog signal, and outputs the analog signal to the liquid crystal display panel 13 from the Vsig AC circuit 24 via a signal line.

  Further, as shown in FIG. 3, the SHD 12a includes a Psig normal data generation circuit 30, a Psig halftone data generation circuit 31, a Psig-DAC input selection circuit 32, a Psig-DAC circuit 33, and a Psig alternating circuit 34. And have.

  The Psig normal data generation circuit 30 generates a precharge signal for precharging the liquid crystal display panel 13 and outputs it to the Psig-DAC input selection circuit 32 at a timing based on a control signal (not shown).

  Further, the Psig halftone data generation circuit 31 generates halftone data (here, data corresponding to 5 V as the voltage value of the precharge signal Psig), and Psig at a timing based on a control signal (not shown). Output to the DAC input selection circuit 32.

  The Psig-DAC input selection circuit 32 receives the data output from the Psig normal data generation circuit 30 and the halftone data from the Psig halftone data generation circuit 31 based on a status signal St output from the Vcom voltage comparison circuit 52 described later. Select one of them. Then, the Psig-DAC input selection circuit 32 outputs the data thus selected to the Psig-DAC circuit 33.

  The Psig-DAC circuit 33 converts the data output from the Psig-DAC input selection circuit 32 into an analog signal, and outputs it from the Psig AC circuit 34 via a signal line.

  In addition, the SHD 12a includes a timing generator (TG) 40 and an FRP selection circuit 41 as shown in FIG. The timing generator 40 outputs to the FRP selection circuit 41 a polarity inversion signal FRP for alternating the video signals Vsig1 to Vsig12 and the precharge signal Psig. The FRP selection circuit 41 selects any one of a status signal St and a polarity inversion signal FRP output from a Vcom voltage comparison circuit 52 described later, and outputs the selected signal to the Vsig AC circuit 24 and the Psig AC circuit 34. When the polarity inversion signal FRP is input, the Vsig AC circuit 24 and the Psig AC circuit 34 convert the input analog signal into an AC signal and output it.

  Here, as shown in FIG. 3, the SHD 12a in this embodiment further includes a Vcom voltage generation circuit 50 (corresponding to an example of a reference voltage generation unit), a Vcom threshold voltage setting circuit 51, a Vcom voltage comparison circuit 52 (voltage). Equivalent to an example of a comparison unit).

  The Vcom voltage generation circuit 50 is a circuit that generates a reference voltage Vcom and outputs the reference voltage Vcom to the VcomOUT terminal. The Vcom threshold voltage setting circuit 51 generates and outputs a predetermined threshold voltage Vr (here, 6.5 V). Circuit.

  The Vcom voltage comparison circuit 52 compares the reference voltage Vcom generated by the Vcom voltage generation circuit 50 with the voltage at the VcomIN input terminal (corresponding to an example of an input terminal), and outputs the result as a status signal St. Here, the VcomOUT terminal is connected to the VcomIN input terminal of the SHD 12a. Therefore, the Vcom voltage comparison circuit 52 compares the reference voltage Vcom generated by the Vcom voltage generation circuit 50 with the threshold voltage Vr generated by the Vcom threshold voltage setting circuit 51, and outputs the result as a status signal St. The Vcom voltage comparison circuit 52 outputs an L level signal as the state signal St when the reference voltage Vcom is lower than the threshold voltage Vr, and as the state signal St when the reference voltage Vcom is a voltage level equal to or higher than the threshold voltage Vr. An H level signal is output.

  The reference voltage Vcom generated by the Vcom voltage generation circuit 50 is lower than the threshold voltage Vr when the power supply to the SHD 12a is turned on, that is, when application of the power supply voltage to the SHD 12a is started (see timing t1 shown in FIG. 2). Voltage. Therefore, the Vcom voltage comparison circuit 52 outputs an L level signal as the status signal St.

  When the status signal St is an L level signal, the Vsig-DAC input selection circuit 22 selects halftone data output from the Vsig halftone data generation circuit 21 as an output signal as described above. Therefore, the halftone data is converted into an analog signal by the Vsig-DAC circuit 23 and input to the Vsig AC circuit 24.

  When the status signal St is an L level signal, the Psig-DAC input selection circuit 32 selects halftone data output from the Psig halftone data generation circuit 31 as an output signal as described above. Therefore, the halftone data is converted into an analog signal by the Psig-DAC circuit 33 and input to the Psig AC circuit 34.

  Furthermore, when the state signal St is an L level signal as described above, the FRP selection circuit 41 selects the state signal St that is an L level signal, and sends it to the Vsig AC circuit 24 and the Psig AC circuit 34. Output.

  Therefore, both the Vsig alternating circuit 24 and the Psig alternating circuit 34 output a constant level of DC voltage. That is, since the Vsig halftone data set to a DC voltage value of 5V is input to the Vsig AC circuit 24, the DC voltage of 5V is output from the Vsig AC circuit 24. Similarly, since Psig halftone data set to a DC voltage value of 5 V is input to the Psig AC circuit 34, a DC voltage of 5 V is output from the Psig AC circuit 34.

  As described above, when the power to the SHD 12a is turned on, an L level signal is output as the status signal St from the Vcom voltage comparison circuit 52, and a DC voltage of 5V, which is a predetermined voltage, is output from the Vsig AC circuit 24 and the Psig AC circuit 34. It is output to the liquid crystal display panel 13 via a line.

  This state continues until the reference voltage Vcom generated by the Vcom voltage generation circuit 50 becomes equal to or higher than the threshold voltage Vr.

  As shown in FIG. 1, the reference voltage Vcom is input from the SHD 12a to the Vcom IN of the SHDs 12b to 12d, and the threshold voltage Vr generated by the Vcom voltage generation circuit 50 of each of the SHDs 12b to 12d is the same as that of the SHD 12a (here Is 6.5V). Accordingly, the states of the SHDs 12b to 12d are the same as the state of the SHD 12a.

  That is, a DC voltage of 5 V is supplied from the Vsig AC circuit 24 and the Psig AC circuit 34 through the signal line until the reference voltage Vcom generated by the SHD 12a becomes equal to or higher than the threshold voltage Vr after the power to the SHDs 12a to 12d is turned on. And output to the liquid crystal display panel 13.

  Thereafter, when the reference voltage Vcom generated by the Vcom voltage generation circuit 50 of the SHD 12a becomes equal to or higher than the threshold voltage Vr, an H level signal is output from the Vcom voltage comparison circuit 52 as the state signal St. Therefore, the Vsig alternating circuit 24 and the Psig alternating circuit 34 output the converted video signals Vsig1 to Vsig12 and the precharge signal Psig to the liquid crystal display panel 13 through signal lines.

  As described above, since the reference voltage Vcom is input from the SHD 12a to the Vcom IN of the SHDs 12b to 12d, the states of the SHDs 12b to 12d are the same as the state of the SHD 12a.

  That is, when the reference voltage Vcom generated by the SHD 12a becomes equal to or higher than the threshold voltage Vr, the video signals Vsig1 to Vsig48 and the precharge signal Psig are transmitted from the Vsig alternating circuit 24 and the Psig alternating circuit 34 to the liquid crystal display panel 13 through signal lines. Is output.

  As described above, the liquid crystal display device 1 according to the first embodiment includes a plurality of sample-and-hold drivers (SHD) that are drive circuits for simultaneously writing video signals to a plurality of pixel electrodes of the liquid crystal display panel 13. This SHD is provided with a VcomOUT terminal for outputting the generated reference voltage Vcom and a VcomIN terminal as an input terminal for inputting the reference voltage Vcom generated by another SHD. The operation is based on a voltage comparison between the voltage applied to the VcomIN terminal and the threshold voltage Vr. That is, when the voltage applied to the VcomIN terminal is equal to or lower than the threshold voltage Vr, instead of the video signal Vsig and the precharge signal Psig, a predetermined DC voltage that falls within a predetermined voltage range of the reference voltage Vcom is output via the signal line. Thus, the occurrence of a stripe domain is prevented. On the other hand, when the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, the normal video signal Vsig and the precharge signal Psig are output.

  Therefore, the supply of the reference voltage Vcom from the VcomOUT terminal of one SHD 12a to the liquid crystal display panel 13 and the input of the reference voltage Vcom to the VcomIN terminals of all the SHDs 12a to 12d can prevent the occurrence of a stripe domain. .

  That is, the reference voltage Vcom generated by one SHD 12 a among the reference voltages Vcom generated by the plurality of SHDs 12 a to 12 d is applied to the counter electrode of the liquid crystal display panel 13. Then, when the applied reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, output of the signals Vsig and Psig is started from each of the SHDs 12a to 12d. Therefore, the voltage difference between the reference voltage Vcom input to the liquid crystal display panel 13 and various signals can be suppressed, and the occurrence of stripe domains can be prevented.

  As a result, the capacitors (for example, C10b to C10d in FIG. 15) necessary for the conventional SHD can be deleted, and the component cost and the circuit mounting area can be reduced.

  In addition, the timing is set by the capacitor C1 connected to one SHD, and it is possible to suppress the deviation of the switching timing of the signals Vsig and Psig caused by the capacitance variation of the capacitor, thereby reducing the risk of stripe domain occurrence. it can.

  Furthermore, since it is only necessary to add a VcomIN terminal to the conventional SHD, it is possible to expect reductions in SHD development man-hours and development costs.

[2. Second Embodiment]
Next, a liquid crystal display device according to a second embodiment will be described. The liquid crystal display device of the second embodiment is different only in the SHD circuit configuration, and the connection between the SHDs and other configurations are the same as those of the liquid crystal display device of the first embodiment, so only the SHD configuration will be described here. . Further, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  FIG. 4 is a diagram showing the configuration of the SHD in the liquid crystal display device of the second embodiment, and FIG. 5 is a diagram showing the relationship between the video signal and the reference voltage of the liquid crystal display device in the second embodiment. As shown in FIG. 4, in the SHD 12a ′ of the second embodiment, the Vsig halftone data generation circuit 21, the Vsig-DAC input selection circuit 22, the Psig halftone data generation circuit 31, and the Psig-DAC of the SHD 12a of the first embodiment. There is no portion corresponding to the input selection circuit 32.

  Instead, the Vsig alternating circuit 24 ′ (corresponding to an example of the video signal output unit) and the Psig alternating circuit 34 ′ receive the state signal St output from the Vcom voltage comparison circuit 52, and further, a Vcom voltage generation circuit. 50 reference voltages Vcom are input.

  Then, when the L level state signal St is input from the Vcom voltage comparison circuit 52, the Vsig alternating circuit 24 'outputs the reference voltage Vcom input from the Vcom voltage generation circuit 50 instead of the video signal Vsig. When the H level state signal St is input from the Vcom voltage comparison circuit 52, the signal input from the Vsig-DAC circuit 23 is output as the video signal Vsig. When the state signal St is at the H level, the polarity inversion signal FRP is input to the Vsig AC circuit 24 ′. Therefore, the Vsig AC circuit 24 ′ converts the signal input from the Vsig-DAC circuit 23 into an AC video. Output as signal Vsig.

  Similarly, when the L level state signal St is input from the Vcom voltage comparison circuit 52, the Psig alternating circuit 34 'outputs the reference voltage Vcom input from the Vcom voltage generation circuit 50. When the H level state signal St is input from the Vcom voltage comparison circuit 52, the signal input from the Psig-DAC circuit 33 is output as the precharge signal Psig. Since the polarity inversion signal FRP is input to the Psig AC circuit 34 ′ when the status signal St is at the H level, the Psig AC circuit 34 ′ converts the signal input from the Psig-DAC circuit 33 into an AC signal and outputs the signal. Output as the charge signal Psig.

  Therefore, as shown in FIG. 5, the SHD 12 ′ of the second embodiment outputs the reference voltage Vcom instead of the video signal Vsig and the precharge signal Psig when the voltage applied to the VcomIN terminal is equal to or lower than the threshold voltage Vr. This prevents the occurrence of stripe domains. On the other hand, when the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, the normal video signal Vsig and the precharge signal Psig are output.

  As a result, the capacitors (for example, C10b to C10d in FIG. 15) necessary for the conventional SHD can be deleted, and the component cost and the circuit mounting area can be reduced.

  In addition, compared with the SHD of the first embodiment, the SHD of the second embodiment does not apply a DC voltage to the liquid crystal of the pixels of the liquid crystal display panel 13 when the power is turned on. Degradation can be reduced.

  Furthermore, compared to the SHD of the first embodiment, in the SHD of the second embodiment, the Vsig halftone data generation circuit 21, the Vsig-DAC input selection circuit 22, the Psig halftone data generation circuit 31, and the Psig-DAC input selection circuit 32 are used. Is not provided. Therefore, it is possible to reduce the cost due to the effect of reducing the circuit mounting area.

  Similarly to the first embodiment, the timing is set by the capacitor C1 connected to one SHD, and the shift of the switching timing of the signals Vsig and Psig caused by the capacitance variation of the capacitor is suppressed. . Therefore, the risk of stripe domain occurrence can be reduced. In addition, since it is only necessary to add a VcomIN terminal to the conventional SHD, it can be expected that the development man-hour and development cost of the SHD are reduced.

[3. Third Embodiment]
Next, a liquid crystal display device according to a third embodiment will be described. FIG. 6 is a schematic configuration diagram of the liquid crystal display device 1 ′ in the third embodiment, and FIG. 7 is a diagram showing the relationship between the video signal and the reference voltage of the liquid crystal display device 1 ′ in the third embodiment.

  As shown in FIG. 6, the liquid crystal display device 1 ′ according to the third embodiment includes a data processing / timing signal generation circuit (DSD / TG) 11, a plurality of sample and hold drivers (SHD) 62a to 62d, and a liquid crystal And a display panel 13. Note that the configurations of the DSD / TG 11 and the liquid crystal display panel 13 are the same as those in the first embodiment, and a description thereof will be omitted. A device having at least SHDs 62a to 62d corresponds to an example of a driving device for a liquid crystal display panel of the present invention, and each SHD 62a to 62d corresponds to an example of a driving circuit or a driving circuit for a liquid crystal display panel of the present invention.

  The SHDs 62a to 62d output the video signal Vsig that has been subjected to parallel processing on the video signals DA1 to DA4 that are sequentially input from the DSD / TG 11 and expanded into 12 phases. The SHD 62a generates video signals Vsig1 to Vsig12 from DA1, and the SHD 62b generates video signals Vsig13 to Vsig24 from DA2. The SHD 62c generates video signals Vsig25 to Vsig36 from DA3, and the SHD 62d generates video signals Vsig37 to Vsig48 from DA4. Further, the SHDs 62a to 62d generate a reference voltage Vcom (here, 7V) to be supplied to the counter electrode and output it from the VcomOUT terminal.

  As described above, each of the SHDs 62 a to 62 d includes the video signal output unit that outputs the video signal Vsig applied to each pixel electrode of the liquid crystal display panel 13 to the liquid crystal display panel 13 and the reference voltage applied to the counter electrode of the liquid crystal display panel 13. It functions as a reference voltage generation unit that generates Vcom. The capacitor C1 is connected to the VcomOUT terminal of the SHD 62a. The capacitor C1 is a capacitor for adjusting the timing of outputting the video signals Vsig1 to 48 from the SHDs 62a to 62d and suppressing the voltage fluctuation of the VcomOUT terminal. .

  Further, each of the SHDs 62a to 62d is provided with an STBY-I / O terminal (standby input / output terminal: corresponding to an example of an input terminal), and the STBY-I / O terminals of the SHDs 62a to 62d are connected to each other. The STBY-I / O terminal functions as an input terminal and an output terminal depending on the setting. Here, the STBY-I / O terminal of the SHD 62a that supplies the reference voltage Vcom to the liquid crystal display panel 13 is set as an output terminal, and the STBY-I / O terminals of the other SHDs 62b to 62d are set as input terminals.

  Here, each of the SHDs 62a to 62d is provided with a voltage comparison unit that compares the voltage of the reference voltage Vcom generated by each of the SHDs 62a to 62d with a threshold voltage Vr (described below, for example, 6.5 V). When the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, the voltage comparison unit outputs an H level state signal St and starts outputting the video signal Vsig.

  Further, the SHD 62a in which the STBY-I / O terminal is set as an output terminal outputs a status signal St output from the internal voltage comparison unit from the STBY-I / O terminal. On the other hand, the SHDs 62b to 62d in which the STBY-I / O terminal is set as an input terminal input the status signal St from the SHD 62a via the STBY-I / O terminal.

  At this time, the SHD 62a operates based on the state signal St generated internally, and the SHDs 62b to 62d operate based on the state signal St generated by the SHD 62a. Then, as shown in FIG. 7, when the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr and the state signal St of each of the SHDs 62a to 62d becomes the H level (see timing t2 shown in FIG. 7), the video from the signal line. The output of the signal Vsig is started. On the other hand, the state signal St is at the L level until the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr (see timings t1 to t2 shown in FIG. 7), and each of the SHDs 62a to 62d outputs a predetermined DC voltage to the signal line. I am doing so.

  Accordingly, when the reference voltage Vcom input to the liquid crystal display panel 13 is lower than the threshold voltage, the video signals Vsig1 to Vsig48 are not output from the respective SHDs 62a to 62d.

  As a result, application of a large voltage to the liquid crystal of the pixels of the liquid crystal display panel 13 can be suppressed, and the occurrence of stripe domains can be prevented.

  In addition, since it is not necessary to connect a capacitor having a large capacity to the VcomOUT terminals of the respective SHDs 62b to 62d, problems such as variations in capacitor capacity, generation of extra component costs, and circuit mounting area expansion can be avoided.

  Hereinafter, a specific configuration of the SHDs 62a to 62d will be specifically described with reference to FIG. FIG. 8 is a configuration diagram of the sample and hold driver (SHD) of the third embodiment. Since the SHDs 62a to 62d have the same configuration, the configuration of the SHD 62a will be described as an example here. Further, the description will be focused on the part related to the characteristic part of the SHD function. In addition, the same reference numerals are used for the same configuration as the SHD 12a of the first embodiment, and the description thereof is omitted.

  In the SHD 62a of the third embodiment, the output of the Vcom voltage generation circuit 50 is connected to a Vcom voltage comparison circuit 52 ′ (corresponding to an example of a voltage comparison unit), and the functions of the Vcom voltage comparison circuit 52 ′ are partially different. This is different from the SHD 12a of the first embodiment.

  The Vcom voltage comparison circuit 52 'has a master mode that is a first mode and a slave mode that is a second mode. When operating in the master mode, the Vcom voltage comparison circuit 52 ′ outputs a state signal St, and when operating in the slave mode, the Vcom voltage comparison circuit 52 ′ does not output the state signal St and sets the output to high impedance. This mode setting is performed by the mode setting unit 53 shown in FIG. The mode setting unit 53 sets the Vcom voltage comparison circuit 52 ′ to the master mode when an H level voltage is applied to a mode setting terminal (not shown), and when an L level voltage is applied to the mode setting terminal. The Vcom voltage comparison circuit 52 ′ is set to the slave mode.

  The state signal St is generated by comparing the reference voltage Vcom output from the Vcom voltage generation circuit 50 with the threshold voltage Vr output from the Vcom threshold voltage setting circuit 51. That is, in the master mode, the Vcom voltage comparison circuit 52 ′ outputs an L level state signal St when the reference voltage Vcom is lower than the threshold voltage Vr, and outputs an H level state signal St when the reference voltage Vcom is equal to or higher than the threshold voltage Vr. Is output. On the other hand, the Vcom voltage comparison circuit 52 'sets the output to high impedance as described above in the slave mode.

  Here, in the example shown in FIG. 6, the SHD 62a is set to the master mode, and the SHDs 62b to 62d are set to the slave mode.

  Therefore, when the power to the SHD 62a to SHD 62d is turned on, an L level signal is output as the status signal St from the Vcom voltage comparison circuit 52 'of the SHD 62a.

  As a result, a 5V DC voltage, which is a predetermined voltage, is output to the liquid crystal display panel 13 from the Vsig AC circuit 24 and the Psig AC circuit 34 of the SHD 62a through the signal line.

  This state continues until the reference voltage Vcom generated by the Vcom voltage generation circuit 50 becomes equal to or higher than the threshold voltage Vr.

  Since the status signal St is input from the SHD 62a to the STBY-I / O terminals of the SHDs 62b to 62d, the statuses of the SHDs 62b to 62d are the same as the status of the SHD 62a.

  Therefore, until the reference voltage Vcom generated by the SHD 62a is equal to or higher than the threshold voltage Vr after the power is turned on to the SHDs 62a to 62d, the 5V DC voltage is supplied from the Vsig AC circuit 24 and the Psig AC circuit 34 of the SHD 62a through the signal line. It is output to the liquid crystal display panel 13.

  Thereafter, when the reference voltage Vcom generated by the Vcom voltage generation circuit 50 of the SHD 62a becomes equal to or higher than the threshold voltage Vr, an H level signal is output as the state signal St from the Vcom voltage comparison circuit 52 'of the SHD 62a. Then, the video signals Vsig1 to Vsig12 and the precharge signal Psig converted from the Vsig alternating circuit 24 and the Psig alternating circuit 34 are output to the liquid crystal display panel 13 through the signal lines by the H level state signal St. The

  As described above, since the status signal St is input from the SHD 62a to the STBY-I / O terminals of the SHDs 62b to 62d, the status of the SHDs 62b to 62d is the same as the status of the SHD 62a.

  Therefore, when the reference voltage Vcom generated by the SHD 62a becomes equal to or higher than the threshold voltage Vr, the video signals Vsig1 to Vsig48 and the precharge signal Psig from the Vsig alternating circuit 24 and the Psig alternating circuit 34 to the liquid crystal display panel 13 through the signal lines. Is output.

  As described above, the liquid crystal display device 1 ′ according to the third embodiment includes a plurality of sample and hold drivers (SHD) that are drive circuits for simultaneously writing video signals to a plurality of pixel electrodes of the liquid crystal display panel 13. This SHD outputs a status signal St that is a comparison result by the voltage comparison unit of its own SHD and a status signal St that is a comparison result by the voltage comparison unit of the other SHD or a VcomOUT terminal that outputs the generated reference voltage Vcom. An STBY-I / O terminal for input is provided. The SHD has a mode setting that sets whether to operate in the master mode or the slave mode. The SHD operates in the status signal St generated by the own SHD in the master mode, and is generated in another SHD in the slave mode. The operation is performed by inputting the status signal St. Accordingly, by setting the SHD that supplies the reference voltage Vcom to the liquid crystal display panel 13 to the master mode and the other SHDs to the slave mode, all the SHDs operate based on the master mode status signal St. That is, the signal output from each SHD is controlled based on the comparison result between the reference voltage Vcom supplied to the liquid crystal display panel 13 and the threshold voltage Vr. Specifically, when the reference voltage Vcom supplied to the liquid crystal display panel 13 and the threshold voltage Vr are lower than the threshold voltage Vr, the master mode SHD state signal St becomes L level, and the Vsig AC circuit 24 and the Psig AC circuit 34 A predetermined DC voltage is output via the signal line. The DC voltage output in this way is within a predetermined voltage range of the reference voltage Vcom, and the occurrence of stripe domains is suppressed. On the other hand, when the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, the SHD status signal St in the master mode becomes H level, and the video signal Vsig and the precharge signal Psig are transmitted from the Vsig alternating circuit 24 and the Psig alternating circuit 34 via the signal line. Is output.

  Therefore, the supply of the reference voltage Vcom from the VcomOUT terminal of one SHD 62a to the liquid crystal display panel 13 and the connection of the STBY-I / O terminals of all the SHDs 62a to 62d can prevent the occurrence of stripe domains. .

  That is, the reference voltage Vcom generated by one SHD 62 a among the reference voltages Vcom generated by the plurality of SHDs 62 a to 62 d is applied to the counter electrode of the liquid crystal display panel 13. When the applied reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, the output of the video signal Vsig and the precharge signal Psig is started from each of the SHDs 62a to 62d. Therefore, the voltage difference between the reference voltage Vcom input to the liquid crystal display panel 13 and various signals can be suppressed, and the occurrence of stripe domains can be prevented.

  As a result, the capacitors (for example, C10b to C10d in FIG. 15) necessary for the conventional SHD can be deleted, and the component cost and the circuit mounting area can be reduced.

  In addition, since the timing is set by the capacitor C1 of one SHD and the shift of the switching timing of the signals Vsig and Psig caused by the capacitance variation of the capacitor can be suppressed, the risk of occurrence of the stripe domain can be reduced.

  Further, since the state signal St input / output at the STBY-I / O terminal is a digital signal, the timing at which the liquid crystal display panel 13 is normally driven is input by inputting this signal to the CPU of the liquid crystal display device 1 ′. Can be used as a system control signal. For example, the CPU of the liquid crystal display device 1 ′ can turn on the backlight when the status signal St becomes H level, and can reduce power consumption.

[4. Fourth Embodiment]
Next, a liquid crystal display device according to a fourth embodiment will be described. The liquid crystal display device of the fourth embodiment is different only in the SHD circuit configuration, and the connection between the SHDs and other configurations are the same as those of the liquid crystal display device 1 ′ of the third embodiment. explain. FIG. 9 is a diagram showing the configuration of the SHD in the liquid crystal display device of the fourth embodiment, and FIG. 10 is a diagram showing the relationship between the video signal and the reference voltage of the liquid crystal display device in the fourth embodiment. In addition, about the structure same as the above-mentioned embodiment, the same code | symbol shall be attached | subjected and description shall be abbreviate | omitted.

  As shown in FIG. 9, in the SHD 62a ′ of the fourth embodiment, the Vsig halftone data generation circuit 21, the Vsig-DAC input selection circuit 22, the Psig halftone data generation circuit 31, and the Psig-DAC of the SHD 62a of the third embodiment. There is no portion corresponding to the input selection circuit 32.

  Instead, a Vsig AC circuit 24 'and a Psig AC circuit 34' are provided instead of the Vsig AC circuit 24 and the Psig AC circuit 34, as in the second embodiment. The Vsig alternating circuit 24 ′ and the Psig alternating circuit 34 ′ receive the state signal St output from the Vcom voltage comparison circuit 52, and further input the reference voltage Vcom of the Vcom voltage generation circuit 50.

  The Vsig alternating circuit 24 ′ receives the reference signal input from the Vcom voltage generation circuit 50 when the L level state signal St is input from the Vcom voltage comparison circuit 52 ′ (STBY-I / O terminal in the slave mode). The voltage Vcom is output to the signal line. Further, when the H level state signal St is input from the Vcom voltage comparison circuit 52 '(STBY-I / O terminal in the slave mode), the signal input from the Vsig-DAC circuit 23 is output as the video signal Vsig. When the state signal St is at the H level, the polarity inversion signal FRP is input to the Vsig AC circuit 24 ′. Therefore, the Vsig AC circuit 24 ′ converts the signal input from the Vsig-DAC circuit 23 into an AC video. The signal Vsig is output to the signal line.

  Similarly, the Psig AC circuit 34 ′ receives an L-level state signal St from the Vcom voltage comparison circuit 52 ′ (STBY-I / O terminal in the slave mode), and then inputs from the Vcom voltage generation circuit 50. The reference voltage Vcom is output to the signal line. Further, when the H level state signal St is input from the Vcom voltage comparison circuit 52 ′ (STBY-I / O terminal in the slave mode), the signal input from the Psig-DAC circuit 33 is output as the precharge signal Psig. . Since the polarity inversion signal FRP is input to the Psig AC circuit 34 ′ when the status signal St is at the H level, the Psig AC circuit 34 ′ converts the signal input from the Psig-DAC circuit 33 into an AC signal and outputs the signal. Output as the charge signal Psig.

  Therefore, as shown in FIG. 10, the SHD 62a ′ of the fourth embodiment uses the reference voltage Vcom as the Vsig AC circuit 24 ′ and the Psig AC when the reference voltage Vcom supplied to the liquid crystal display panel 13 is lower than the threshold voltage Vr. From the circuit 34 '. This prevents the occurrence of stripe domains. On the other hand, when the reference voltage Vcom becomes equal to or higher than the threshold voltage Vr, the video signal Vsig and the precharge signal Psig are output from the Vsig alternating circuit 24 'and the Psig alternating circuit 34'.

  As a result, the capacitors (for example, C10b to C10d in FIG. 15) necessary for the conventional SHD can be deleted, and the component cost and the circuit mounting area can be reduced.

  In addition, compared with the SHD of the third embodiment, the SHD of the fourth embodiment does not apply a DC voltage to the liquid crystal of the pixels of the liquid crystal display panel 13 when the power is turned on. Degradation can be reduced.

  Furthermore, compared to the SHD of the third embodiment, in the SHD of the fourth embodiment, the Vsig halftone data generation circuit 21, the Vsig-DAC input selection circuit 22, the Psig halftone data generation circuit 31, and the Psig-DAC input selection circuit 32 are used. Is not provided. Therefore, it is possible to reduce the cost due to the effect of reducing the circuit mounting area.

  Similarly to the third embodiment, the timing is set by one SHD capacitor C1. Thereby, since the shift of the switching timing of the signals Vsig and Psig caused by the capacitance variation of the capacitor can be suppressed, the risk of occurrence of the stripe domain can be reduced.

[5. Fifth Embodiment]
FIG. 11 is a schematic block diagram showing a projector 100 using the liquid crystal display device according to the fifth embodiment of the present invention. In the fifth embodiment, for example, any one of the liquid crystal display devices described in the first to fourth embodiments is used. Therefore, the configuration of the liquid crystal display device is the same as that of the first to fourth embodiments, and thus the description thereof is omitted.

  The projector 100 includes a light source 131, dichroic mirrors 132 to 134 that separate red R, green G, and blue B, a polarizing beam splitter 135, three liquid crystal display devices 140 installed for each of RGB, and a combining prism 136. And a projection lens 137. The light source 131 includes a halogen lamp including RGB wavelength light, a mercury lamp, a xenon lamp, an LED, or the like. The light from the light source 131 is separated into RG and B by the dichroic mirror 132, and the light separated into RG is further separated into R and G by the dichroic mirror 133. The light separated into R is converted into polarized light by the polarization beam splitter 135R and applied to the liquid crystal display device 140R. The light separated into G is converted into polarized light by the polarization beam splitter 135G and irradiated to the liquid crystal display device 140G. The light separated into B is reflected by the dichroic mirror 134 or the reflecting surface, converted into polarized light by the polarization beam splitter 135B, and irradiated onto the liquid crystal display device 140B.

  Each of the liquid crystal display devices 140R, 140G, and 140B modulates the polarization direction of the incident light according to the RGB image signals, and reflects the modulated light to the corresponding polarization beam splitters 135R, 135G, and 135B, respectively. Each of the polarization beam splitters 135R, 135G, and 135B visualizes the modulated light incident from the respective liquid crystal display devices 140R, 140G, and 140B, and emits the light onto the corresponding surface of the combining prism 136. The combining prism 136 combines the modulated light beams of the respective colors and emits the light toward the projection lens 137 so that the projection image is projected on the screen 138. As a result, it is possible to project a projected image with a fast response speed that prevents the occurrence of domains in the liquid crystal layer and prevents uneven brightness and a decrease in contrast.

  Although the reflective liquid crystal display device 140 is used as the liquid crystal display device 140 in the fifth embodiment, the present invention is not limited to this. The reflection directions of the polarizing beam splitters 135R, 135G, and 135B are reversed to the combining prism side, and transmissive liquid crystal display devices 140R, 140G, and 140B are installed between the polarizing beam splitters 135R, 135G, and 135B and the combining prism 136, respectively. May be. In this case, a polarizing plate is installed between each of the liquid crystal display devices 140R, 140G, and 140B and the combining prism 136.

  In addition, the liquid crystal display devices described in the first to fourth embodiments can be applied not only to projectors but also to electronic devices such as liquid crystal televisions and mobile phones.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. It can be changed.

It is a schematic block diagram of the liquid crystal display device in 1st Embodiment. It is a figure which shows the relationship between the video signal of the liquid crystal display device in 1st Embodiment, and a reference voltage. It is a block diagram of the sample hold driver (SHD) of the liquid crystal display device in 1st Embodiment. It is a figure which shows the structure of the sample hold driver (SHD) of the liquid crystal display device in 2nd Embodiment. It is a figure which shows the relationship between the video signal of the liquid crystal display device in 2nd Embodiment, and a reference voltage. It is a schematic block diagram of the liquid crystal display device in 3rd Embodiment. It is a figure which shows the relationship between the video signal of the liquid crystal display device in 3rd Embodiment, and a reference voltage. It is a figure which shows the structure of the sample hold driver (SHD) of the liquid crystal display device in 3rd Embodiment. It is a figure which shows the structure of the sample hold driver (SHD) of the liquid crystal display device in 4th Embodiment. It is a figure which shows the relationship between the video signal of the liquid crystal display device in 4th Embodiment, and a reference voltage. It is a typical block diagram showing the projector using the liquid crystal display device in 5th Embodiment. It is a schematic diagram for demonstrating the conventional liquid crystal display device which employ | adopted the multiple pixel simultaneous writing system. It is a figure for demonstrating the conventional method which carries out the sequence control of the rise of a video signal and a reference voltage. It is a figure which shows the relationship between the video signal of a conventional liquid crystal display device, and a reference voltage. It is a block diagram of the liquid crystal display device which operates a liquid crystal display panel using two or more conventional SHD. FIG. 16 is a diagram illustrating a relationship between a video signal and a reference voltage of the liquid crystal display device of FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 11 Data processing / timing signal generation circuit (DSD / TG)
12a to 12d, 12a 'to 12d', 62a to 62d, 62a 'to 62d' Sample hold driver (SHD: drive circuit)
13 Liquid crystal display panel 20 Sample hold decoder circuit 21 Vsig halftone data generation circuit 22 Vsig-DAC input selection circuit 23 Vsig-DAC circuit 24, 24 'Vsig alternating circuit 30 Psig normal data generation circuit 31 Psig halftone data generation circuit 32 Psig-DAC input selection circuit 33 Psig-DAC circuit 34, 34 'Psig alternating circuit 40 Timing generator (TG)
41 FRP selection circuit 50 Vcom voltage generation circuit 51 Vcom threshold voltage setting circuit 52, 52 ′ Vcom voltage comparison circuit 100 Projector 131 Light sources 132 to 134 Dichroic mirrors 135R, 135G, 135B Polarization beam splitter 136 Synthetic prism 137 Projection lens 138 Screen 140R, 140G, 140B liquid crystal display device

Claims (9)

A plurality of drive circuits for simultaneously writing video signals to a plurality of pixel electrodes of a liquid crystal display panel,
Each of the drive circuits
A video signal output unit for outputting a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line;
A reference voltage generating unit that generates a reference voltage to be applied to the counter electrode of the liquid crystal display panel,
When the reference voltage generated by one drive circuit among the reference voltages generated by the plurality of drive circuits is applied to the counter electrode of the liquid crystal display panel, and the applied reference voltage is equal to or higher than a threshold voltage, A driving device for a liquid crystal display panel, which starts output of the video signal from a video signal output unit of a driving circuit. Each of the drive circuits
An input terminal for inputting a reference voltage generated by a reference voltage generator of an internal or other drive circuit;
A voltage comparison unit for comparing the reference voltage input to the input terminal and the threshold voltage;
2. The liquid crystal display panel driving device according to claim 1, wherein when the reference voltage input to the input terminal becomes equal to or higher than the threshold voltage, output of the video signal is started from the video signal output unit. Each of the drive circuits
A voltage comparison unit that compares the reference voltage generated by the reference voltage generation unit and the threshold voltage;
An input terminal for inputting a comparison result of a voltage comparison unit of another drive circuit;
A mode setting unit that sets a first mode that operates based on a comparison result by an internal voltage comparison unit and a second mode that operates based on an input to the input terminal;
When the first mode is set, the video signal output unit starts outputting the video signal based on the detection result of the internal voltage comparison unit, and when the second mode is set, the input 2. The liquid crystal display panel driving device according to claim 1, wherein output of the video signal is started from the video signal output unit based on an input to a terminal.   4. Each of the video signal output units outputs a predetermined DC voltage to the liquid crystal display panel via the signal line until a reference voltage applied to the liquid crystal display panel becomes equal to or higher than the threshold voltage. 2. A driving device for a liquid crystal display panel according to claim 1.   Each said video signal output part outputs the said reference voltage to the said liquid crystal display panel via the said signal line until the reference voltage applied to the said liquid crystal display panel becomes more than the said threshold voltage. 2. A drive device for a liquid crystal display panel according to item 1. A liquid crystal display panel, and a plurality of drive circuits for simultaneously writing video signals to a plurality of pixel electrodes of the liquid crystal display panel,
Each of the drive circuits
A video signal output unit for outputting a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line;
A reference voltage generating unit that generates a reference voltage to be applied to the counter electrode of the liquid crystal display panel,
When the reference voltage generated by one drive circuit among the reference voltages generated by the plurality of drive circuits is applied to the counter electrode of the liquid crystal display panel, and the applied reference voltage is equal to or higher than a threshold voltage, A liquid crystal display device that starts outputting the video signal from a video signal output unit of a drive circuit. A liquid crystal display device comprising the liquid crystal display panel and a plurality of drive circuits for simultaneously writing video signals to the plurality of pixel electrodes of the liquid crystal display panel;
Each of the drive circuits
A video signal output unit for outputting a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line;
A reference voltage generating unit that generates a reference voltage to be applied to the counter electrode of the liquid crystal display panel,
When the reference voltage generated by one drive circuit among the reference voltages generated by the plurality of drive circuits is applied to the counter electrode of the liquid crystal display panel, the reference voltage applied is equal to or higher than a threshold voltage. An electronic device that starts outputting the video signal from the video signal output unit of the drive circuit. A video signal output unit for outputting a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line;
A reference voltage generator for generating a reference voltage to be applied to the counter electrode of the liquid crystal display panel;
When the reference voltage applied to the liquid crystal display panel is a reference voltage generated by the reference voltage generation unit, the voltage is input, and the reference voltage applied to the liquid crystal display panel is generated by another device An input terminal for inputting the voltage when the voltage,
A voltage comparison unit that compares a voltage input to the input terminal with a preset threshold voltage;
A driving circuit for a liquid crystal display panel, wherein the video signal output unit starts outputting the video signal when a voltage input to the input terminal becomes equal to or higher than the threshold voltage. A video signal output unit for outputting a video signal applied to the plurality of pixel electrodes to the liquid crystal display panel via a signal line;
A reference voltage generator for generating a reference voltage to be applied to the counter electrode of the liquid crystal display panel;
A voltage comparison unit that compares the reference voltage generated by the reference voltage generation unit and a preset threshold voltage;
An input terminal for inputting an output of a voltage comparison unit of another drive circuit;
A mode setting unit that sets a first mode that operates based on a comparison result by the voltage comparison unit and a second mode that operates based on an input to the input terminal;
When the first mode is set, the video signal output unit starts outputting the video signal based on the detection result of the voltage comparison unit, and when the second mode is set, the input terminal A liquid crystal display panel drive circuit that starts outputting the video signal from the video signal output unit based on an input to the video signal.

Images