JP2009540331A - Differential signal test structure and probe - Google Patents

Abstract

Test structures and differential signal probes that include differential gain cells include compensation for the Miller effect that reduces the frequency dependent variation of the input impedance of the test structure.

Description

CROSS REFERENCE FOR RELATED APPLICATIONS This application claims the benefit of US Provisional Application No. 60 / 813,120, previously filed on June 12, 2006.

  The present invention relates to wafer probing, and more particularly to probes and test structures for wafer probing with differential signals.

  Integrated circuits (ICs) are economically attractive because a large number of roughly complex circuits, such as microprocessors, can be manufactured inexpensively on the surface of a wafer or substrate. After fabrication, individual dies containing one or more circuits are separated or singulated and encapsulated in a package that provides electrical connection between the package exterior and the encapsulated die circuitry. Because die separation and packaging represents a significant portion of the manufacturing cost of an integrated circuit device, manufacturers typically monitor and control the IC manufacturing process to reduce defective die packaging costs. Electrical circuits or test structures have been added to the wafer that allow on-wafer testing or “probing” to verify the characteristics of the integrated circuit before breaking up.

  In general, a test structure connects a device under test (DUT), a plurality of metal probes or a plurality of bond pads deposited on the surface of a wafer, and usually a bond pad and a DUT fabricated below the wafer surface. Includes a plurality of conductive vias. In general, a DUT consists of a simple circuit that includes a copy of one or more basic elements of an integrated circuit, such as a single wire of conductive material, a series of vias or a single transistor. In general, the circuit elements of a DUT are manufactured in the same process on the same layer of the die as the corresponding elements of an integrated circuit. An IC is typically “on-wafer” characterized by applying a signal generated by a test instrument to a test structure and measuring the response of the test structure to the signal. Since the circuit elements of the DUT are manufactured in the same way as the corresponding elements of the integrated circuit, the electrical characteristics of the DUT should show the electrical characteristics of the corresponding components of the integrated circuit.

  At high frequencies, on-wafer characterization is usually performed with a network analyzer. The network analyzer includes an AC signal source, typically a radio frequency (RF) signal source that is used to stimulate the DUT of the test structure. The changeover switch directs the stimulus signal to one or more bond pads of the test structure. Directional couplers or bridges pick off forward or reverse traveling waves to or from the test structure. These signals are downconverted by the intermediate frequency (IF) stage of the network analyzer, and these signals are filtered, amplified and digitized for further processing and display. As a result, a plurality of S parameters (scattering parameters), which is a ratio of the normalized power wave including the response of the DUT and the normalized power wave including the stimulus signal supplied by the signal source, is obtained.

  A suitable interconnection for transmitting signals between the signal source, the network analyzer receiver, and the test structure is a coaxial cable. The transition between the coaxial cable and the bond pad of the test structure is preferably provided by a movable probe having one or more conductive probe tips that can be co-located with the test structure bond pad. By bringing the probe tip into contact with the bond pad of the test structure, the network analyzer and the test structure can be temporarily interconnected.

  In general, integrated circuits include a ground plane on the lower surface of the substrate on which the active and passive devices of the circuit are manufactured. Usually, the terminals of transistors manufactured on a semiconductor substrate are capacitively interconnected to the ground plane through the substrate. The interconnection impedance of this parasitic capacitance depends on the frequency, and at high frequencies, the nature of the ground potential and the ground reference (single-ended) signal is uncertain.

Balanced devices are attractive for high performance ICs because they can tolerate poor radio frequency (RF) ground more than single-ended devices. Referring to FIG. 1, the differential gain cell 20 is a balanced device comprising two nominally identical circuit halves 2OA, 2OB. When this balanced device is biased with a DC current source 22 and stimulated with differential mode signals 24, 26 containing even and odd mode components of equal amplitude and antiphase (Si ^{+ 1} and Si- ¹ ), two circuit halves A virtual ground is set on the axis of symmetry 28. In this virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulus signal. The quality of the balanced device's virtual ground is independent of the physical ground path, and therefore balanced or differential circuits can tolerate less RF ground than circuits operating with single-ended signals. The two waveforms of the differential output signals (So ⁺¹ and So ⁻¹ ) 30, 32 make the determination of the transition from one binary value to the other binary value more reliable and reduce the voltage swing of the signal to a binary value. It is a mutual reference to make the transition between them faster. In general, differential devices can operate with lower signal power and higher data rates than single-ended devices. Furthermore, noise from external sources, such as adjacent conductors, tends to couple electrically and electromagnetically in common mode and cancel in differential mode. As a result, signals that are out of phase at the fundamental frequency will be in phase at the even harmonics, so the balanced or differential circuit will have good tolerance to noise, including noise at even harmonics. . Differential devices with improved tolerance for poor RF grounding, high resistance to noise, and reduced signal power are attractive for high frequency operation.

  A DUT with a differential gain cell forms the basis for a test structure that enables on-wafer evaluation of devices contained in market-oriented integrated circuits manufactured on wafers at high frequencies. However, the impedance of the internal connections of DUT components is often frequency dependent, complicating DUT de-embedding and affecting test accuracy. For example, the input and output of a differential gain cell (eg, differential gain cell 20) are typically capacitively interconnected by a parasitic capacitance that couples the cell's transistor terminals. The parasitic capacitance 42 between the gates 38, 40 and the drains 34, 36 is caused by the diffusion of the drain dopant under the gate oxide and is inherent and unique to the MOS transistor. When the gate voltage changes due to the gain of the transistor, the drain voltage of the transistor changes more greatly. When a different voltage is applied to the terminal of the parasitic capacitor (Cgd) between the gate and the drain, the capacitor acts as a very large capacitance, and this phenomenon is known as a mirror effect. As a result, the input impedance of the differential device varies greatly with frequency, and the operation of the differential device becomes unstable.

  What is desired is a method and apparatus for testing differential devices that minimizes or eliminates the mirror effect.

1 is a schematic diagram of a balancing device. 1 is a schematic diagram of a differential test structure comprising a probe, a field effect transistor and a pair of mirror effect neutralizing capacitors. FIG. 1 is a schematic diagram of a differential test structure comprising a probe, a bipolar junction (BJT) transistor and a pair of Miller effect neutralizing capacitors. FIG. It is a perspective view of a test structure and a probe. It is the schematic of the differential test structure for go / no go test of a transistor function.

Referring to the drawings in which like parts bear the same reference numerals, and in particular with reference to FIG. 1, a differential gain cell 20 is a balanced device comprising two nominally identical circuit halves 20A, 20B. It is. When this balanced device is biased with a DC current source 22 and stimulated with differential mode signals 24, 26 containing even and odd mode components of equal amplitude and antiphase (Si ^{+ 1} and Si- ¹ ), two circuit halves A virtual ground is set on the temporary symmetry axis 28. In this virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the stimulus signal. The virtual ground quality of a balanced device is independent of the physical ground path, so a balanced or differential circuit can tolerate less RF ground than a circuit operating with a single-ended (ground referenced) signal. Can do. Differential devices can operate at lower signal power and higher data rates compared to single-ended devices, and include even harmonics from external sources such as adjacent conductors It also has good resistance to noise.

  However, the response of an integrated circuit including a test structure with differential gain cells to high frequency signals is usually frequency dependent. Integrated circuits are manufactured by depositing a layer of semiconductor and insulating material on a semiconductor substrate, and typically natural frequency dependent coupling exists between the various elements of the manufactured device. Such natural frequency dependent coupling connects the gate and drain of the MOS transistor and connects the base and collector of the bipolar junction transistor (BJT). For example, the gate and drain of a typical MOS transistor are interconnected by an inherent parasitic capacitance (Cgd) because the drain dopant diffuses under the oxide that forms the gate of the transistor. As the frequency of the stimulus signal increases, the impedance between the gate and drain of the transistor, and thus the input impedance of the differential gain cell, changes. Furthermore, the transistor gain causes any change in the transistor's gate voltage to be amplified at the transistor's drain, causing a phenomenon known as the Miller effect where the parasitic capacitance (Cgd) becomes visible as a very large capacitor. The inventor recognizes that the signal carried by each transistor of the differential gain cell is a mirror image, and can minimize or eliminate the mirror effect, and further connect the gate of the first transistor between the gate and the drain. It was concluded that the input impedance of the test structure with differential gain cells is stabilized by connecting to the drain of the second transistor with a capacitor having a value equal to the parasitic capacitance (Cgd).

Referring to FIG. 2, the test structure 50 includes a differential gain cell 51 that includes transistors 52A, 52B. The gate of each transistor is connected to probe pads 54 and 56. The probe tips 64 and 66 arranged so as to be arranged at the same position as the probe pad are connected to the source 74 of the differential input signal including the component signal Si ⁺¹ and its differential complementary signal Si ⁻¹ . The source of the differential signal is typically a radio frequency (RF) signal source included in the network analyzer 76. The network analyzer also includes a sink 78 for the output signal of the test structure including the components So ^{+ 1} and So- ¹ . Each component of the output signal is transmitted from the drain of the transistor via probe tips 68 and 70 to probe pads 58 and 60 that can be connected to a signal sink. The sources of the transistors are interconnected and connected to a bias probe pad 62 that is engageable with the probe tip 72. The probe tip interconnects with a DC current source 80 that provides bias to the differential gain cell.

Each transistor 52A, 52B has its own parasitic capacitance (Cgd) 82, 83 interconnecting the gate and drain that respectively constitute the input and output terminals of the test structure. Due to the gain (A) of the transistor, the change (dV) in the gate voltage of the transistor is amplified (A * dV) at the drain, exciting different voltages on both sides of the parasitic capacitance. Due to a phenomenon known as the Miller effect, the parasitic capacitance (Cgd) will act as a very large capacitor, causing the input impedance of the test structure to vary greatly with frequency. In order to reduce or eliminate the influence of parasitic capacitance between the gate and the drain, and to provide a stable input impedance by the test structure, the compensation capacitors 84A and 84B are provided with a gate of each transistor (for example, the gate of the transistor 52A) and a differential. The drain of the second transistor of the gain cell (for example, the drain of the transistor 52B) is connected. This compensation capacitor has a value equal to the value of Cgd. Since the transistors of the differential gain cell are matched and the phase of the differential input signal component Si ^{+ 1} is 180 ° from the phase of the differential output signal component So- ¹ , the change in the drain voltage of the transistor due to the gate-drain capacitance For example, A * dV is canceled out by the voltage # (− A * dV) of the compensation capacitor, and the input impedance of the test structure becomes constant.

Referring to FIG. 3, a test structure 100 according to another embodiment includes a differential gain cell 102 including bipolar junction transistors (BJT) 104A and 104B connected in a grounded emitter configuration. The base of the transistor is connected to probe pads 106 and 108 that are engageable with probe tips 116 and 118 that are interconnected to a source 126 of a differential signal containing input signal components (Si ⁺¹ and Si ⁻¹ ). The collector of the transistor is connected to a probe pad 110, 112 that is engageable with a probe tip 120, 122 interconnected to a sink 128 for the output signal of the differential cell containing the signal components (So ^{+ 1} and So- ¹ ). To do. The emitter of the matched transistor is connected to a DC current source 130 that biases the differential gain cell through a probe tip 124 that can be interconnected and connected to a bias probe pad 114. Each BJT includes a base-collector parasitic capacitance (Cbc) that forms a frequency dependent interconnection between the input and output of the test structure. To address the Miller effect, a compensation capacitor 134 having a value equal to Cbc interconnects the respective gates of each transistor 104A, 104B to the collectors of the other transistors in the differential gain cell.

  The compensation capacitor can be manufactured as part of the test structure and can be reliably matched to the parasitic capacitance of the transistor. On the other hand, compensation capacitors can also be connected to each probe tip that can engage an appropriate probe pad. In general, differential probing is performed with two probes. Referring to FIG. 4, the differential test structure 200 includes at least four bonds or probes of probe pads 202, 204 for input signal components and probe pads 206, 208 for output signal components arranged in a linear array. A plurality of conductive vias 216 are connected to a DUT 212 that includes pads and is manufactured below the surface of the wafer 214. The fifth probe pad 210 biases the DUT through it and is preferably manufactured in a linear array, but can also be offset. A linear array of probe pad structures allows the test structure to be fabricated in the comb path 218 (shown in parentheses) between the dies 220, so that the test structure has no meaning after singulation of the dies. The area of the wafer occupied by can be reduced. With a linear arrangement of probe pads, a single comprising a linear array of at least four probe tips 222, 224, 226, 228 that can be manufactured on the surface of the insulating plate 232 and can be co-located with the probe pads for input and output signals Probing with a probe becomes possible. The fifth probe tip 230 biases the DUT through this, and is preferably manufactured in a linear array of probe tips, but may be offset or arranged at different angles to the wafer. May be. By linearly arranging the probe tips, the probe tips 222 and 224 that transmit the input signal to the conductor 234 and the two transistors of the differential gain cell of the DUT are interconnected with the probe tips 226 and 228 that transmit the output signal. The compensation capacitor 236 can be easily manufactured.

  It is desirable to be able to easily determine during operation of an integrated circuit (IC) whether a transistor included in the integrated circuit operates. Referring to FIG. 5, a test structure 150 in which go / no go is easily tested has circuit elements fabricated in the same process and on the same layer of the wafer as corresponding components of an integrated circuit for the market. A differential gain cell 152 is included. The test structure negates the Miller effect caused by the gate-drain parasitic capacitance (Cgd) and stabilizes the input impedance of the test structure so that the gates of each of the transistors 154A, 154B are in pairs, respectively. It includes a compensation capacitor 156 connected to the drains of certain 154B and 154A. A resistor network including resistors 178 connecting the signal input probe tips 168, 170 is configured to engage the input probe pads 158, 160 and the signal source 74. Similarly, the signal output probe pads 162 and 164 are connected to the signal sink 78 via probe tips 172 and 174 and resistors 182 and 184. The test structure is biased by a probe pad 166 and a probe tip 176 that is grounded by a bias resistor 186. The resistance at all terminals stabilizes the DC operation of the amplifier, and further reduces the Q factor of resonance created by the capacitive and inductive interconnections of the parasitic devices, thus avoiding amplifier oscillation. The value of the resistor is chosen to provide stability and a convenient gain level (preferably approximately 1). Data is collected by testing multiple transistor pairs known to be normal. By comparing this data with data obtained by testing an on-wafer test structure, a go / no go criterion for transistor function is obtained that is easy to use during the manufacturing process.

  The input impedance of the test structure with a differential gain cell is that the gate of the first transistor and the drain of the second transistor of the differential pair are connected to a parasitic capacitance between the device gate-drain (base-collector). Stable by interconnecting with capacitors with close values.

  In the foregoing detailed description, a number of specific examples have been set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific examples. In other instances, well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

  All references cited herein are hereby incorporated by reference.

  The terms and formulas used in the above specification are merely used for explanation and do not limit the present invention. Furthermore, the use of such terms and formulas is not intended to exclude equivalents or portions of features shown and described. The scope of the present invention is limited only by the appended claims.

Claims (10)

A difference including a first input signal probe pad capacitively interconnected to the first output signal probe pad and a second input signal probe pad capacitively interconnected to the second output signal probe pad. A test structure comprising a dynamic gain cell,
(A) a first compensation capacitor interconnecting the first input signal probe pad and the second output signal probe pad;
(B) A test structure comprising a second compensation capacitor interconnecting the second input signal probe pad and the first output signal probe pad. The first compensation capacitor has a capacitance that is approximately equal to a capacitance of the interconnect between the first input signal probe pad and the first output signal probe pad;
The second compensation capacitor has a capacitance that is approximately equal to the capacitance of the interconnect between the second input signal probe pad and the second output signal probe pad.
The test structure of claim 1. A difference including a first input signal probe pad capacitively interconnected to the first output signal probe pad and a second input signal probe pad capacitively interconnected to the second output signal probe pad. A probe for probing a dynamic gain cell,
(A) a first probe tip connectable to a source of a first input signal and disposed to contact the first input signal probe pad of the differential gain cell;
(B) a second probe tip that is connectable to a source of a second input signal and is disposed in contact with the second input signal probe pad;
(C) a third probe tip connectable to a sink of the first output signal and disposed to contact the first output signal probe pad;
(D) a fourth probe tip connectable to a sink of a second output signal and configured to contact the second output signal probe pad;
(E) a first capacitor that interconnects the first probe chip and the fourth probe chip; and (f) a second capacitor that interconnects the second probe chip and the third probe chip. Two capacitors,
Probe with. The first probe tip, the second probe tip, the third probe tip, and the fourth probe tip are arranged in a linear array,
The probe according to claim 3. The capacitor interconnecting the first probe chip and the fourth probe chip has a capacitance approximately equal to the capacitance of the interconnection between the first input signal probe pad and the first output signal probe pad. In addition,
The capacitor that interconnects the second probe chip and the third probe chip has a capacitance that is approximately equal to the capacitance of the interconnection between the second input signal probe pad and the second output signal probe pad. Having
The probe according to claim 3. The first probe tip, the second probe tip, the third probe tip, and the fourth probe tip are arranged in a linear array,
The probe according to claim 5. A difference including a first input signal probe pad capacitively interconnected to the first output signal probe pad and a second input signal probe pad capacitively interconnected to the second output signal probe pad. A method for probing a dynamic gain cell, comprising:
(A) the first input signal probe pad and the second output signal probe pad, and the capacitance of the interconnection between the first input signal probe pad and the first output signal probe pad; Interconnecting with capacitors having approximately equal capacitances;
(B) the second input signal probe pad and the first output signal probe pad, and the capacitance of the interconnection between the second input signal probe pad and the second output signal probe pad; Interconnecting with capacitors having approximately equal capacitances;
A method for probing a differential gain cell. A test structure for testing the functionality of a transistor:
(A) (i) a first terminal connectable to a source of a first component of a differential signal via a first resistor;
(Ii) a second terminal connectable to a sink for the first component of the output signal via a second resistor and interconnected to the first terminal by a parasitic capacitance;
(Iii) a third terminal;
A first transistor comprising:
(B) (i) a first terminal connectable to the source of the second component of the differential signal via a third resistor;
(Ii) a second terminal connectable to a sink for the second component of the output signal via a fourth resistor and interconnected to the first terminal by a parasitic capacitance;
(Iii) a third terminal interconnected to the third terminal of the first transistor and a source of bias voltage;
A second transistor comprising:
(C) a first compensation capacitor that connects the first terminal of the first transistor and the second terminal of the second transistor;
(D) a second compensation capacitor that connects the first terminal of the second transistor and the second terminal of the first transistor;
With test structure. The first compensation capacitor has a capacitance that is approximately equal to the parasitic capacitance that interconnects the first terminal of the first transistor and the second terminal of the first transistor;
The second compensation capacitor has a capacitance that is substantially equal to the parasitic capacitance that interconnects the first terminal of the second transistor and the second terminal of the second transistor.
The test structure according to claim 8. The first resistor, the second resistor, the third resistor, and the fourth resistor have values selected such that the test structure has a gain of approximately one;
The test structure according to claim 8.

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