Cross reference to related
The present application claims the effect of June 12, 2006
U.S. Patent Application No. 60 / 813,120.
Background of the invention
The present invention relates to the testing of wafers (wafer probing)
and in particular sensors
and test structures for testing wafers using differential
Circuits (ICs) are economically attractive because of large numbers
complex circuits, such as microprocessors, on the
a wafer or substrate can be produced inexpensively. To
The manufacturing process involves individual dies, which are one or more circuits
have, separated or isolated and enclosed in a housing,
by the electrical connections between the outside of the housing
and the circuit can be provided on the enclosed chip.
The separation and the Einhausen of a chip claim a substantial
Part of the manufacturing cost of the integrated circuit chip,
and to monitor
and controlling the IC manufacturing process and avoiding costs
Einhausen defective chips add
The wafer usually produces electrical circuits or
Add test structures to enable on-wafer testing or on-wafer probing, and
to verify the characteristics of the integrated circuits,
before the chips are separated.
Test structure typically has one device-under-test (DUT), several
metallic probe pads or pads (bond pads),
the on the wafer surface
are applied, and a plurality of conductive vias or vias
on that the pads
connect with the DUT, which is typically below the surface of the
Wafers is made. The DUT typically includes a simple one
Circuit, which is a copy of one or more of the basic elements
the integrated circuit has, for. B. a single line
from a conductive
Material, a series of vias, or a single one
Transistor. The circuit elements of the DUT typically become
through the same process and in the same layers of the chip
made as the corresponding elements of the integrated circuit.
The ICs are typically characterized on the wafer (on-wafer),
the test structure generates a signal generated by a test instrument
and the response of the test structure to the signal is measured. Because
the circuit elements of the DUT through the same process as the
corresponding elements of the integrated circuit are manufactured,
is expected that the electrical properties of the DUT for the electrical
Properties of the corresponding components of the integrated circuit
Frequencies will usually take an on-wafer characterization below
Using a network analyzer. The network analyzer
has a source for
an alternating current signal, which is normally a radio frequency (RF) signal
that is used to excite the DUT of a test structure.
A forward / reverse switch
Excitation signals to one or more pads of the test structure to. directional
key the forward or test structure running to the test structure
from. These signals are divided by intermediate frequency (IF) sections of the
Down-converted network analyzer,
where the signals for
a further processing and representation filtered, amplified and
be digitized. As a result, several s-parameters (scattering parameters) are obtained,
the the relationship
a normalized voltage wave having the response of the DUT,
to a normalized voltage wave, the by the
Signal source supplied
preferred connection for transmitting
Signals between the signal source and the receiver of the network analyzer
and the test structure is a coaxial cable. For the transition between the coaxial cable
and the contact surfaces
The test structure is preferably provided with a movable sensor
one or more conductive probe tips,
which are arranged so that they with the contact surfaces of
Test structure aligned are positionable. The network analyzer and
the test structure can
be joined together by the sensor tips with the contact surfaces of the
Test structure are brought into contact.
Circuits typically have a ground plane at the bottom
of the substrate on which the active and passive components of the
Circuit are produced. The connections of the on a semiconductor substrate
formed transistors are typically capacitive across the substrate
connected to the ground plane. The impedance of this parasitic capacitive
Connection is frequency-dependent,
and at high frequencies become the ground potential and the true ones
Characteristics of ground-based (single-ended) signals uncertain.
Balanced devices are more tolerant of poor radio frequency (RF) grounding as single-ended devices, making them attractive for high performance ICs. Referring to 1 is a differential amplifier cell 20 a symmetrical device with two nominally identical circuit halves 20A . 20B , Biased by a DC source 22 and excited by a differential mode signal, the common mode and even mode (odd) mode components having the same amplitude and opposite phases (S i +1 and S i -1 ) 24 . 26 has, is at the axis of symmetry 28 the two circuit halves generates a virtual mass. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the excitation signal. The quality of the virtual ground of a balanced device is independent of the physical ground path, so that balanced or differential circuits can tolerate inferior RF grounding better than circuits operated with single-ended signals. The two waveforms of the differential output signal (S o +1 and S o -1 ) 30 . 32 represent mutual references that provide greater certainty in determining the transition from one to another binary value and allow for a reduction in the voltage swing of the signal and a faster transition between binary values. Typically, differential devices can operate at lower signal power and higher data rates than single-ended devices. In addition, noise from external sources, such as adjacent conductors, tends to electrically and electromagnetically couple to common mode and cancel out in the differential mode. As a result, symmetric or differential circuits have good immunity to noise at even harmonic frequencies because signals that are out of phase at the fundamental frequency are in phase with the even harmonics. Improved tolerance for inferior RF grounding, increased resistance to noise, and reduced signal power make differential devices attractive for operation at higher frequencies.
A DUT with a differential amplifier cell provides a basis for a test structure that enables high frequency on-wafer analysis of devices included in the marketable integrated circuits fabricated on the wafer. However, the impedance of the internal connections of the DUT components is often frequency-dependent, which makes it difficult to de-embed or disintegrate the DUT and affect test accuracy. For example, the input and output of a differential amplifier cell, e.g. B. the differential amplifier cell 20 normally capacitively connected due to parasitic capacitances connecting the terminals of the cell transistors. The parasitic capacity 42 between the gate electrode 38 . 40 and the drain electrode 34 . 36 , a result of diffusion of the drain dopant under the oxide of the gate electrode, is intrinsic and typical in MOS transistors. As a result of the transistor gain, a change in the gate voltage produces an even greater change in the voltage at the drain of the transistor. Applying different voltages to the terminals of the parasitic gate-drain capacitance (C gd ) causes the capacitor to behave like a much larger capacitance; a phenomenon known as the Miller effect. As a result, the input impedance of the differential device substantially changes with the frequency, whereby an unstable operation of the differential device is obtained.
are a method and an apparatus for testing a differential device,
by which the Miller effect is minimized or eliminated.
Brief description of the drawings
1 shows a schematic diagram of a symmetrical device;
2 shows a schematic representation of a sensor and a differential test structure with field effect transistors and a pair of Miller effect neutralizing capacitors;
3 shows a schematic representation of a probe and a differential test structure with bipolar transistors (BJTs) and a pair of Miller effect neutralizing capacitors;
4 shows a perspective view of a test structure and a probe; and
5 shows a schematic representation of a differential test structure for a go / no-go test of the functionality of a transistor.
Detailed description more preferred
Reference is made in detail to the drawings, in which like parts are designated by like reference numerals, and in particular 1 in which a differential amplifier cell 20 a symmetrical device with two nominally identical circuit halves 20A . 20B is. Im by a DC source 22 biased state and excited by a differential mode signal, the common mode and differential mode components having the same amplitude and opposite phases (S i +1 and S i -1 ) 24 . 26 is at the axis of symmetry 28 the two circuit halves generates a virtual mass. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the excitation signal. The quality of the virtual ground of a balanced device is independent of the physical ground path, so that balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single-ended (ground related) signals. Also, differential devices typically can operate at lower signal power and at higher data rates than single-ended devices, and have good immunity to noise from external sources, such as adjacent conductors, including noise at even harmonic frequencies.
However, the response of integrated circuits, including differential amplifier cell testing structures, to high frequency signals is typically frequency dependent. Integrated circuits are fabricated by depositing layers of semiconductor and insulating materials on a semiconductor substrate, with intrinsic frequency dependent connections normally present between the various elements of the fabricated devices. Such an intrinsic frequency-dependent connection connects the gate and drain electrodes of MOS transistors and the bases and collectors of bipolar transistors (BJTs). For example, an intrinsic parasitic capacitance (C gd ) connects the gate and drain of a typical MOS transistor because the drain dopant diffuses under the oxide of the gate of the transistor. As the frequency of the excitation signal increases, the impedance between the gate and drain of the transistor changes, thereby changing the input impedance of the differential amplifier cell. In addition, due to the gain of the transistor, any voltage change at the gate of the transistor is amplified at the drain of the transistor, whereby the parasitic capacitance (C gd ) appears as a much larger capacitor; a phenomenon known as the Miller effect.
The inventors recognized that the signals transmitted by the respective transistors of the differential amplifier cell are mirror images and concluded that the Miller effect could be minimized or eliminated and the input impedance of a differential amplifier cell test structure could be stabilized by passing the gate of a transistor over a capacitor whose capacitance is equal to the parasitic gate-drain capacitance (C gd ) is connected to the drain of the second transistor.
Referring to 2 has a test structure 50 a differential amplifier cell 51 with transistors 52A . 52B on. The gate electrodes of the respective transistors are with sensor contact pads 54 . 56 connected. Probe tips 64 . 66 , which are arranged so that they are positioned with the probe contact surfaces aligned, are with a source 74 for a differential input signal having the signal component S i +1 and its differential complementary signal S i -1 . The source of the differential signal is typically one in a network analyzer 76 arranged high frequency (HF) source. The network analyzer also has a sink 78 for the output of the test structure having components (S o +1 and S o -1 ). The respective components of the output signal are from the drains of the transistors to probe contact surfaces 58 . 60 transmit that across sensor tips 68 . 70 can be connected to the signal sink. The sources of the transistors are connected to each other and to a bias probe pad 62 connected with a probe tip 72 can be brought into contact. The probe tip is powered by a DC source 80 which provides the bias for the differential amplifier cell.
In every transistor 52A . 52B is an intrinsic parasitic capacitance (C gd ) 82A . 82B which connects the respective gate and drain electrodes constituting the input terminals and the output terminals of the test pattern. The gain (A) of the transistor amplifies a change in the voltage (dV) at the gate of a transistor at the drain (A * V), whereby opposite sides of the parasitic capacitance experience different voltages. As a result of a phenomenon known as Miller effect, the parasitic capacitance (C gd ) has the effect of a larger capacitor, whereby the input impedance of the test structure changes substantially with frequency. To reduce or eliminate the effect of the parasitic gate-drain capacitance and to provide a more constant input impedance to the test structure, a compensation capacitor is used 84A . 84B from the gate of each transistor, e.g. B. the gate electrode of the transistor 52A , connected to the drain of the second transistor of the differential amplifier cell, e.g. B. with the drain electrode of the transistor 52B , The compensation capacitor has a capacitance value equal to the value C gd . Because the transistors of the differential amplifier cell are matched and the phase of the differential input signal component S i + 1 is shifted by 180 ° with respect to the phase of the differential output signal component S o -1 , the voltage change at the drain caused by the gate-drain capacitance is Electrode of the transistor, z. B. A · dV shifted by the voltage at the compensation capacitor # (-A · dV), so the input impedance of the test structure remains constant.
Referring to 3 shows another exemplary embodiment of a test structure 100 a differential amplifier cell 102 with bipolar transistors (BJTs) 104A . 104B which are connected in a common emitter configuration. The bases of the transistors are with probe pads 106 . 108 connected with sensor tips 106 . 108 can be brought into contact with a source 126 are connected for a differential signal having the input signal components (S i +1 and S i -1 ). The collectors of the transisitors are with probe contact surfaces 110 . 112 connected with sensor tips 120 . 122 can be brought into contact with a sink 128 are connected for the output signal of the differential cell having the signal components (S o +1 and S o -1 ). The emitters of the matched transistors are interconnected and across a probe tip 124 connected to a bias probe pad 114 can be brought into contact with a DC power source 130 connected, which biases the differential amplifier cell. Each BJT has a parasitic base-collector capacitance (C bc ) 132 which has a frequency-dependent connection between an input and an output of the test structure. To counteract the Miller effect, a compensation capacitor connects 134 , whose capacitance is equal to C bc , the gate of each of the transistors 104A . 104B with the collector of the other transisitor of the differential amplifier cell.
The compensation capacitors may be fabricated as part of the test structure on the wafer to allow for proper matching to the parasitic capacitance of the transistors. On the other hand, the compensation capacitors may be connected across the respective probe tips, which are arranged to contact the appropriate probe pads. Typically, a differential test (probing) is performed with two probes. According to 4 has the differential test structure 200 at least four pads or probe pads, including probe pads 202 . 204 for the input signal components and probe contact surfaces 206 . 208 for the output signal components arranged in a linear pattern and over several conductive vias 216 with the DUT 212 connected below the surface of a wafer 214 is trained. The fifth probe contact surface 210 , over which the DUT is biased, is preferably formed within the linear pattern, but could be offset. The arrangement of the probe pads in a linear pattern allows the test structure to be formed in a saw-toothed trajectory (represented by a staple) 218 between chips 220 whereby the wafer area occupied by the test pattern can be reduced, serving no purpose after the dies are singulated. The linear array of probe pads also allows for a test using a single probe that has a linear array of at least four probe tips 222 . 224 . 226 . 228 having on the surfaces of a dielectric plate 232 may be formed and arranged so that they can be positioned aligned with the sensor contact surfaces for the input and output signals. The fifth probe tip 230 , over which the DUT is biased, is preferably made in the linear array of probe tips, but could also be offset or at a different angle with respect to the wafer. The linear arrangement of the probe tips facilitates the manufacture of conductors 234 and compensation capacitors 236 that the sensor tips 222 . 224 which transmit the input signals to the two transistors of the differential amplifier cell of the DUT, and the probe tips 226 . 228 connect each other, which transmit the output signals for the two transistors of the differential amplifier cell of the DUT.
During integrated circuit (IC) fabrication, it is desirable to be able to easily determine whether the transistors included in the integrated circuits are functioning. 5 shows an easy to test go / no-go test structure 150 with a differential amplifier cell 152 with circuit elements fabricated by the same process and in the same layers of the wafer as the elements of the marketable integrated circuits corresponding to them. The test structure has compensation capacitors 156 on which the gate of each transistor 154A . 154B with the drain electrode of its counterpart 154B respectively. 154A to neutralize the Miller effect generated by the parasitic gate-drain capacitance (C gd ) and to stabilize the input impedance of the test structure. A resistor network with resistors 178 connects the signal input probe tips 168 . 170 , which are arranged to match the input transducer pads 158 . 160 ver bindable, with the signal source 74 , Similarly, the signal output probe pads 162 . 164 over sensor tips 172 . 174 and resistances 182 . 184 with the signal sink 78 connected. The test structure is over the probe contact surface 166 and the probe tip 176 biased, which via the bias resistor 186 connected to ground. The resistors on all terminations stabilize the DC operation of the amplifier and prevent it from oscillating by reducing the Q factor of resonances caused by the capacitance tive and inductive parasitic connections of the device are generated. The resistance values of the resistors are selected to provide stable operation and a suitable gain of preferably about one. Data is collected by testing multiple pairs of transistors known to be functional. By comparing this data with data obtained by testing on-wafer test structures, a Go / No-Go criterion of transistor performance is provided which can be readily used during the manufacturing process.
Input impedance of a test structure containing a differential amplifier cell
is connected by connecting the gate electrode of a transistor
with the drain electrode
of the second transistor of the differential pair is stabilized by a capacitor,
its capacity value
that of the parasitic
Gate-drain (base-collector) capacity of the device
the above detailed
Description were for
a comprehensive understanding
the present invention shown specific details. For professionals
However, it can be seen that the present invention also without
these special details is feasible. Otherwise, are known
Methods, procedures, components and circuits are not described in detail
to avoid the present invention becoming unclear.
all references cited herein are incorporated by reference.
used in the foregoing description are terms and expressions
as terms and expressions
the description and not in a limiting sense, and
By using these terms and expressions, equivalents of the illustrated
and described features or parts thereof are not excluded
and it will be appreciated that the scope of the invention is limited
through the attached
defined and restricted
Test structure and probe for differential
The present invention will be a test structure with a differential
Amplifier cell and
a differential signal sensor provided, wherein
the Miller effect is compensated by the frequency-dependent change
the input impedance of the test structure is reduced.