DE112007001435T5 - Test structure and probe for differential signals - Google Patents

Test structure and probe for differential signals

Info

Publication number
DE112007001435T5
DE112007001435T5 DE200711001435 DE112007001435T DE112007001435T5 DE 112007001435 T5 DE112007001435 T5 DE 112007001435T5 DE 200711001435 DE200711001435 DE 200711001435 DE 112007001435 T DE112007001435 T DE 112007001435T DE 112007001435 T5 DE112007001435 T5 DE 112007001435T5
Authority
DE
Germany
Prior art keywords
probe
contact surface
output signal
input signal
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE200711001435
Other languages
German (de)
Inventor
Richard L. Portland Campbell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
FormFactor Beaverton Inc
Original Assignee
Cascade Microtech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US81311906P priority Critical
Priority to US60/813,119 priority
Priority to US11/710,149 priority
Priority to US11/710,149 priority patent/US7403028B2/en
Application filed by Cascade Microtech Inc filed Critical Cascade Microtech Inc
Priority to PCT/US2007/010801 priority patent/WO2007145728A2/en
Publication of DE112007001435T5 publication Critical patent/DE112007001435T5/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2884Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2621Circuits therefor for testing field effect transistors, i.e. FET's
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2822Testing of electronic circuits specially adapted for particular applications not provided for elsewhere of microwave or radiofrequency circuits

Abstract

A test structure including a differential amplifier cell having a first input signal probe pad capacitively coupled to a first output signal probe pad and a second input signal probe pad capacitively coupled to a second output signal probe pad, the test structure comprising:
(a) a first compensation capacitor connecting the first input signal probe pad and the second output signal sensor contact pad, and
(b) a second compensation capacitor connecting the second input signal probe pad and the first output signal sensor pad.

Description

  • Cross reference to related Registrations
  • The The present application claims the effect of June 12, 2006 submitted provisional U.S. Patent Application No. 60 / 813,120.
  • Background of the invention
  • The The present invention relates to the testing of wafers (wafer probing) and in particular sensors and test structures for testing wafers using differential Signals.
  • integrated Circuits (ICs) are economically attractive because of large numbers often complex circuits, such as microprocessors, on the surface a wafer or substrate can be produced inexpensively. To The manufacturing process involves individual dies, which are one or more circuits have, separated or isolated and enclosed in a housing, by the electrical connections between the outside of the housing and the circuit can be provided on the enclosed chip. The separation and the Einhausen of a chip claim a substantial Part of the manufacturing cost of the integrated circuit chip, and to monitor and controlling the IC manufacturing process and avoiding costs for the Einhausen defective chips add The wafer usually produces electrical circuits or Add test structures to enable on-wafer testing or on-wafer probing, and to verify the characteristics of the integrated circuits, before the chips are separated.
  • A Test structure typically has one device-under-test (DUT), several metallic probe pads or pads (bond pads), the on the wafer surface are applied, and a plurality of conductive vias or vias on that the pads connect with the DUT, which is typically below the surface of the Wafers is made. The DUT typically includes a simple one Circuit, which is a copy of one or more of the basic elements the integrated circuit has, for. B. a single line from a conductive Material, a series of vias, or a single one Transistor. The circuit elements of the DUT typically become through the same process and in the same layers of the chip made as the corresponding elements of the integrated circuit. The ICs are typically characterized on the wafer (on-wafer), the test structure generates a signal generated by a test instrument supplied and the response of the test structure to the signal is measured. Because the circuit elements of the DUT through the same process as the corresponding elements of the integrated circuit are manufactured, is expected that the electrical properties of the DUT for the electrical Properties of the corresponding components of the integrated circuit representative are.
  • at higher Frequencies will usually take an on-wafer characterization below Using a network analyzer. The network analyzer has a source for an alternating current signal, which is normally a radio frequency (RF) signal that is used to excite the DUT of a test structure. A forward / reverse switch leads the Excitation signals to one or more pads of the test structure to. directional or bridges key the forward or test structure running to the test structure returning backward waves from. These signals are divided by intermediate frequency (IF) sections of the Down-converted network analyzer, where the signals for a further processing and representation filtered, amplified and be digitized. As a result, several s-parameters (scattering parameters) are obtained, the the relationship a normalized voltage wave having the response of the DUT, to a normalized voltage wave, the by the Signal source supplied Has suggestion.
  • The preferred connection for transmitting Signals between the signal source and the receiver of the network analyzer and the test structure is a coaxial cable. For the transition between the coaxial cable and the contact surfaces The test structure is preferably provided with a movable sensor one or more conductive probe tips, which are arranged so that they with the contact surfaces of Test structure aligned are positionable. The network analyzer and the test structure can temporarily be joined together by the sensor tips with the contact surfaces of the Test structure are brought into contact.
  • integrated Circuits typically have a ground plane at the bottom of the substrate on which the active and passive components of the Circuit are produced. The connections of the on a semiconductor substrate formed transistors are typically capacitive across the substrate connected to the ground plane. The impedance of this parasitic capacitive Connection is frequency-dependent, and at high frequencies become the ground potential and the true ones Characteristics of ground-based (single-ended) signals uncertain.
  • Balanced devices are more tolerant of poor radio frequency (RF) grounding as single-ended devices, making them attractive for high performance ICs. Referring to 1 is a differential amplifier cell 20 a symmetrical device with two nominally identical circuit halves 20A . 20B , Biased by a DC source 22 and excited by a differential mode signal, the common mode and even mode (odd) mode components having the same amplitude and opposite phases (S i +1 and S i -1 ) 24 . 26 has, is at the axis of symmetry 28 the two circuit halves generates a virtual mass. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the excitation signal. The quality of the virtual ground of a balanced device is independent of the physical ground path, so that balanced or differential circuits can tolerate inferior RF grounding better than circuits operated with single-ended signals. The two waveforms of the differential output signal (S o +1 and S o -1 ) 30 . 32 represent mutual references that provide greater certainty in determining the transition from one to another binary value and allow for a reduction in the voltage swing of the signal and a faster transition between binary values. Typically, differential devices can operate at lower signal power and higher data rates than single-ended devices. In addition, noise from external sources, such as adjacent conductors, tends to electrically and electromagnetically couple to common mode and cancel out in the differential mode. As a result, symmetric or differential circuits have good immunity to noise at even harmonic frequencies because signals that are out of phase at the fundamental frequency are in phase with the even harmonics. Improved tolerance for inferior RF grounding, increased resistance to noise, and reduced signal power make differential devices attractive for operation at higher frequencies.
  • A DUT with a differential amplifier cell provides a basis for a test structure that enables high frequency on-wafer analysis of devices included in the marketable integrated circuits fabricated on the wafer. However, the impedance of the internal connections of the DUT components is often frequency-dependent, which makes it difficult to de-embed or disintegrate the DUT and affect test accuracy. For example, the input and output of a differential amplifier cell, e.g. B. the differential amplifier cell 20 normally capacitively connected due to parasitic capacitances connecting the terminals of the cell transistors. The parasitic capacity 42 between the gate electrode 38 . 40 and the drain electrode 34 . 36 , a result of diffusion of the drain dopant under the oxide of the gate electrode, is intrinsic and typical in MOS transistors. As a result of the transistor gain, a change in the gate voltage produces an even greater change in the voltage at the drain of the transistor. Applying different voltages to the terminals of the parasitic gate-drain capacitance (C gd ) causes the capacitor to behave like a much larger capacitance; a phenomenon known as the Miller effect. As a result, the input impedance of the differential device substantially changes with the frequency, whereby an unstable operation of the differential device is obtained.
  • What therefore desirable are a method and an apparatus for testing a differential device, by which the Miller effect is minimized or eliminated.
  • Brief description of the drawings
  • 1 shows a schematic diagram of a symmetrical device;
  • 2 shows a schematic representation of a sensor and a differential test structure with field effect transistors and a pair of Miller effect neutralizing capacitors;
  • 3 shows a schematic representation of a probe and a differential test structure with bipolar transistors (BJTs) and a pair of Miller effect neutralizing capacitors;
  • 4 shows a perspective view of a test structure and a probe; and
  • 5 shows a schematic representation of a differential test structure for a go / no-go test of the functionality of a transistor.
  • Detailed description more preferred embodiments
  • Reference is made in detail to the drawings, in which like parts are designated by like reference numerals, and in particular 1 in which a differential amplifier cell 20 a symmetrical device with two nominally identical circuit halves 20A . 20B is. Im by a DC source 22 biased state and excited by a differential mode signal, the common mode and differential mode components having the same amplitude and opposite phases (S i +1 and S i -1 ) 24 . 26 is at the axis of symmetry 28 the two circuit halves generates a virtual mass. At the virtual ground, the potential at the operating frequency does not change with time regardless of the amplitude of the excitation signal. The quality of the virtual ground of a balanced device is independent of the physical ground path, so that balanced or differential circuits can tolerate poor RF grounding better than circuits operated with single-ended (ground related) signals. Also, differential devices typically can operate at lower signal power and at higher data rates than single-ended devices, and have good immunity to noise from external sources, such as adjacent conductors, including noise at even harmonic frequencies.
  • However, the response of integrated circuits, including differential amplifier cell testing structures, to high frequency signals is typically frequency dependent. Integrated circuits are fabricated by depositing layers of semiconductor and insulating materials on a semiconductor substrate, with intrinsic frequency dependent connections normally present between the various elements of the fabricated devices. Such an intrinsic frequency-dependent connection connects the gate and drain electrodes of MOS transistors and the bases and collectors of bipolar transistors (BJTs). For example, an intrinsic parasitic capacitance (C gd ) connects the gate and drain of a typical MOS transistor because the drain dopant diffuses under the oxide of the gate of the transistor. As the frequency of the excitation signal increases, the impedance between the gate and drain of the transistor changes, thereby changing the input impedance of the differential amplifier cell. In addition, due to the gain of the transistor, any voltage change at the gate of the transistor is amplified at the drain of the transistor, whereby the parasitic capacitance (C gd ) appears as a much larger capacitor; a phenomenon known as the Miller effect.
  • The inventors recognized that the signals transmitted by the respective transistors of the differential amplifier cell are mirror images and concluded that the Miller effect could be minimized or eliminated and the input impedance of a differential amplifier cell test structure could be stabilized by passing the gate of a transistor over a capacitor whose capacitance is equal to the parasitic gate-drain capacitance (C gd ) is connected to the drain of the second transistor.
  • Referring to 2 has a test structure 50 a differential amplifier cell 51 with transistors 52A . 52B on. The gate electrodes of the respective transistors are with sensor contact pads 54 . 56 connected. Probe tips 64 . 66 , which are arranged so that they are positioned with the probe contact surfaces aligned, are with a source 74 for a differential input signal having the signal component S i +1 and its differential complementary signal S i -1 . The source of the differential signal is typically one in a network analyzer 76 arranged high frequency (HF) source. The network analyzer also has a sink 78 for the output of the test structure having components (S o +1 and S o -1 ). The respective components of the output signal are from the drains of the transistors to probe contact surfaces 58 . 60 transmit that across sensor tips 68 . 70 can be connected to the signal sink. The sources of the transistors are connected to each other and to a bias probe pad 62 connected with a probe tip 72 can be brought into contact. The probe tip is powered by a DC source 80 which provides the bias for the differential amplifier cell.
  • In every transistor 52A . 52B is an intrinsic parasitic capacitance (C gd ) 82A . 82B which connects the respective gate and drain electrodes constituting the input terminals and the output terminals of the test pattern. The gain (A) of the transistor amplifies a change in the voltage (dV) at the gate of a transistor at the drain (A * V), whereby opposite sides of the parasitic capacitance experience different voltages. As a result of a phenomenon known as Miller effect, the parasitic capacitance (C gd ) has the effect of a larger capacitor, whereby the input impedance of the test structure changes substantially with frequency. To reduce or eliminate the effect of the parasitic gate-drain capacitance and to provide a more constant input impedance to the test structure, a compensation capacitor is used 84A . 84B from the gate of each transistor, e.g. B. the gate electrode of the transistor 52A , connected to the drain of the second transistor of the differential amplifier cell, e.g. B. with the drain electrode of the transistor 52B , The compensation capacitor has a capacitance value equal to the value C gd . Because the transistors of the differential amplifier cell are matched and the phase of the differential input signal component S i + 1 is shifted by 180 ° with respect to the phase of the differential output signal component S o -1 , the voltage change at the drain caused by the gate-drain capacitance is Electrode of the transistor, z. B. A · dV shifted by the voltage at the compensation capacitor # (-A · dV), so the input impedance of the test structure remains constant.
  • Referring to 3 shows another exemplary embodiment of a test structure 100 a differential amplifier cell 102 with bipolar transistors (BJTs) 104A . 104B which are connected in a common emitter configuration. The bases of the transistors are with probe pads 106 . 108 connected with sensor tips 106 . 108 can be brought into contact with a source 126 are connected for a differential signal having the input signal components (S i +1 and S i -1 ). The collectors of the transisitors are with probe contact surfaces 110 . 112 connected with sensor tips 120 . 122 can be brought into contact with a sink 128 are connected for the output signal of the differential cell having the signal components (S o +1 and S o -1 ). The emitters of the matched transistors are interconnected and across a probe tip 124 connected to a bias probe pad 114 can be brought into contact with a DC power source 130 connected, which biases the differential amplifier cell. Each BJT has a parasitic base-collector capacitance (C bc ) 132 which has a frequency-dependent connection between an input and an output of the test structure. To counteract the Miller effect, a compensation capacitor connects 134 , whose capacitance is equal to C bc , the gate of each of the transistors 104A . 104B with the collector of the other transisitor of the differential amplifier cell.
  • The compensation capacitors may be fabricated as part of the test structure on the wafer to allow for proper matching to the parasitic capacitance of the transistors. On the other hand, the compensation capacitors may be connected across the respective probe tips, which are arranged to contact the appropriate probe pads. Typically, a differential test (probing) is performed with two probes. According to 4 has the differential test structure 200 at least four pads or probe pads, including probe pads 202 . 204 for the input signal components and probe contact surfaces 206 . 208 for the output signal components arranged in a linear pattern and over several conductive vias 216 with the DUT 212 connected below the surface of a wafer 214 is trained. The fifth probe contact surface 210 , over which the DUT is biased, is preferably formed within the linear pattern, but could be offset. The arrangement of the probe pads in a linear pattern allows the test structure to be formed in a saw-toothed trajectory (represented by a staple) 218 between chips 220 whereby the wafer area occupied by the test pattern can be reduced, serving no purpose after the dies are singulated. The linear array of probe pads also allows for a test using a single probe that has a linear array of at least four probe tips 222 . 224 . 226 . 228 having on the surfaces of a dielectric plate 232 may be formed and arranged so that they can be positioned aligned with the sensor contact surfaces for the input and output signals. The fifth probe tip 230 , over which the DUT is biased, is preferably made in the linear array of probe tips, but could also be offset or at a different angle with respect to the wafer. The linear arrangement of the probe tips facilitates the manufacture of conductors 234 and compensation capacitors 236 that the sensor tips 222 . 224 which transmit the input signals to the two transistors of the differential amplifier cell of the DUT, and the probe tips 226 . 228 connect each other, which transmit the output signals for the two transistors of the differential amplifier cell of the DUT.
  • During integrated circuit (IC) fabrication, it is desirable to be able to easily determine whether the transistors included in the integrated circuits are functioning. 5 shows an easy to test go / no-go test structure 150 with a differential amplifier cell 152 with circuit elements fabricated by the same process and in the same layers of the wafer as the elements of the marketable integrated circuits corresponding to them. The test structure has compensation capacitors 156 on which the gate of each transistor 154A . 154B with the drain electrode of its counterpart 154B respectively. 154A to neutralize the Miller effect generated by the parasitic gate-drain capacitance (C gd ) and to stabilize the input impedance of the test structure. A resistor network with resistors 178 connects the signal input probe tips 168 . 170 , which are arranged to match the input transducer pads 158 . 160 ver bindable, with the signal source 74 , Similarly, the signal output probe pads 162 . 164 over sensor tips 172 . 174 and resistances 182 . 184 with the signal sink 78 connected. The test structure is over the probe contact surface 166 and the probe tip 176 biased, which via the bias resistor 186 connected to ground. The resistors on all terminations stabilize the DC operation of the amplifier and prevent it from oscillating by reducing the Q factor of resonances caused by the capacitance tive and inductive parasitic connections of the device are generated. The resistance values of the resistors are selected to provide stable operation and a suitable gain of preferably about one. Data is collected by testing multiple pairs of transistors known to be functional. By comparing this data with data obtained by testing on-wafer test structures, a Go / No-Go criterion of transistor performance is provided which can be readily used during the manufacturing process.
  • The Input impedance of a test structure containing a differential amplifier cell is connected by connecting the gate electrode of a transistor with the drain electrode of the second transistor of the differential pair is stabilized by a capacitor, its capacity value that of the parasitic Gate-drain (base-collector) capacity of the device approximately like.
  • In the above detailed Description were for a comprehensive understanding the present invention shown specific details. For professionals However, it can be seen that the present invention also without these special details is feasible. Otherwise, are known Methods, procedures, components and circuits are not described in detail to avoid the present invention becoming unclear.
  • On all references cited herein are incorporated by reference.
  • All used in the foregoing description are terms and expressions as terms and expressions the description and not in a limiting sense, and By using these terms and expressions, equivalents of the illustrated and described features or parts thereof are not excluded and it will be appreciated that the scope of the invention is limited through the attached claims defined and restricted is.
  • Summary
  • Test structure and probe for differential signals
  • By The present invention will be a test structure with a differential Amplifier cell and a differential signal sensor provided, wherein the Miller effect is compensated by the frequency-dependent change the input impedance of the test structure is reduced.

Claims (10)

  1. Test structure with a differential amplifier cell, a first input signal probe contact surface, the Capacitive with a first output signal transducer contact surface and having a second input signal probe pad, the capacitive with a second output signal transducer contact area connected, wherein the test structure comprises: (a) a first one Compensation capacitor, the first input signal probe contact surface and the second output signal transducer contact surface connects, and (B) a second compensation capacitor, the second Input signal probe contact surface and the first output signal transducer contact surface connects.
  2. Test structure according to claim 1, wherein the capacitance value of the first compensation capacitor a capacitance value of the connection between the first input signal probe contact surface and the first output signal transducer contact area substantially equal and the capacity value of the second compensation capacitor has a capacitance value of Connection between the second input signal probe contact surface and the second output signal transducer contact surface substantially like.
  3. A probe for testing a differential amplifier cell having a first input probe contact pad capacitively coupled to a first output probe contact pad and a second input probe contact pad capacitively coupled to a second output probe contact pad, the probe comprising: ( a) a first probe tip connectable to a source of a first input signal and arranged to contact the first input signal probe pad of the differential amplifier cell, (b) a second probe tip connectable to a source of a second input signal and being arranged to contact the second input signal probe pad, (c) a third probe tip connectable to and arranged for sinking a first output signal with the first output signal probe (d) a fourth probe tip connectable to a sink for a second output signal and arranged to contact the second output transducer probe pad; (e) a first capacitor carrying the first probe tip the fourth probe tip connects, and (f) a second capacitor which measures the second probe Sensor tip connects to the third probe tip.
  4. probe according to claim 3, wherein the first, the second, the third and the fourth probe tip arranged in a linear pattern.
  5. probe The device of claim 3, wherein the capacitor is the first probe tip with the fourth probe tip connects, a capacity has that capacity the connection between the first input signal probe contact surface and the first output signal transducer contact surface substantially equalizes, and the capacitor, the second probe tip with the third probe tip connects, a capacity that has the capacity of Connection between the second input signal probe contact surface and the second output signal transducer contact surface substantially like.
  6. probe according to claim 5, wherein the first, the second, the third and the fourth probe tip arranged in a linear pattern.
  7. Method for testing a differential amplifier cell with a first input signal probe contact surface, the Capacitive with a first output signal transducer contact surface and a second input signal probe contact surface Capacitive with a second output signal transducer contact surface connected, the method comprising the steps: (A) Connecting the first input signal probe contact surface and the second output signal transducer contact surface a capacitor whose capacity is a connection capacity between the first input signal probe contact surface and approximately equal to the first output signal transducer contact area, and (b) connecting the second input signal probe pad and the first output signal transducer contact surface a capacitor whose capacity is a connection capacity between the second input signal probe contact surface and approximately equal to the second output signal transducer contact area.
  8. Test structure for testing a functionality a transistor, the test structure comprising: (a) one first transistor with: (i) a first port connected via a first resistor with a source of a first component of a differential signal is connectable, (ii) a second one Connection, over a second resistor having a drain for a first component of a Output signal connectable and by a parasitic capacitance with the first connection is connected, and (iii) a third port, (B) a second transistor with: (i) a first port connected via a third resistor with a source of a second component of a differential signal is connectable, (ii) a second one Connection, over a fourth resistor having a drain for a second component of a Output signal connectable and by a parasitic capacitance with the first connection is connected, and (iii) a third port, the one with the third terminal of the first transistor and a bias source connected is, (c) a first compensation capacitor, the the first terminal of the first transistor to the second terminal of the second transistor connects, and (d) a second compensation capacitor, the first terminal of the second transistor with the second Connection of the first transistor connects.
  9. The test structure of claim 8, wherein the first compensation capacitor a capacity which has the first terminal of the first transistor with the substantially equalizing the parasitic capacitance connecting the second terminal of the first transistor, and wherein the second compensation capacitor has a capacitance the first terminal of the second transistor with the second Connecting the second transistor connecting parasitic capacitance substantially like.
  10. Test structure according to claim 8, wherein the first, the second, third and fourth resistances have resistance values, which are selected causing the test structure to have a gain factor of about has one.
DE200711001435 2006-06-12 2007-05-03 Test structure and probe for differential signals Withdrawn DE112007001435T5 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
US81311906P true 2006-06-12 2006-06-12
US60/813,119 2006-06-12
US11/710,149 2007-02-22
US11/710,149 US7403028B2 (en) 2006-06-12 2007-02-22 Test structure and probe for differential signals
PCT/US2007/010801 WO2007145728A2 (en) 2006-06-12 2007-05-03 A test structure and probe for differential signals

Publications (1)

Publication Number Publication Date
DE112007001435T5 true DE112007001435T5 (en) 2009-05-20

Family

ID=38832257

Family Applications (2)

Application Number Title Priority Date Filing Date
DE200711001435 Withdrawn DE112007001435T5 (en) 2006-06-12 2007-05-03 Test structure and probe for differential signals
DE200720018748 Expired - Lifetime DE202007018748U1 (en) 2006-06-12 2007-05-03 Test structure for probes for differential signals

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE200720018748 Expired - Lifetime DE202007018748U1 (en) 2006-06-12 2007-05-03 Test structure for probes for differential signals

Country Status (3)

Country Link
JP (1) JP4870211B2 (en)
DE (2) DE112007001435T5 (en)
WO (1) WO2007145728A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006031646A2 (en) 2004-09-13 2006-03-23 Cascade Microtech, Inc. Double sided probing structures
CN103117536B (en) * 2013-01-15 2014-11-12 费新华 Storage battery protective circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625299A (en) * 1995-02-03 1997-04-29 Uhling; Thomas F. Multiple lead analog voltage probe with high signal integrity over a wide band width
JP2001242214A (en) * 2000-02-28 2001-09-07 Asahi Kasei Microsystems Kk Characteristic measuring circuit of semiconductor
JP2002057288A (en) * 2000-08-09 2002-02-22 Rohm Co Ltd Semiconductor integrated circuit device
US6856126B2 (en) * 2003-01-21 2005-02-15 Agilent Technologies, Inc. Differential voltage probe
JP4151572B2 (en) * 2003-12-16 2008-09-17 株式会社デンソー Transistor pair characteristic difference measuring device and characteristic difference measuring method

Also Published As

Publication number Publication date
WO2007145728A2 (en) 2007-12-21
WO2007145728A3 (en) 2008-05-02
JP4870211B2 (en) 2012-02-08
DE202007018748U8 (en) 2009-08-13
JP2009540331A (en) 2009-11-19
DE202007018748U1 (en) 2009-04-02

Similar Documents

Publication Publication Date Title
Kolding A four-step method for de-embedding gigahertz on-wafer CMOS measurements
US7772868B2 (en) Accurate capacitance measurement for ultra large scale integrated circuits
US6856129B2 (en) Current probe device having an integrated amplifier
US10037926B2 (en) Apparatus and methods for through substrate via test
Kolding On-wafer calibration techniques for giga-hertz CMOS measurements
JP4351632B2 (en) Sensor arrangement and sensor arrangement driving method
Vandamme et al. Improved three-step de-embedding method to accurately account for the influence of pad parasitics in silicon on-wafer RF test-structures
US20080012640A1 (en) Unilateralized amplifier
US6560567B1 (en) Method and apparatus for measuring on-wafer lumped capacitances in integrated circuits
US6838885B2 (en) Method of correcting measurement error and electronic component characteristic measurement apparatus
US6856126B2 (en) Differential voltage probe
CA1278106C (en) Tunable microwave wafer probe
EP1506428B1 (en) Method for calibrating and de-embedding, set of devices for de-embedding and vector network analyzer
Redman-White et al. 1/f noise in passive CMOS mixers for low and zero IF integrated receivers
US7701227B2 (en) High precision voltage source for electrical impedance tomography
US7262626B2 (en) Connection apparatus and cable assembly for semiconductor-device characteristic measurement apparatus
US6480013B1 (en) Method for the calibration of an RF integrated circuit probe
EP0714130B1 (en) Method of manufacturing a capacitive signal transfer device between the chip layers of a vertical integrated circuit
US6998869B2 (en) Semiconductor device characteristics measurement apparatus and connection apparatus
CN101501511A (en) Method of expanding tester drive and measurement capability
US6404222B1 (en) Chip capacitance measurement circuit
Pehlke et al. High-frequency application of MOS compact models and their development for scalable RF model libraries
US6885213B2 (en) Circuit and method for accurately applying a voltage to a node of an integrated circuit
US7099808B2 (en) Capacitance and transmission line measurements for an integrated circuit
US6366098B1 (en) Test structure, integrated circuit, and test method

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G01R 31/28 AFI20070503BHDE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20111201