JP2009535861A - Semiconductor device having superlattice to block dopants and related method - Google Patents

Abstract

  The semiconductor element may include at least one metal-oxide field effect transistor (MOSFET). The at least one MOSFET may include a main portion, a channel layer adjacent to the main portion, and a superlattice for blocking a dopant provided between the main portion and the channel layer. The superlattice for blocking the dopant may include a plurality of stacked groups of a plurality of layers. Each group of superlattice layers blocking the dopant comprises a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion, and at least one layer constrained within the crystal lattice of an adjacent basic semiconductor portion. A non-semiconductor molecular layer may be included.

Description

  The present invention relates to the semiconductor field. More specifically, the present invention relates to semiconductors having improved properties based on energy band engineering and methods related thereto.

  Structures and methods have been proposed for improving the performance of semiconductor devices, such as improving charge carrier mobility. For example, Patent Document 1 discloses a strained material layer made of silicon, silicon-germanium, and relaxed silicon. These material layers also have regions that do not contain impurities so as not to cause performance degradation. As a result of the biaxial strain in the upper silicon layer, the carrier mobility changes. Thereby, a higher speed and / or lower power consumption element is possible. Patent Document 2 discloses a CMOS inverter based on the same strained silicon technology.

  Patent Document 3 discloses a semiconductor element in which a conduction layer and a valence band of a second silicon layer are affected by tensile strain by having silicon and a carbon layer sandwiched between silicon layers. It is believed that the n-channel MOSFET has a higher mobility because electrons having a smaller effective mass and electrons induced by the electric field applied to the gate electrode are confined to the second silicon layer.

  Patent Document 4 discloses a superlattice in which a plurality of layers including less than eight layers and a plurality of layers including a fractional compound, that is, a binary compound semiconductor layer are alternately epitaxially grown. The direction in which the current mainly flows is perpendicular to the superlattice layer.

  Patent Document 5 discloses a Si—Ge short period superlattice in which high mobility is realized by reducing alloy scattering in the superlattice. In line with this policy, Patent Document 6 discloses a MOSFET having a channel layer having an alloy of silicon and a second material. In the MOSFET, the mobility is improved by the presence of the replacement of the second material in the silicon lattice in such a ratio that the channel layer is subjected to tensile strain.

Patent Document 7 discloses a quantum well having two barrier regions and an epitaxially grown semiconductor thin film sandwiched between the barrier layers. Each barrier region is typically composed of a repeating layer of SiO ₂ / Si having a thickness in the range of 2 to 6 molecular layers. A fairly thick silicon part is sandwiched between the barriers.

  Non-patent document 1 titled “Phenomena in silicon nanostructure device” by Tsu discloses a semiconductor-atomic superlattice (SAS) composed of silicon and oxygen. is doing. Si / O superlattices are disclosed as being useful as silicon quantum devices and light emitting devices. In particular, a green electroluminescent diode structure has been constructed and tested. The current in the diode structure flows vertically, ie perpendicular to the SAS layer. The disclosed SAS may have semiconductor layers separated by adsorbing species such as oxygen atoms and CO molecules. It can be said that the growth of silicon on the adsorbed oxygen molecular layer is an epitaxial growth with a considerably low defect density. One SAS structure has a silicon portion of 1.1 nm thickness, which is about 8 atomic layers of silicon, and the other SAS structure has twice the thickness of this silicon. Non-patent document 2 entitled “Chemical Design of Direct-Gap Light-Emitting Silicon” by Luo et al. Is discussed further.

  Patent Document 8 discloses a barrier that is composed of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby reducing the current flowing vertically through the lattice by less than four orders of magnitude. The insulating / barrier layer allows low defect silicon to be epitaxially grown on the insulating layer.

  Patent Document 9 discloses that the principle of an aperiodic photonic band gap (APBG) structure is compatible with electronic band gap engineering. In particular, the application discloses that by adjusting material parameters such as the position of the band minimum, effective mass, etc., a new aperiodic material having the desired band structure characteristics can be obtained. Other parameters such as conductivity, thermal conductivity, dielectric constant, or permeability are also disclosed as enabling material design.

In material engineering, despite significant efforts to increase the mobility of charge carriers in semiconductor devices, significant improvements are still needed. Increasing mobility is thought to increase device speed and / or decrease device power consumption. By increasing the mobility, it is possible to maintain the performance of the element while continuing to reduce the characteristic part of the element. Moreover, as the size of the device decreases, the regions within the device approach each other and dopant diffusion between the regions can become a problem. For example, in a MOSFET device, dopants or the like from a substance injected into the main part may diffuse into the channel of the device, thereby degrading the device performance.
US Patent Application Publication No. 2003/0057416 US Patent Application Publication No. 2003/0034529 U.S. Pat. U.S. Pat. No. 4,937,204 U.S. Pat.No. 5,357,119 U.S. Patent No. 5683934 U.S. Pat.No. 5,216,262 International Publication No. 2002/103767 Pamphlet UK Patent Application No. 2347520 US Patent Application No. 10/647069 US Patent Application No. 10/467069 Tsu, Applied Physics and Materials Science & Processing, pp.391-402, published online 6 September 2000 Luo et al., Physical Review Letters, Vol. 89, August 12, 2002

  In view of the above background, an object of the present invention is to provide a semiconductor device having a dopant blocking layer that mitigates channel degradation caused by dopant diffusion.

  The above and other objects, features and advantages of the present invention are provided by a semiconductor device having at least one metal-oxide field effect transistor (MOSFET). More specifically, the at least one MOSFET may have a main portion, a channel layer adjacent to the main portion, and a superlattice for blocking a dopant provided between the main portion and the channel layer. . The superlattice for blocking the dopant may include a plurality of stacked groups of a plurality of layers. Each group of superlattice layers blocking the dopant comprises a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion, and at least one layer constrained within the crystal lattice of an adjacent basic semiconductor portion. A non-semiconductor molecular layer may be included.

  Due to the superlattice layer structure and the constrained non-semiconductor molecular layer, the superlattice advantageously prevents unintentional dopant diffusion between the main portion and the channel layer. In addition, the thickness of the superlattice blocking the dopant may be relatively thin. In addition, the superlattice can be used in certain applications in addition to the ability to block dopants, for example, when a portion of a MOSFET channel is formed in a superlattice that blocks the dopant. It also enjoys improved mobility characteristics.

In addition, the main part may have at least one doped region therein. As an example, the main portion may have a dopant concentration greater than about 1 × 10 ¹⁸ cm ⁻³ . Further, the channel layer may be substantially undoped, that is, may have a dopant concentration of, for example, less than about 1 × 10 ¹⁵ cm ⁻³ . At least one of the group of superlattice layers blocking the dopant may also be substantially undoped.

  For example, the basic semiconductor may include silicon, and the at least one non-semiconductor molecular layer may include oxygen. In particular, the at least one non-semiconductor molecular layer may basically include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

  The at least one MOSFET further includes a gate that is on the channel layer and has a gate insulating layer adjacent to the channel layer, and a gate electrode that is adjacent to the gate insulating layer and faces the channel layer. In addition, the source and drain regions may be laterally adjacent to the channel layer.

  The at least one non-semiconductor molecular layer may be a single molecular layer thick. The basic semiconductor portion may have a thickness of less than 8 molecular layers. For example, all the basic semiconductor portions may have the same number of molecular layers. Alternatively, at least a part of the basic semiconductor portion may have a different number of molecular layers. In addition, the basic semiconductor molecular layers facing and included in the adjacent group of superlattice layers may be chemically bonded together.

  Another embodiment of the present invention relates to a method for manufacturing a semiconductor element. The method may include the step of producing at least one MOSFET. The at least one MOSFET includes forming a main portion, forming a superlattice blocking a dopant adjacent to the main portion, and a channel facing the main portion adjacent to the superlattice blocking the dopant. It is produced by a step of forming a layer. More specifically, the superlattice for blocking the dopant may include a plurality of stacked groups composed of a plurality of layers. Each group of superlattice layers blocking the dopant comprises a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion, and at least one layer constrained within the crystal lattice of an adjacent basic semiconductor portion. A non-semiconductor molecular layer may be included.

  Due to the superlattice layer structure and the constrained non-semiconductor molecular layer, the superlattice advantageously prevents unintentional dopant diffusion between the main portion and the channel layer. In addition, the thickness of the superlattice blocking the dopant may be relatively thin. In addition, the superlattice can be used in certain applications in addition to the ability to block dopants, for example, when a portion of a MOSFET channel is formed in a superlattice that blocks the dopant. It also enjoys improved mobility characteristics.

  The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments are shown. However, the invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout this specification, the same reference numbers will refer to the same elements, and the dash will be used to refer to similar elements in alternative embodiments.

  The present invention relates to improving the performance of semiconductor devices by controlling the properties of semiconductor materials at the atomic or molecular level. The present invention further relates to identifying, making, and utilizing improved materials for use in the conduction path of semiconductor devices.

で与えられ、正孔については、

で与えられる。ここでfはフェルミ-ディラック分布関数、E_Fはフェルミエネルギー、Tは温度、E(k,n)は波数ベクトルk及びn番目のエネルギーバンドに対応する状態での電子のエネルギー、指数i及びjはガリレオ座標x,y,及びzを意味し、積分はブリュアンゾーン(B.Z.)全体で取られ、かつ総和は、電子のフェルミエネルギーよりも高いエネルギーを有するバンドについて、及び正孔のフェルミエネルギーよりも低いエネルギーを有するバンドについて、それぞれ取られている。 Applicants hypothesize that certain superlattices described herein reduce the effective mass of charge carriers and thereby increase the mobility of charge carriers. However, applicants are not obsessed with that hypothesis. Effective mass is described by various definitions in the reference. Applicants used “conductivity reciprocal effective mass tensor”, M _e ⁻¹ and M _h ⁻¹ as an indicator that the effective mass was improved. The conductive inverse effective mass tensor M _e ^{−1 for} electrons and the conductive inverse effective mass tensor M _h ⁻¹ for holes are respectively defined as follows. For electronics

For holes,

Given in. Where f is the Fermi-Dirac distribution function, E _F is the Fermi energy, T is the temperature, E (k, n) is the energy of the electron in the state corresponding to the wave vector k and the nth energy band, the indices i and j Means Galileo coordinates x, y, and z, the integral is taken over the entire Brillouin zone (BZ), and the sum is greater for bands with higher energy than the electron Fermi energy and more than the hole Fermi energy Each of the bands with low energy is taken.

  Applicants' definition of a conductive inverse effective mass tensor is such that the corresponding component becomes larger, which increases the tensor component for the conductivity of the material. To reiterate, Applicants have found that the superlattices described herein determine the value of the conductive inverse effective mass tensor and the material's conduction properties, such as the preferred direction of charge carrier transport, typically. I hypothesized that it would be set to improve. However, applicants are not obsessed with that hypothesis. The reciprocal of the appropriate tensor element is called the conductive effective mass. In other words, to evaluate the structure of the semiconductor material, the above-described conductive effective mass for electrons / holes calculated for the intended carrier transport direction is used to define the improved material.

  By using the above-mentioned index, a material having an improved band structure can be selected for a specific purpose. One such example is a superlattice material 25 for a channel region in a semiconductor device. Here, a planar MOSFET 20 having a superlattice 25 according to the present invention will be described first with reference to FIG. However, one of ordinary skill in the art will readily appreciate that the materials specified herein can be used in many different types of semiconductor devices, such as discrete devices and / or integrated devices. As another example, another application where the superlattice 25 can be used as a dielectric interface layer is FINFET.

  The illustrated MOSFET 20 has a substrate 21 having one or more main body implants 29 therein. Lightly doped source / drain extension regions 22 and 23 and heavily doped source / drain regions 26 and 27 are also implanted in the substrate 21. As shown, channel layer 24 extends between lightly doped source / drain extension regions 22,23. The superlattice 25 is provided between the main implant 29 and the channel layer 24 to be advantageous as a dopant blocking layer that prevents dopants from diffusing into the channel.

More particularly, one or more main implants 29 may be used to set the voltage threshold (V _T ) of the MOSFET 20 and / or mitigate the punch-through effect. This will be apparent to those skilled in the art. As an example, such an implant into the main body may have a dopant concentration greater than about 1 × 10 ¹⁸ cm ⁻³ . However, in many applications it is desirable to have a channel that is substantially undoped. “Substantially undoped” means that no dopant is intentionally added. However, it will be apparent to those skilled in the art that impurities may still be present by the semiconductor process. As such, the dopant concentration in the substantially undoped channel layer is preferably, for example, less than about 1 × 10 ¹⁵ cm ^{−3 and} less than about 5 × 10 ¹⁴ cm ^−3. It is considered more preferable.

  In typical prior art MOSFET devices where the channel exists directly on the implant into the main body, it may be difficult to prevent the dopant from diffusing into the channel. The superlattice 25 advantageously prevents unintentional diffusion of dopants present between the main portion and the channel layer 24 due to its structure. This will be further described later.

  The gate dielectric layer 37 (shown in FIG. 1 as being dotted) is on the superlattice 25, and the gate electrode layer 36 is on and above the gate dielectric layer. On the other side of the grid. The illustrated MOSFET 20 is provided with sidewall spacers 40, 41 and silicide layers 30, 31 are provided on the corresponding lightly doped source / drain regions 22, 23. A silicide layer 34 is present on the gate electrode layer 36.

  Applicants have identified an improved material or structure for use in the superlattice 25 of MOSFET20. More specifically, Applicants have identified materials or structures having an energy band structure in which the appropriate conductive effective mass of electrons and / or holes is substantially less than the corresponding value in silicon.

  Referring now also to FIGS. 2 and 3, the material or structure is in the form of a superlattice 25. The structure is controlled at the atomic or molecular level and can be made using known atomic or molecular layer deposition methods. As best understood by referring to the schematic cross-sectional view of FIG. 2 in detail, the superlattice 25 has a group 45a-45n consisting of a plurality of layers arranged in a stacked state.

  Each of the plurality of layers 45a-45n of the superlattice 25 includes a plurality of stacked basic semiconductor molecular layers 46, and an energy band modifying layer 50 thereon, defining each corresponding basic semiconductor portion 46a-46n. Have The energy band correction layer 50 is illustrated in a dotted manner in FIG. 2 for easy understanding.

  As shown, the energy band correction layer 50 has one non-semiconductor molecular layer constrained within the crystal lattice of the adjacent basic semiconductor portion. That is, the basic semiconductor molecular layers 46 facing each other in the adjacent group of layers 45a-45n are chemically bonded together. For example, in the case of the silicon molecular layer 46, some of the silicon atoms in the upper molecular layer group 46a, ie, the upper semiconductor molecular layer, are covalently bonded to the lower part of the group 46b, ie, some silicon atoms in the bottom molecular layer. As a result, the crystal lattice can be continued through a group of a plurality of layers despite the presence of (a plurality of) non-semiconductor molecular layers (for example, (a) oxygen molecule layers). Of course, since silicon atoms in each of the opposing silicon layers of adjacent groups 45a-45n are bonded to non-semiconductor atoms (ie, oxygen in this example), they are completely between adjacent silicon layers of adjacent groups 45a-45n. There is no pure covalent bond. This will be apparent to those skilled in the art.

  In other embodiments, such molecular layers can be more than one. By way of example, it may be preferred that the number of non-semiconductor molecular layers in the energy band correction layer 50 be less than about 5 molecular layers in order to provide the desired energy band correction characteristics.

  It should be noted that a non-semiconductor or semiconductor molecular layer herein means a non-semiconductor or semiconductor when the material used for the molecular layer is bulk. Thus, for example, a semiconductor monolayer material may not necessarily exhibit the same properties as when a bulk or relatively thick layer is formed. This will be apparent to those skilled in the art.

  Applicants have determined that the energy band correction layer 50 and adjacent basic semiconductor portions 46a-46n have a suitable effective charge carrier conduction mass in the direction of the parallel layers in the superlattice 25, the energy band correction layer 50 and adjacent The hypothesis was made that the basic semiconductor portions 46a-46n to be made smaller than the prior art that does not exist. However, applicants are not obsessed with that hypothesis. From another perspective, this parallel direction is perpendicular to the stacking direction. The band modifying layer 50 may also be such that the superlattice 25 has a common energy band structure so that the superlattice 25 functions advantageously as an insulator in its vertical direction. Moreover, as described above, this structure also advantageously provides a barrier to the supply or diffusion of dopants and / or materials between layers that are above and below the superlattice 25 in the vertical direction.

  Further, it was hypothesized that a semiconductor device such as the MOSFET 20 shown in the drawing enjoys a larger charge carrier mobility based on a conductive effective mass smaller than that of the prior art. In some embodiments, the superlattice 25 may further include a substantially direct transition band gap as a result of the band engineering achieved by the present invention. As will be described in detail later, the direct transition type band gap is considered to be particularly advantageous for an optoelectronic device, for example. Of course, not all of the above properties of the superlattice 25 have to be utilized for every application. For example, in some applications, the superlattice 25 may utilize only its dopant blocking / insulating properties, or improved mobility. Alternatively, in other applications, the superlattice 25 may utilize both its dopant blocking / insulating properties and improved mobility. This will be apparent to those skilled in the art.

  Moreover, in some embodiments, the superlattice 25 may also be advantageously used to provide the channel region 24 because the appropriate conductive effective mass of charge carriers is reduced as described above in the parallel layer directions. More specifically, in the illustrated embodiment, the channel layer 24 of the MOSFET 20 is the cap layer 52 of the superlattice 25. That is, the illustrated superlattice 25 is fabricated with sufficient thickness so that a portion of the channel is defined within the upper group (s) of the superlattice layer 45. For example, in other embodiments, a second channel superlattice layer may be grown on superlattice 25 that blocks dopants. Further details on the use of the superlattice for the channel of the semiconductor element are provided in Patent Document 10.

  The cap layer 52 is present on the upper layer group 45 n of the superlattice 25. The cap layer 52 may include a plurality of basic semiconductor molecular layers 46. The cap layer 52 may have 2 to 100 basic semiconductor molecular layers, and more preferably 10 to 50 molecular layers. Similarly, other thicknesses may be used.

  Each basic semiconductor portion 46a-46n may comprise a basic semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, the term group IV semiconductor also includes group IV-IV semiconductors. This will be apparent to those skilled in the art. More specifically, the basic semiconductor may comprise at least one of silicon and germanium, for example.

  Each energy band modifying layer 50 may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen, for example. Non-semiconductors also aid in fabrication because they are thermally stable during the deposition of the next layer. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with a given semiconductor process. This will be apparent to those skilled in the art. More particularly, the basic semiconductor may comprise at least one of, for example, silicon and germanium.

  It should be noted that the term “molecular layer” is meant to include monoatomic and monomolecular layers. It should also be noted that the energy band modifying layer 50 provided by the monolayer is meant to include molecular layers that do not occupy all possible sites. For example, referring in detail to the atomic scale diagram of FIG. 4, a 4/1 repeat structure is illustrated, using silicon as the basic semiconductor material and oxygen as the energy band modifying material. Only half of the possible sites for oxygen are occupied.

  In other embodiments and / or different materials, it is not necessarily a problem that this half is occupied, as will be apparent to those skilled in the art. In particular, even in this schematic, it can be seen that the individual oxygen atoms in a given molecular layer are not strictly aligned along the flat surface. This is obvious to those skilled in the art. By way of example, a suitable occupation range is about 1/8 to 1/2 of all possible oxygen sites. However, other numbers may be used depending on the embodiment.

  Silicon and oxygen are widely used at present in conventional semiconductor processes. Thus, manufacturers can readily use these materials described herein. Atomic or molecular deposition is also widely used today. Accordingly, a semiconductor device comprising a superlattice 25 according to the present invention can be readily implemented and implemented. This will be apparent to those skilled in the art.

  For example, for a superlattice such as a Si / O superlattice, it is desirable that the number of silicon molecular layers be, for example, 7 or less, which is desirable because the energy band of the superlattice is generally common or relatively uniform Hypothesized that the benefits of. However, depending on the embodiment, eight or more layers may be used. The 4/1 repeat structure for Si / O, illustrated in FIGS. 3 and 4, was modeled to show improved electron and hole mobility in the X direction. For example, the calculated effective conductive mass for electrons is 0.26 (isotropic in bulk silicon), and for a 4/1 SiO superlattice in the X direction, the effective mass of electrons is 0.12, so the ratio is 0.46. . Similarly, the calculation for holes yields a value of 0.36 for bulk silicon and a value of 0.16 for the 4/1 Si / O superlattice. As a result, the ratio is 0.44.

  Such a direction selectivity feature is desirable for certain semiconductor devices, but other devices are due to the more uniform increase in mobility in any direction parallel to the group of layers. It is thought that it will enjoy the benefits. It may be advantageous to increase the mobility of both electrons and holes, or it may be advantageous to increase the mobility of only one of these types of charge carriers. This will be apparent to those skilled in the art.

  The small conductive effective mass for the 4/1 Si / O embodiment according to the superlattice 25 is less than 2/3 of the conductive effective mass according to the prior art. This is true for both electrons and holes. Of course, the superlattice 25 may further comprise at least one conductive dopant contained therein. This will be apparent to those skilled in the art. For example, if the superlattice 25 provides part of the channel, it may be particularly appropriate to dope part of the superlattice 25. In other embodiments, it may be preferable to have one or more groups of the plurality of layers 45 of the superlattice 25 substantially undoped.

  Still referring to FIG. 4, another embodiment of a superlattice 25 'having various properties according to embodiments of the present invention is described. In this embodiment, a repeating pattern of 3/1/5/1 is shown. More specifically, the bottommost basic semiconductor portion 46a 'has three molecular layers, and the next bottommost basic semiconductor portion 46b' has five molecular layers. This pattern is repeated throughout the superlattice 25 '. Each of the energy band correction layers 50 'may include a single molecular layer. For such a superlattice 25 'with Si / O, the improvement in charge carrier mobility is independent of the in-plane orientation of the layer. The other elements in FIG. 4 without specific mention are the same as those discussed above with reference to FIG. 2 and need not be discussed further here.

  In some device embodiments, all of the basic semiconductor portions 46a-46n of the superlattice 25 may be the same number of molecular layers. In another device embodiment, at least some of the basic semiconductor portions 46a-46n may have a different number of molecular layer thicknesses. In another device embodiment, all of the basic semiconductor portions 46a-46n of the superlattice 25 may have different numbers of molecular layer thicknesses.

  In FIGS. 5A-5C, band structures calculated using density functional theory (DFT) are given. It is well known to those skilled in the art that DFT estimates the absolute value of the band gap small. All bands above the gap will therefore be shifted by an appropriate “scissors correction”. However, the shape of the band is known to be quite reliable. The energy on the vertical axis must be interpreted taking this viewpoint into account.

  FIG. 5A shows the band structure of the bulk silicon calculated for the γ point (G) (represented by a continuous line) and the band structure of the 4/1 Si / O superlattice 25 illustrated in FIG. 1 (dashed line). Is represented). The direction shown in the figure means a unit cell having a 4/1 Si / O structure, and does not represent a unit cell normally used for Si. Nonetheless, the (001) direction in the figure corresponds to the (001) direction of the unit cell conventionally used for Si, and thus indicates the position of the expected minimum value of the conduction band of Si. The (100) and (010) directions in the figure correspond to the (110) and (110) directions of unit cells conventionally used for Si. It will be apparent to those skilled in the art that the silicon bands shown in the figure are folded to represent bands in the appropriate reciprocal lattice direction for the 4/1 Si / O structure.

  Unlike bulk silicon (Si), the minimum value of the conduction band of the 4/1 Si / O structure is located at the γ point, while the maximum value of the valence band is what we call the Z point. It can be seen that it is located at the end of the Brillouin zone in the (001) direction. It can also be seen that the curvature of the conduction band minimum of the 4/1 Si / O structure is larger than the curvature of the Si conduction band minimum because the band was split by perturbation introduced by the added oxygen layer. right.

  FIG. 5B shows the bulk silicon band structure calculated for the Z point (represented by a continuous line) and the 4/1 Si / O superlattice 25 band structure (represented by a broken line). This figure shows that the curvature of the valence band in the (100) direction is improved.

  5C shows the bulk silicon band structure calculated for the γ and Z points (represented by continuous lines) and the 5/1/3/1 Si / O band of the superlattice 25 ′ of FIG. Represents the structure (represented by a dashed line). Due to the symmetry of the 5/1/3/1 Si / O structure, the band structure calculated for the (100) direction and the band structure calculated for the (010) direction are equivalent. Therefore, it is expected that the conductive effective mass and mobility are isotropic in a plane parallel to the layer, that is, perpendicular to the (001) stacking direction. Also note that in the 5/1/3/1 Si / O structure example, both the conduction band minimum and valence band maximum are located at or near the Z point.

  Even though an increase in curvature indicates a decrease in effective mass, an appropriate comparison and distinction may be made through a conductive inverse effective mass tensor. Thereby, Applicants have further hypothesized that the 5/1/3/1 superlattice 25 'is substantially a direct transition bandgap. As will be apparent to those skilled in the art, an appropriate matrix element for optical transitions is another indicator that distinguishes the behavior of direct and indirect transition band gaps.

  With further reference now to FIGS. 6A-6D, a method of fabricating MOSFET 20 is described. The method begins by providing a silicon substrate 21. By way of example, the substrate may be a <100> oriented, lightly doped p-type or n-type single crystal silicon 8-inch wafer, although other suitable substrates may be used. According to the present invention, the groove 60 is formed in the substrate and the injection 29 into the main part is performed in the groove 60. Of course, it will be appreciated that in other embodiments, an injection into the main portion may be performed before the groove 60 is formed.

  Subsequently, a material layer of the superlattice 25 is formed in the groove 60. More specifically, as described above, the material of the superlattice 25 is deposited in the trench 60 using an atomic layer deposition method, and an epitaxially grown silicon cap layer 52 is formed over the channel layer 24 of the MOSFET 20. And the surface is planarized.

  Note that in some embodiments, the material of the superlattice 25 may be selectively deposited in the desired region, rather than being deposited over the entire substrate 21. This will be apparent to those skilled in the art. That is, in some embodiments, the superlattice may be formed on the upper surface of the substrate 21 without the groove 60, and the source / drain regions 22, 26 and 23, 27 are epitaxially grown so as to be laterally adjacent to the superlattice. May be formed. Moreover, flattening is not necessary for any embodiment.

  Epitaxially grown silicon cap layer 52 may have a thickness suitable to prevent channel consumption during gate oxide growth or other subsequent oxidation processes. According to the well-known relationship that growing a given oxide consumes about 45% of the underlying silicon, the silicon cap layer can be sized as known to those skilled in the art.

Once the formation of the superlattice 25 is completed, a gate dielectric layer 37 and a gate electrode layer 36 are formed. More particularly, dielectric material is deposited and polycrystalline deposition, patterning, and etching are performed to provide the gate stack illustrated in FIG. 6B. Polycrystalline silicon deposition means low pressure chemical vapor deposition (LPCVD) of silicon on oxide (because of low pressure, a polycrystalline silicon material is formed). The process includes making the polycrystalline silicon conductive by doping with P ⁺ or As ⁻ . The layer may be about 250 nm thick, for example.

  In addition, the patterning step may include a step of performing photoresist coating, baking, exposure (that is, a photolithography step), and resist development. In most cases, the pattern is transferred to another layer (oxide or nitride) that serves as a mask during the etching process. The etching process is typically a plasma etch (anisotropic dry etch) that has material selectivity (eg, silicon is etched 10 times that of the oxide) and transfers the lithographic pattern to the material of interest.

  In the illustrated embodiment, etching of the superlattice 25 is not required, but as described above, in those embodiments where a superlattice blocking dopant is formed on the upper surface of the substrate 21, the material of the superlattice 25 May be etched using known semiconductor processing methods. However, it should be noted that even if a non-semiconductor such as oxygen is present in superlattice 25, the superlattice can still be easily etched by an etchant prepared for oxygen rather than for silicon. Of course, the appropriate etch for performing a given implant will vary based on the structure and materials used for the superlattice 25 and the substrate 21. This will be apparent to those skilled in the art.

  In FIG. 6C, lightly doped source / drain extension regions 22, 23 ("LDD") are formed. These regions are formed using n-type or p-type LDD implantation, annealing, and cleaning. The annealing process may be performed before and after LDD injection. However, depending on the specific process, the annealing step may be omitted. The cleaning process is a chemical etching that removes metals and organic substances before the oxide film is deposited.

FIG. 6D illustrates the formation of sidewall spacers 40, 41 and the implantation of source / drain regions 26, 27. A SiO ₂ layer may be deposited and etched for this purpose. Appropriate n-type or p-type ion implantation is used to form source / drain regions 26, 27 depending on a given implantation. The structure is subsequently annealed and cleaned. Subsequently, silicide layers 30, 31, and 34 may be formed by forming self-aligned silicide. By forming the source / drain contacts 32 and 33, the final semiconductor element 20 shown in FIG. 1 is provided. The formation of silicide is also known as salicidation. The salicide process includes metal (eg, Ti) deposition, nitrogen annealing, metal etching, and second annealing.

  The foregoing is, of course, only an example of processes and devices that can utilize the present invention. Those skilled in the art will appreciate the application and use of the present invention in many other processes and devices. In other processes and devices, the structure of the present invention may be formed on a portion of the wafer or on almost the entire area of the wafer. In addition, in some embodiments, it is not necessary to use an atomic layer deposition apparatus to form the superlattice 25. For example, the molecular layer can also be formed by using a CVD apparatus under process conditions compatible with the molecular layer control. This will be apparent to those skilled in the art. Further details regarding the fabrication of semiconductor elements according to the present invention can be found, for example, in US Pat.

  Many modifications and other embodiments of the invention may occur to those skilled in the art having the benefit of the teachings set forth in the foregoing description and related figures. Therefore, it should be noted that the invention should not be limited to the specific embodiments disclosed, and that modifications and variations are included within the scope of the claims. .

1 is a schematic cross-sectional view of a semiconductor device having a superlattice channel for blocking dopants according to the present invention. FIG. 2 is a schematic cross-sectional view in which the superlattice shown in FIG. 1 is considerably enlarged. FIG. 2 is a schematic perspective view of a part of the superlattice illustrated in FIG. 1 on an atomic scale. FIG. 3 is a schematic cross-sectional view, which is considerably enlarged, of another embodiment of a superlattice that can be used in the device of FIG. A graph of the band structure calculated at the γ point (G) for bulk silicon as a prior art and the band calculated at the γ point (G) for the 4/1 Si / O superlattice shown in Figure 1-3. It is a graph of a structure. FIG. 4 is a graph of a band structure calculated at the Z point for bulk silicon as a conventional technique, and a graph of a band structure calculated at the Z point for the 4/1 Si / O superlattice illustrated in FIG. 1-3. Band structure graph calculated at both γ point (G) and Z point for bulk silicon as a prior art, and γ point (5/1/3/1 Si / O superlattice shown in FIG. It is a graph of the band structure calculated at both G) and Z points. A-D is a series of schematic cross-sectional views illustrating a method of fabricating the semiconductor device of FIG.

Claims (34)

A semiconductor device having at least one metal-oxide field effect transistor (MOSFET),
The MOSFET is:
Main part;
A channel layer adjacent to the main portion; and a superlattice blocking dopants present between the main portion and the channel layer;
Have
The superlattice for blocking the dopant has a plurality of stacked groups of a plurality of layers,
Each group of superlattice layers blocking the dopant comprises a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and at least one non-layer constrained within the crystal lattice of an adjacent basic semiconductor portion. Having a semiconductor molecular layer,
Semiconductor element.   2. The semiconductor device according to claim 1, wherein the main part has at least one doped region therein. The semiconductor device of claim 1, wherein the main portion has a dopant concentration greater than about 1 × 10 ¹⁸ cm ⁻³ .   2. The semiconductor device according to claim 1, wherein the channel layer is not substantially doped. The semiconductor device of claim 1, wherein the channel layer has a dopant concentration of less than about 1 × 10 ¹⁵ cm ⁻³ .   2. The semiconductor device of claim 1, wherein at least one group of superlattice layers blocking said dopant is substantially undoped.   2. The semiconductor device according to claim 1, wherein the basic semiconductor portion includes silicon.   8. The semiconductor element according to claim 7, wherein the at least one non-semiconductor molecular layer contains oxygen.   2. The semiconductor element according to claim 1, wherein the at least one non-semiconductor molecular layer has a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.   2. The semiconductor device according to claim 1, further comprising a gate existing on the channel layer.   11. The semiconductor device according to claim 10, further comprising source and drain regions adjacent to a lateral side of the channel layer.   11. The semiconductor device according to claim 10, wherein the gate has a gate insulating layer adjacent to the semiconductor channel layer and a gate electrode layer adjacent to the gate insulating layer.   2. The semiconductor device according to claim 1, wherein the at least one non-semiconductor molecular layer has a thickness of a monomolecular layer.   2. The semiconductor device according to claim 1, wherein each basic semiconductor portion has a thickness of less than eight molecular layers.   2. The semiconductor device according to claim 1, wherein all of the basic semiconductor portions have the same number of molecular layers.   2. The semiconductor element according to claim 1, wherein a part of the basic semiconductor portion has a thickness with a different number of molecular layers. 2. The semiconductor device according to claim 1, wherein opposing basic semiconductor molecular layers in an adjacent group composed of a plurality of layers of the superlattice are chemically bonded together.
A method of manufacturing a semiconductor device comprising a step of forming at least one metal-oxide field effect transistor (MOSFET),
The MOSFET is:
Forming a main part;
Forming a superlattice to block dopants adjacent to the main part, comprising:
The superlattice for blocking the dopant has a plurality of stacked groups of a plurality of layers,
Each group of superlattice layers blocking the dopant comprises a plurality of stacked basic semiconductor molecular layers defining a basic semiconductor portion and at least one non-layer constrained within the crystal lattice of an adjacent basic semiconductor portion. Having a semiconductor molecular layer; and forming a channel layer facing the main portion adjacent to a superlattice blocking the dopant;
Formed by,
Method.   19. The method of claim 18, wherein the main portion has at least one doped region therein. The method of claim 18, wherein the main portion has a dopant concentration greater than about 1 × 10 ¹⁸ cm ⁻³ .   The method of claim 18, wherein the channel layer is substantially undoped. The method of claim 18, wherein the channel layer has a dopant concentration of less than about 1 × 10 ¹⁵ cm ⁻³ .   19. The method of claim 18, wherein at least one group of superlattice layers blocking said dopant is substantially undoped.   The method of claim 18, wherein the basic semiconductor portion comprises silicon.   25. The method of claim 24, wherein the at least one non-semiconductor molecular layer comprises oxygen.   19. The method of claim 18, wherein the at least one non-semiconductor molecular layer comprises a non-semiconductor selected from the group consisting essentially of oxygen, nitrogen, fluorine, and carbon-oxygen.   The method of claim 18, further comprising a gate overlying the channel layer.   28. The method of claim 27, further comprising source and drain regions adjacent to a lateral side of the channel layer.   28. The method of claim 27, wherein forming the gate comprises forming a gate insulating layer adjacent to the semiconductor channel layer and a gate electrode layer adjacent to the gate insulating layer.   19. The method of claim 18, wherein the at least one non-semiconductor molecular layer is a monolayer thickness.   19. The method of claim 18, wherein each basic semiconductor portion is less than 8 molecular layers thick.   19. The method of claim 18, wherein all of the basic semiconductor portions are the same number of molecular layers.   19. The method of claim 18, wherein a portion of the basic semiconductor portion is a different number of molecular layers.   19. The method of claim 18, wherein opposing basic semiconductor molecular layers in adjacent groups of layers of the superlattice are chemically bonded together.

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