CN117616580A

CN117616580A - Semiconductor devices including superlattices that provide metal work function tuning and related methods

Info

Publication number: CN117616580A
Application number: CN202280048282.5A
Authority: CN
Inventors: R·J·米尔斯; 武内英树
Original assignee: Atomera Inc
Current assignee: Atomera Inc
Priority date: 2021-05-18
Filing date: 2022-05-18
Publication date: 2024-02-27

Abstract

A semiconductor fully-surrounding Gate (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a fully-surrounding gate arrangement, and a doped diffusion liner adjacent at least one of the source and drain regions and including a first superlattice. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Description

Semiconductor devices including superlattices that provide metal work function tuning and related methods

Technical Field

The present disclosure relates generally to semiconductor devices, and more particularly, to semiconductor devices including nanostructures and related methods.

Background

Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by increasing the mobility of charge carriers. For example, U.S. patent application No.2003/0057416 to Currie et al discloses a strained material layer having silicon, silicon-germanium, and relaxed silicon, and further comprising impurity-free regions that would otherwise cause performance degradation. The biaxial strain created in the upper silicon layer changes the carrier mobilities enabling higher speed and/or lower power devices. Published U.S. patent application No.2003/0034529 to Fitzgerald et al discloses a CMOS inverter also based on similar strained silicon technology.

U.S. Pat. No.6,472,685b2 to Takagi discloses a semiconductor device comprising silicon and carbon layers sandwiched between silicon layers such that the conduction and valence bands of the second silicon layer receive tensile strain. Electrons that have a smaller effective mass and that have been induced by the electric field applied to the gate electrode are confined in the second silicon layer, and therefore, the n-channel MOSFET is considered to have higher mobility.

U.S. Pat. No.4,937,204 to Ishibashi et al discloses a superlattice in which less than 8 monolayers are alternately epitaxially grown and a plurality of layers including fractional or binary compound semiconductor layers. The direction of the main current is perpendicular to the layers of the superlattice.

U.S. Pat. No.5,357,119 to Wang et al discloses a Si-Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Pat. No.5,683,934 to Candelaria discloses an enhanced mobility MOSFET comprising a channel layer comprising an alloy of silicon and a second material that is alternatively present in the silicon lattice at a percentage such that the channel layer is under tensile stress.

U.S. Pat. No.5,216,262 to Tsu discloses a quantum well structure comprising two barrier regions and an epitaxially grown thin semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating SiO2/Si layers typically ranging in thickness from 2 to 6 monolayers. A much thicker silicon portion is sandwiched between the barriers.

A Semiconductor Atomic Superlattice (SAS) of silicon and oxygen is disclosed in a paper titled "Phenomena in silicon nanostructure devices" by Applied Physics and Materials Science & Processing, pp.391-402 published online at 9/6/2000, also Tsu. Si/O superlattices are disclosed as being useful in silicon quantum and light emitting devices. In particular, green electroluminescent diode structures were constructed and tested. The current in the diode structure is vertical, i.e., perpendicular to the layers of the SAS. The disclosed SAS may include semiconductor layers separated by adsorbed species such as oxygen atoms and CO molecules. Silicon growth beyond the adsorbed monolayer of oxygen is described as epitaxial growth with a fairly low defect density. A SAS structure includes a 1.1nm thick silicon portion that is approximately 8 atomic layers of silicon, while another structure has twice that thickness of silicon. The Light Emitting SAS structure of Tsu is further discussed in Luo et al entitled "Chemical Design of Direct-Gap Light-emission Silicon" published in Physical Review Letters, vol.89, no.7 (8/12/2002).

U.S. patent No.7,105,895 to Wang et al discloses a barrier building block of thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen to reduce the current flowing vertically through the lattice by more than four orders of magnitude. The insulating layer/barrier layer allows low defect epitaxial silicon to be deposited next to the insulating layer.

Published united kingdom patent application 2,347,520 to Mears et al discloses that the principles of non-periodic photonic bandgap (APBG) structures can be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, e.g., the location of band minima, effective mass, etc., can be adjusted to produce new aperiodic materials with desirable band-structure characteristics. Other parameters are disclosed, such as electrical conductivity, thermal conductivity and permittivity or permeability, which may also be designed into the material.

Furthermore, U.S. patent No.6,376,337 to Wang et al discloses a method for producing an insulating or barrier layer of a semiconductor device, which method comprises depositing a silicon and at least one additional element on a silicon substrate, whereby the deposited layer is substantially defect-free, such that substantially defect-free epitaxial silicon can be deposited on the deposited layer. Alternatively, a monolayer of one or more elements, preferably comprising oxygen, is adsorbed onto the silicon substrate. A plurality of insulating layers sandwiched between epitaxial silicon form a barrier composite.

Despite the existence of such approaches, further enhancements are desirable for achieving improved performance in semiconductor devices using advanced semiconductor materials and processing techniques.

Disclosure of Invention

A semiconductor fully-surrounding Gate (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, a gate surrounding the plurality of semiconductor nanostructures in a fully-surrounding gate arrangement (arrangement), and a doped diffusion liner adjacent at least one of the source and drain regions and including a first superlattice. The first superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In an example implementation, the doped diffusion liner may include respective portions adjacent to each of the source and drain regions. In some embodiments, the semiconductor device may further include a second superlattice within at least one of the nanostructures. The second superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

According to yet another example implementation, the semiconductor device may further include a third superlattice embedded in the semiconductor substrate extending between the source region and the drain region. The third superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In another example embodiment, the semiconductor device may further include a fourth superlattice on the semiconductor substrate below the source region. The fourth superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In another implementation, the semiconductor device may further include a fifth superlattice on the semiconductor substrate below the drain region. The fifth superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

For example, the gate may include a metal. Also for example, the base semiconductor portion may comprise silicon and the at least one non-semiconductor monolayer may comprise oxygen.

A method of fabricating a semiconductor fully-around Gate (GAA) device may include forming a source region and a drain region on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source region and the drain region, forming a gate surrounding the plurality of semiconductor nanostructures in a fully-around gate arrangement, and forming a doped diffusion liner adjacent at least one of the source region and the drain region and including a first superlattice. The first superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In example embodiments, the doped diffusion liner may include respective portions adjacent to each of the source and drain regions. In a certain embodiment, the method may further include forming a second superlattice within at least one of the nanostructures, the second superlattice including a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In yet another example embodiment, the method may include forming a third superlattice embedded in the semiconductor substrate extending between the source region and the drain region. The third superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In another example embodiment, the method may further include forming a fourth superlattice on the semiconductor substrate below the source region. The fourth superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

In some embodiments, the method may further include forming a fifth superlattice on the semiconductor substrate below the drain region. The fifth superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

Drawings

Fig. 1 is a greatly enlarged schematic cross-sectional view of a superlattice for use in a semiconductor device in accordance with an example embodiment.

Fig. 2 is a perspective schematic atomic diagram of a portion of the superlattice shown in fig. 1.

Fig. 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice in accordance with an example embodiment.

Fig. 4A is a calculated band structure diagram from gamma point (G) for both bulk silicon in the prior art and for a 4/1Si/O superlattice as shown in fig. 1-2.

Fig. 4B is a calculated band structure diagram from the Z point for both bulk silicon in the prior art and for a 4/1Si/O superlattice as shown in fig. 1-2.

Fig. 4C is a calculated energy band structure diagram from both the gamma and Z points for both bulk silicon in the prior art and for a 5/1/3/1Si/O superlattice as shown in fig. 3.

Fig. 5 is a schematic block diagram of a fully-round Gate (GAA) semiconductor device in accordance with an example embodiment.

Fig. 6 is a cross-sectional view of the GAA device of fig. 5 taken along line B-B.

Fig. 7 is a cross-sectional view of the GAA device of fig. 5 taken along line A-A.

Fig. 8 is a graph of atomic concentration versus voltage illustrating an example threshold voltage reduction of a metal gate semiconductor device, such as the GAA device of fig. 5, in accordance with an example embodiment.

Fig. 9 is a series of cross-sectional views illustrating a method for fabricating the GAA device of fig. 5 having a superlattice in the GAA nanostructure.

Fig. 10 is a series of cross-sectional views illustrating a method for fabricating an alternative embodiment of the GAA device of fig. 5 without a superlattice in the GAA nanostructure.

Detailed Description

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown. Embodiments may, however, be embodied in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

The present disclosure relates generally to fully-surrounding Gate (GAA) semiconductor devices having one or more enhanced semiconductor superlattices therein to provide performance enhancing characteristics. The enhanced semiconductor superlattice may also be referred to in this disclosure as a "MST" layer or "MST technology.

More particularly, MST technology relates to advanced semiconductor materials such as the superlattice 25 as further described below. Applicants theorize, but do not wish to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers, and that this thereby results in higher charge carrier mobility. Effective mass is variously defined in the literature. As a measure of improvement in effective mass, applicants use the "conductivity reciprocal effective mass tensor" of electrons and holes, respectively "And

for electrons, it is defined as:

and for holes, is defined as:

where f is the Fermi-Dirac distribution, E _F Is the fermi level, T is the temperature, E (k, n) is the energy of the electrons in states corresponding to the wave vector k and the n-th energy band, the indices i and j refer to cartesian coordinates x, y and z, integration is performed in the brillouin zone (b.z.), and summation is performed for electrons and holes in energy bands above and below the fermi level, respectively.

Applicant's definition of the conductivity reciprocal effective mass tensor is such that the greater the tensor component of the conductivity of the material for a greater value of the corresponding component of the conductivity reciprocal effective mass tensor. Again, applicants theorize, but without wishing to be bound thereto, that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically with respect to the preferred directions of charge carrier transport. The reciprocal of the appropriate tensor element is called the conductivity effective mass. In other words, to characterize the semiconductor material structure, the conductivity effective mass of electrons/holes, as described above and calculated in the direction of intended carrier transport, is used to distinguish between improved materials.

Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, applicants have identified materials or structures having energy band structures for which the appropriate conductivity effective mass for electrons and/or holes is substantially lower than the corresponding value for silicon. In addition to the enhanced mobility characteristics of these structures, they may be formed or used in a manner such that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are beneficial for use in a variety of different types of devices, as described further below.

Referring now to fig. 1 and 2, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in stacked relation as best understood by particular reference to the schematic cross-sectional view of fig. 1.

Each group of layers 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor monolayers 46 defining a corresponding base semiconductor portion 46a-46n and an energy band-modifying layer 50 thereon. For clarity of illustration, the energy band-modifying layer 50 is represented by stippling in FIG. 1.

The energy band-modifying layer 50 illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. As shown in fig. 2, "confined within the lattice of adjacent base semiconductor portions" means that at least some semiconductor atoms from opposing base semiconductor portions 46a-46n are chemically bonded together with a non-semiconductor monolayer 50 therebetween. Generally, this configuration is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques such that not all (i.e., less than full or 100% coverage) available semiconductor bonding sites are filled with bonds to non-semiconductor atoms, as described further below. Thus, when additional monolayers 46 of semiconductor material are deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining empty bonding sites of the semiconductor atoms under the non-semiconductor monolayer.

In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that references herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, as will be appreciated by those skilled in the art, a single monolayer of a material such as silicon may not necessarily exhibit the same properties as would be exhibited if formed in bulk or relatively thick layers.

Applicants theorize, but without wishing to be bound thereto, that the energy band-modifying layers 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a lower appropriate conductivity effective mass for charge carriers in the parallel layer direction than would otherwise be present. From another perspective, the parallel direction is orthogonal to the stacking direction. The energy band modifying layers 50 may also provide the superlattice 25 with a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Furthermore, such superlattice structures may also advantageously act as barriers to dopant and/or material diffusion between layers vertically above and below the superlattice 25. Thus, those skilled in the art will appreciate that these properties may advantageously allow the superlattice 25 to provide an interface for the high-K dielectric that not only reduces diffusion of the high-K material into the channel region, but may also advantageously reduce unwanted scattering effects and improve device mobility.

It is also theoretically demonstrated that semiconductor devices including the superlattice 25 may enjoy higher charge carrier mobilities based on lower conductivity effective masses than would otherwise be present. In some embodiments, and as a result of the energy band engineering achieved by the present invention, the superlattice 25 may also have a substantially direct energy bandgap that may be particularly advantageous, for example, for photovoltaic devices.

The superlattice 25 also illustratively includes a cap layer 52 on an upper layer group 45 n. The cap layer 52 may include a plurality of base semiconductor monolayers 46. The capping layer 52 may have 2 to 100 base semiconductor monolayers, more preferably 10 to 50 monolayers.

Each base semiconductor portion 46a-46n may comprise a base semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, those skilled in the art will appreciate that the term group IV semiconductor also includes group IV-IV semiconductors. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

For example, each energy band-modifying layer 50 may include a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. The non-semiconductor is also desirably thermally stable through deposition of the next layer, thereby facilitating fabrication. In other embodiments, those skilled in the art will appreciate that the non-semiconductor may be other inorganic or organic elements or compounds compatible with a given semiconductor process. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

It should be noted that the term monolayer is meant to include a single atomic layer as well as a single molecular layer. It should also be noted that the energy band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than complete or 100% coverage). For example, with particular reference to the atomic diagram of fig. 2, a 4/1 repeating structure is shown for silicon as the base semiconductor material and oxygen as the energy band modifying material. In the example shown in the illustration, only half of the possible sites for oxygen are occupied.

In other embodiments and/or where different materials are used, those skilled in the art will appreciate that this 1/2 occupation is not necessarily the case. In fact, even though it can be seen in this schematic diagram, the individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane, as will be appreciated by those skilled in the art of atomic deposition. For example, the preferred occupation range is about 1/8 to 1/2 of the possible oxygen sites are filled, although other numbers may be used in some embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and therefore manufacturers will be able to readily use these materials described herein. Atomic deposition or monolayer deposition is also now widely used. Thus, those skilled in the art will appreciate that semiconductor devices incorporating a superlattice 25 in accordance with the invention may be readily adopted and implemented.

Theoretically, but applicants do not wish to be bound by this, for a superlattice, such as a Si/O superlattice, for example, the number of silicon monolayers should desirably be seven or less so as to make the energy band of the superlattice everywhere common or relatively uniform to achieve the desired advantages. For Si/O, the 4/1 repeating structures shown in FIGS. 1 and 2 have been modeled to indicate enhanced mobility of electrons and holes in the X direction. For example, the calculated conductivity effective mass of electrons (isotropy of bulk silicon) is 0.26, and for a 4/1SiO superlattice in the X direction, it is 0.12, resulting in a ratio of 0.46. Similarly, the calculation for holes yields a value of 0.36 for bulk silicon and 0.16 for the 4/1Si/O superlattice, resulting in a ratio of 0.44.

While such directionally preferential features may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. Those skilled in the art will appreciate that it may also be beneficial to have increased mobility for electrons and holes or just one of these types of charge carriers.

The lower conductivity effective mass of the 4/1Si/O embodiment of the superlattice 25 may be less than 2/3 of the conductivity effective mass that would otherwise occur, and this applies to both electrons and holes. Of course, those skilled in the art will appreciate that the superlattice 25 may also include at least one type of conductivity dopant therein.

Indeed, with additional reference now to fig. 3, another embodiment of a superlattice 25' in accordance with the invention having different properties will now be described. In this embodiment, a 3/1/5/1 repeating pattern is shown. More specifically, the lowest base semiconductor portion 46a 'has 3 monolayers, while the next lowest base semiconductor portion 46b' has 5 monolayers. This pattern repeats throughout the superlattice 25'. The energy band-modifying layers 50' may each comprise a single monolayer. For such a superlattice 25' including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements not specifically mentioned in fig. 3 are similar to those discussed above with reference to fig. 1 and need not be discussed further herein.

In some device embodiments, all of the base semiconductor portions of the superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

In fig. 4A-4C, the band structure calculated using Density Functional Theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Thus, all energy bands above the band gap can be shifted by appropriate "scissors correction". However, the shape of the known energy bands is much more reliable. The vertical energy axis should be interpreted from this perspective.

Fig. 4A shows the calculated band structure from gamma point (G) for both bulk silicon (represented by solid lines) and for the 4/1Si/O superlattice 25 shown in fig. 1 (represented by dashed lines). The direction relates to the unit cell of the 4/1Si/O structure, and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, thus showing the expected position of the conduction band minimum of Si. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of a conventional Si unit cell. Those skilled in the art will appreciate that the energy bands of Si in the figures are folded to represent them in the appropriate reciprocal lattice direction of the 4/1Si/O structure.

It can be seen that the conduction band minimum of the 4/1Si/O structure is located at the gamma point compared to the bulk silicon (Si), while the valence band minimum occurs at the edge of the brillouin zone in the (001) direction, which we call the Z point. It can also be noted that the curvature of the conduction band minimum of the 4/1Si/O structure is greater than that of Si due to the band splitting caused by the perturbation introduced by the additional oxygen layer.

Fig. 4B shows the calculated band structure from the Z point for both bulk silicon (solid line) and for the 4/1Si/O superlattice 25 (dashed line). The figure illustrates the enhanced curvature of the valence band in the (100) direction.

Fig. 4C shows the calculated band structure from both the gamma and Z points for both bulk silicon (solid line) and for the 5/1/3/1Si/O structure (dashed line) of the superlattice 25' of fig. 3. The calculated band structures in the (100) and (010) directions are equivalent due to the symmetry of the 5/1/3/1Si/O structure. Thus, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1Si/O example, both the conduction band minimum and the valence band maximum are at or near the Z point.

Although the increased curvature is indicative of a reduced effective mass, appropriate comparison and discrimination can be made by conductivity reciprocal effective mass tensor calculation. This results in applicants further theorized that the 5/1/3/1 superlattice 25' should be substantially a direct bandgap. As will be appreciated by those skilled in the art, a suitable matrix element for optical transitions is another indicator of the distinction between direct bandgap behavior and indirect bandgap behavior.

Referring now to fig. 5-8, for example, the superlattice structure described above may be advantageously used to provide enhanced metal work function tuning in semiconductor devices, such as in a fully-surrounding Gate (GAA) device 100. More specifically, in the illustrated GAA device 100, the nanostructures (here nanoplatelets 101) are surrounded on all sides by a gate 102 comprising a high-K dielectric 103 and a metal electrode 104. In other embodiments, the nanostructures may take the form of nanoparticles, nanowires, nanofibers, nanotubes, nanobelts (nanobelts), nanodiscs, nanoplatelets, or nanohorns, and such nanostructures typically have a thickness or diameter, for example, in the range of 0.5nm to 100nm, although other dimensions may be used in different embodiments. The channel of GAA device 100 extends through nanoplatelets 101 between source region 105 and drain region 106.

In general, GAA devices not only guarantee more efficient use of device space to achieve higher device densities, but can also help reduce problems associated with channel width variations, such as variability and mobility loss. However, in conventional GAA devices, the threshold voltage (Vt) may need to be controlled by the metal work function of the electrode metal. Typically, this involves adjusting the thickness of the metal, with thicker metals providing higher Vt values and thinner metals providing lower Vt values. However, GAA structures may be spatially limited such that insufficient space is available for low Vt (high thickness) metals, as this would limit the number of nanoplates 101 that may otherwise be placed in the gate stack. Since the drive current is proportional to the number of nanoplatelets 101 present, the use of low Vt (high thickness) metals may instead result in an undesirable reduction in the drive current of the low Vt device. By way of background, U.S. patent publication No. 2021/012688 to Zhang et al, which is incorporated herein by reference in its entirety, discloses a method of implementing a GAA device that shifts Vt based on the thickness of a portion of a dielectric layer.

In this example, one or more intervening non-semiconductor (e.g., oxygen) monolayers 50 or full MST films 125 can be incorporated within the nanoplatelets of the GAA device to advantageously provide the desired work function tuning (see fig. 6 and 7). As shown in graph 80 of fig. 8, the simulation results demonstrate that incorporating one or more non-semiconductor monolayers within the nanoplatelets advantageously reduces Vt as compared to pure silicon nanoplatelets, such that relatively thin metal thicknesses can be used without resulting in high Vt with relatively low metal thicknesses. In the example shown in the illustrations, the respective graphs 81, 82 show the voltage per atomic area simulated using a straight silicon consisting of a MST film with a TiN/HfO2 gate having a thickness of 7 nm. However, it should be appreciated that other gate materials and configurations may be used in different embodiments.

Thus, for integrated circuits requiring both high-Vt and low-Vt devices, similar structures can be used for both, with only the inclusion of an interposed oxygen (or MST) layer within the nanoplatelets of the low-Vt devices. The process for fabricating the high-Vt GAA device and the low-Vt GAA device with and without the interposed oxygen/MST layer in the nanoplatelets 100 will be discussed below with reference to fig. 9 and 10, respectively. It should be noted that one or more intervening oxygen (or MST) layers may be at different locations within the nanoplatelets, such as at the top and/or bottom interfaces, as well as in the middle of the nanoplatelets. Further details regarding the incorporation of an interposed oxygen/MST layer in a nanostructure are provided in U.S. patent publication No.2022/0005926 to Weeks et al, assigned to the present applicant and incorporated herein by reference in its entirety.

As shown in fig. 6, interposed oxygen (or MST) layers 225a and/or 225b may additionally (or instead) be incorporated on the surface of the substrate 110 (here, a silicon substrate) under the source 105 and/or drain 106, respectively, to advantageously provide a punch-through barrier (PTS) layer to help avoid source/drain dopant punch-through. Further, the interposed oxygen (or MST) layer 325 may additionally (or alternatively) be located in the substrate 110 as a PTS layer extending between the source 105 and drain 106, either alone or in combination with the layers 225a and/or 225 b. In the illustrated example, shallow Trench Isolation (STI) regions 111 (e.g., siO ₂ ) For use inDifferent devices are electrically isolated on the substrate 110.

Also in the illustrated example, respective doped diffusion liners 425a, 425b (which may be interposed oxygen or MST layers) are positioned between the source 105 and the gate 102 and/or between the drain 106 and the gate, respectively, as shown, to advantageously help prevent diffusion of dopants from the source/drain regions to the nanoplatelets 101. Further information regarding the use of an MST layer as a PTS layer and for doping diffusion barriers is set forth in U.S. patent nos. 9,941,359 and 9,899,479, both assigned to the present applicant and incorporated herein by reference in their entirety. The MST film for each layer 125, 225a, 225b, 325, 425a, and 425b may be similar to that described above with reference to fig. 1-4c and, for example, in the above-mentioned U.S. patent publication No. 2022/0005926.

Referring now additionally to the process flow diagrams 500, 500 'of fig. 9 and 10, an example method of preparing a low-Vt GAA device 100 and a high-Vt GAA device 100' with and without a superlattice 125, respectively, in a nanoplatelet 101 is now described. In step (a) of both process flows, a PTS implant 112 or 112 'is formed in the substrate 110 or 110'. The PTS layer 325 or 325' is then formed and the nanoplatelets are epitaxially deposited with epitaxial silicon germanium (SiGe) 113 or 113' in which there is a vertically spaced silicon/oxygen superlattice layer 125 or 125'. In step (b), the regions where the source 105 or 105 'and drain 106 or 106' are to be formed may then be etched away to define the nanoplatelet "fin (fin)", and to provide patterning for forming the STI region 111, as well as dummy gate patterning. A respective MST layer 225a, 225b or 225a ', 225b' may then be formed on the surface of the substrate 110 or 110', and vertical MST doped diffusion liners 425a, 425b or 425a', 425b 'may be formed on the source or drain side of the SiGe 113 or 113', respectively, followed by the growth of source/drain regions 105, 106 or 105', 106'. In the example shown in the illustrations, doped SiC: P epitaxy may be performed to grow source and drain regions 105, 106 or 105', 106'. As will be appreciated by those skilled in the art, this may be done using cluster tools to perform etch + ash + clean operations as well as epitaxial growth.

In step (c) of both process flows 500, 500', the SiGe is removedSacrificial layer 113 or 113'. However, for the high Vt GAA device 100', a high temperature anneal is also performed (e.g., at 800-1000C at N ₂ Or O ₂ Or 5s-120s in UHV) to diffuse oxygen out of MST layer 125 '(i.e., the MST layer is no longer present in nanoplatelets 101'). Further details regarding annealing to out-diffuse oxygen from the MST layer can be found in U.S. patent No.10,109,479, assigned to the present applicant and incorporated herein by reference in its entirety. Here again, the process may also be performed using a cluster tool. Both process flows end with the formation of a high-K metal gate (HKMG) gate 102 or 102' in step (d).

Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and embodiments are intended to be included.

Claims

1. A semiconductor full surrounding Gate (GAA) device, comprising:

a semiconductor substrate;

a source region and a drain region on the semiconductor substrate;

a plurality of semiconductor nanostructures extending between the source and drain regions;

a gate surrounding the plurality of semiconductor nanostructures in a fully surrounding gate arrangement; and

a doped diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

2. The semiconductor device of claim 1, wherein the doped diffusion liner comprises a respective portion adjacent each of the source and drain regions.

3. The semiconductor device of claim 1, further comprising a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

4. The semiconductor device of claim 1, further comprising a third superlattice embedded in the semiconductor substrate extending between the source region and the drain region, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

5. The semiconductor device of claim 1, further comprising a fourth superlattice on the semiconductor substrate below the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

6. The semiconductor device of claim 1, further comprising a fifth superlattice on the semiconductor substrate below the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

7. The semiconductor device of claim 1, wherein the gate comprises a metal.

8. The semiconductor device of claim 1, wherein the base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1, wherein the at least one non-semiconductor monolayer comprises oxygen.

10. A semiconductor full surrounding Gate (GAA) device, comprising:

a semiconductor substrate;

a source region and a drain region on the semiconductor substrate;

a gate surrounding the plurality of semiconductor nanostructures in a fully surrounding gate arrangement;

source and drain doped diffusion liners adjacent respective portions of the source and drain regions and each comprising a first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and

a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

11. The semiconductor device of claim 10, further comprising a third superlattice embedded in the semiconductor substrate extending between the source region and the drain region, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

12. The semiconductor device of claim 10, further comprising a fourth superlattice on the semiconductor substrate below the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

13. The semiconductor device of claim 10, further comprising a fifth superlattice on the semiconductor substrate below the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

14. The semiconductor device of claim 10, wherein the gate comprises a metal.

15. A method of fabricating a semiconductor full surrounding Gate (GAA) device, comprising:

forming a source region and a drain region on a semiconductor substrate;

forming a plurality of semiconductor nanostructures extending between the source and drain regions;

forming a gate surrounding the plurality of semiconductor nanostructures in a fully surrounding gate arrangement; and

a doped diffusion liner is formed adjacent at least one of the source and drain regions and includes a first superlattice including a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

16. The method of claim 15, wherein the doped diffusion liner comprises a respective portion adjacent each of the source and drain regions.

17. The method of claim 15, further comprising forming a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

18. The method of claim 15, further comprising forming a third superlattice embedded in the semiconductor substrate extending between the source region and the drain region, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

19. The method of claim 15, further comprising a fourth superlattice formed on the semiconductor substrate below the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

20. The method of claim 15, further comprising a fifth superlattice formed on the semiconductor substrate below the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.

21. The method of claim 15, wherein the gate comprises a metal.

22. The method of claim 15 wherein the base semiconductor portion comprises silicon.

23. The method of claim 15, wherein the at least one non-semiconductor monolayer comprises oxygen.