JP2009530827A - Spintronic device having constrained spintronic dopant and method of manufacturing the same - Google Patents

Abstract

  The spintronic device has at least one superlattice and at least one electrical contact coupled thereto, the at least one superlattice including a plurality of layers. Each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and spintronics A dopant may be included. The spintronic dopant can be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. In some embodiments, a repetitive structure of the superlattice is not required.

Description

  The present invention relates to the field of electronics, and more specifically to the field of spin-based electronics and methods for manufacturing the same.

  Spin-based electronics, or spintronics, uses both the charge of electrons and the spin of electrons, for example, to realize new devices with higher functionality, higher speed, and / or lower power consumption. It is. A typical spintronic device is a spin valve as shown in FIGS. 1A and 1B. The spin valve 11 provides a low resistance when the spins are aligned (FIG. 1A) and a high resistance when the spins are not aligned (FIG. 1B). The spin valve 11 can be used as a nonvolatile memory element, for example. Other typical spintronic devices include a spin FET 12 as schematically shown in FIG. 2 and a qubit device 13 as shown in FIG.

  For example, Patent Document 1 discloses a diluted magnetic semiconductor (DMS) containing zinc oxide containing a sufficient amount of a transition element or rare earth lanthanide, or both, to change the material from a non-magnetic state to a room temperature ferromagnetic state. is doing. This material may be in the form of a bulk or a thin film. The DMS material is a semiconductor in which a transition metal ion or a rare earth lanthanide substitutes a cation (cation) of a host semiconductor material. More specifically, DMS material 15 is schematically illustrated in FIG. 4B. 4A on the left is a magnetic material 14 and FIG. 4C on the right is a nonmagnetic material 16.

  Patent Document 2 discloses a spintronic switching device having a metalloid region between a first conductive region and a second conductive region. The metalloid region contains a material that is substantially free of available electronic states in the minority spin channel at the intrinsic Fermi level. By changing the voltage of the metalloid region relative to the first conductive region, its Fermi level is shifted relative to the energy band of the electrons in the first conductive region, and the number of available electronic states in the multiple spin channel. Changes. At that time, the multiple spin-polarized current passing through the switching device changes. The metalloid region may include CrAs, and the conductive region may include a p-type doped or n-type doped semiconductor. For example, the p-type doped semiconductor can be Mn-doped GaAs.

Patent Document 3 discloses an application of a spintronic device as a memory and a logic device using a spin valve effect obtained by injecting spin-polarized carriers from ferromagnetism to a semiconductor at room temperature, and a spin-polarized field effect transistor. Are disclosed. The ferromagnetic material is disclosed as any one of Fe, Co, Ni, FeCo, NiFe, GaMnAs, InMnAs, GeMn, and GaMnN, for example, a semimetal having 100% spin polarization such as CrO ₂ It can be. The semiconductor may be a semiconductor selected from Si, GaAs, InAs, and Ge. The spin channel region is disclosed as a silicon-on-insulator (SOI) or compound semiconductor two-dimensional electron gas.

Non-Patent Document 1 by Jonker et al. Discloses a semiconductor heterostructure using carrier spin as a new degree of freedom. This document discloses four essential conditions for implementing semiconductor spintronics technology in a device, and the efficient electrical injection of spin-polarized carriers into a semiconductor is a serious issue that greatly hinders the progress of this field. That you are presenting. This reference further discloses that due to advances in material quality, the Curie temperature of Ga _1-x Mn _x As has been increased to about 150 K, which has the potential to exceed room temperature. A spin-dependent resonant tunneling phenomenon has been identified as one that increases the spin selectivity of tunnel contacts very efficiently. A double-barrier heterojunction (DBH) having a non-magnetic semiconductor quantum well between two insulating barriers and two ferromagnetic semiconductor electrodes is a semi-metal junction when the quantum well and barrier parameters are appropriately adjusted. Can behave.

  Current spin electronics technology is limited by the materials currently in use. For example, it is important to have efficient spin carrier injection, as mentioned by Jonker et al. It is also desirable to have manufacturing and operational compatibility with existing semiconductor processing technologies. Further, it is desirable that the magnetic ordering temperature or the Curie temperature is not a more general 100-200K, but a normal temperature or near normal temperature. One possible approach is a DMS material as disclosed in US Pat.

  As another spintronic device structure, for example, there is a digital ferromagnetic heterostructure (DFH) as disclosed in Non-Patent Document 2. This document mentions that although the solubility limit of Mn in GaAs is quite low, a high Mn concentration is obtained in the zincblende MnAs submonolayer in GaAs forming MnAs / GaAs superlattices. . A schematic diagram of a DFH structure 18 according to the prior art is shown in FIG. The DFH structure 18 has a transition metal (Tm) in the form of Mn in a silicon superlattice. This can have a large spin polarization at the Fermi level, a large magnetoresistive effect, and a higher Curie temperature than in the bulk, but has the problem of low thermal stability.

Unfortunately, many of the materials and structures for spintronics have fairly low concentrations of spintronic dopants such as Mn. Spin electronics dopants tend to fall out of the crystal lattice, especially when the concentration is increased and / or when the device is subjected to a heat treatment step.
US Patent Application Publication No. 2006/0018816 US Patent Application Publication No. 2005/0258416 US Patent Application Publication No. 2004/0178460 Jonker et al., `` Electrical Spin Injection and Transport in Semiconductor Spintronic Devices '', MRS Bulletin, October 2003, p.740-748 Sanvito et al., "Ab Initio Transport Theory for Digital Ferromagnetic Heterostructure", Physical Review Letters, Vol. 87, No. 26, December 24, 2001, p.1-4

  In view of the above background art, an object of the present invention is to provide a spintronic device that is easy to manufacture and exhibits good spintronic characteristics at, for example, room temperature or higher.

  These and other objects, features and advantages in accordance with the present invention include at least one superlattice and at least one electrical contact coupled thereto, wherein the at least one superlattice has a plurality of layers. Fulfilled by spintronic devices. Each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and spintronics Can have a dopant. Further, the spintronic dopant can be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. Accordingly, a considerably higher spintronic dopant concentration can be achieved and maintained while reducing the possibility of precipitating the spintronic dopant.

  The spintronic dopant can have at least one spintronic dopant monolayer adjacent to the at least one non-semiconductor monolayer. For example, this may be the case if the energy level favors the attraction and retention of the spintronic dopant to the non-semiconductor. The spintronic dopant may comprise a transition metal such as at least one of manganese, iron and chromium. Alternatively or in addition, the spintronic dopant may include a rare earth element such as a rare earth lanthanide.

  The non-semiconductor may have one or more of oxygen, nitrogen, fluorine, carbon-oxygen, and sulfur, for example. The semiconductor may comprise silicon or, more generally, may comprise a semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Specific materials and structural configurations can be preferably selected such that the superlattice exhibits a Curie temperature above room temperature.

  One embodiment of a spintronic device is a spintronic field effect transistor. Along with that, the spintronic FET includes a substrate carrying a pair of superlattices spaced apart so as to define the source and drain, a channel between the source and drain, and a gate adjacent to the channel. obtain. Another embodiment of the spintronic device is a spin valve. The spin valve may include a substrate carrying a pair of superlattices spaced apart from each other and a spacer between the pair of superlattices.

  In some embodiments, a repetitive structure of the superlattice is not required. In other words, the spintronic device comprises a plurality of stacked base semiconductor monolayers that define a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice, and the at least one non-conductor layer. There may be a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the semiconductor monolayer. In addition, the device may include an electrical contact coupled to the base semiconductor portion.

  An aspect relating to a method of manufacturing a spintronic device includes a step of forming at least one superlattice and a step of forming at least one electrical contact coupled to the superlattice, wherein the at least one superlattice includes a plurality of superlattices. It has a layer group. Each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and spintronics Can have a dopant. Further, the spintronic dopant can be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. Based on the disclosure herein, other method aspects will be appreciated by those skilled in the art.

  The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout, similar reference numbers shall refer to similar elements.

  First, a first embodiment of the present invention will be described with reference to FIGS. 6A and 6B. In the DFH structure 20 schematically shown in FIG. 6A, oxygen is included in a Si superlattice containing a transition metal such as Mn. As can be seen in the energy level diagram 21 of FIG. 6B, Mn has a lower energy as it approaches the oxygen layer. In other words, when the Mn atom sticks to the silicon atom, this structure is the most energetically favorable and the Mn atom is properly positioned and constrained in the silicon. As will be appreciated by those skilled in the art, positioning the Mn atom relative to the oxygen atom can be used, for example, to adjust the Curie temperature (Tc). For example, in a 2D restraint system, Tc can be much higher than room temperature. The oxygen-containing DFH structure 20 is advantageously more thermally stable than conventional structures.

  For example, Mn substitutes only a small stress in the silicon single crystal structure. Mn is an example of a transition metal suitable for a spintronic device. As will be appreciated by those skilled in the art, other materials such as Fe and Cr may be used as well. For example, rare earth elements such as rare earth lanthanides can also be used.

  Other substances may be used instead of oxygen or in combination with oxygen. For example, nitrogen, fluorine, carbon-oxygen, and sulfur are suitable materials. Also, the base semiconductor, illustratively in the form of Si, may be a semiconductor selected from a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. Of course, the term group IV semiconductor includes group IV-IV semiconductors.

  The charge and spin densities of the various layers of the DFH structure 22 and the incorporation of oxygen in addition to Mn into the Si single crystal superlattice are schematically illustrated in FIG. Layer 1 is shown in a conductive state, as opposed to the other layers, layers 6 and 16.

  A schematic atomic model 25 comprising a transition metal (eg, Mn) incorporated with oxygen in a silicon lattice is shown in FIG. Referring to FIG. 9, a spin-up energy state 27 (upper diagram) and a spin-down energy state 28 (lower diagram) are shown. The spin-up energy diagram 27, as will be appreciated by those skilled in the art, and in contrast to the high energy state at the Fermi level in the case of the spin-down diagram 28, the current is due to the low energy state at the Fermi level. It points to flowing.

  Still referring to FIGS. 10A-C, the relative energies of various Si—Mn—O structures are schematically shown. More specifically, the structure 31 shown in FIG. 10A having an oxygen atom between adjacent Mn atoms shows the lowest stability, and FIG. 10B shows an oxygen atom separated from a pair of Mn atoms. The structure 32 shown in FIG. 10C shows intermediate stability, and the structure 33 shown in FIG. 10C having an oxygen atom bonded to one of a pair of Mn atoms shows the highest relative stability.

  In some embodiments, the spintronic device has at least one superlattice and at least one electrical contact coupled thereto, the at least one superlattice having a plurality of layers. Each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and spintronics Can have a dopant. The base semiconductor portion has, for example, 5 to 30 monolayers. The spintronic dopant can be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. Accordingly, a relatively high spintronic dopant concentration can be achieved and maintained while reducing the possibility of spintronic dopant shedding. For example, the concentration of the spintronic dopant can be in the range of about 0.1-10%.

  The spintronic dopant can have at least one spintronic dopant monolayer adjacent to the at least one non-semiconductor monolayer. For example, this may be the case if the energy level favors the attraction and retention of the spintronic dopant to the non-semiconductor.

  For further details regarding superlattice structures containing silicon and oxygen, for example to achieve energy band modification to increase charge carrier mobility, see, for example, US Pat. Nos. 6,891,188 and 7,153,763 of the Applicant. It is described in. Note that the entire contents thereof are incorporated herein by reference. While not wishing to be bound by theory, applicants have found that, according to the spintronic devices described herein, non-semiconductor monolayers can become spintronic dopants, especially during any subsequent thermal processing steps, as will be appreciated by those skilled in the art. It is theorized that the dopant can act to collect, or at least contain, so that it does not fall off. In some embodiments, the spintronic dopant may be added by atomic layer deposition. In other embodiments, for example, the spintronic dopant may be added by ion implantation and optionally annealed thereafter. Meanwhile, the non-semiconductor monolayer acts to at least contain the dopant.

  Non-semiconductor monolayers may initially be formed discontinuously. That is, for example, a non-semiconductor monolayer may not initially be filled at all positions in the silicon lattice that can accept oxygen. Also, applicants still do not want to be bound by theory, but monolayer atomic layer deposition (ALD) is particularly well-defined or precisely defined monolayers, especially when subsequently subjected to heat treatment. Theorized that there is a tendency to form clusters at the atomic level. For example, the superlattice is optionally formed prior to the formation of shallow trench isolation (STI) and is therefore subjected to heat treatment during STI formation.

  Thus, the term monolayer extends to this theorized clustering phenomenon, as will be appreciated by those skilled in the art, and is not limited to an exact mathematical or atomic stick model layer. . Applicants also do not want to be bound by theory, but that the clustering phenomenon can be considered to occur with spintronic dopants, especially in the case of a combination of materials such as Si-O-Mn, where Mn is attracted to O. Theorize.

  To further extend the principles described herein, in some embodiments, a superlattice repetitive structure may not be required. In other words, the spintronic device includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice, and the at least one non-semiconductor There may be a spintronic dopant constrained by the monolayer within the crystal lattice of the base semiconductor portion. The spintronic device may also include an electrical contact coupled to the base semiconductor portion.

  Next, an example of a spintronic device in the form of a spintronic field effect transistor (FET) 40 will be described with reference to FIG. The spintronics FET 40 illustratively includes a semiconductor substrate 41, which is a pair of superlattices that are spaced apart to define a source 43 and a drain 44, a channel between the source and drain. 45 and a gate 50 adjacent to the channel. The gate 50 includes a dielectric layer 52 and a gate electrode or gate contact 51 thereon.

  For clarity of explanation, the source 43 and drain 44 are shown using a plurality of horizontally extending lines that schematically represent repetitive superlattice groups, and the spintronic dopant is represented by dots. Source contact 46 and drain contact 47 are illustratively coupled to source 43 and drain 44, respectively. Channel 45 is also illustratively in the form of a superlattice, but does not have a spintronic dopant. In other embodiments, the channel need not be a superlattice, as will be appreciated by those skilled in the art. In still other embodiments, only one of the source or drain may be a superlattice.

  Another embodiment of the spintronic device is a spin valve 60 described also with reference to FIG. The spin valve 60 also includes a semiconductor substrate 61, and the semiconductor substrate 61 carries a pair of superlattices 62 and 63 spatially separated by spacers 66 on the upper surface thereof. Respective electrical contacts 64 and 65 are coupled to the superlattices 62 and 63. As will be appreciated by those skilled in the art, one of the superlattices 62, 63 is configured to be pinned or to be a hard ferromagnetic region while the other is a soft ferromagnetic region. May be.

  One aspect of the method is a method of manufacturing a spintronic device, comprising forming at least one superlattice and forming at least one electrical contact coupled to the superlattice, the at least one One superlattice has a plurality of layers. Each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice, at least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and spintronics Can have a dopant. The spintronic dopant can also be constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer. Based on the teachings herein, other method aspects will be apparent to those of skill in the art.

  The spintronic devices described herein, including spintronic FETs and spin valves, may be configured without using superlattice repetitive structures, as will be appreciated by those skilled in the art. The materials described herein can be used in numerous spintronic devices, particularly for improving spin carrier injection efficiency, which is believed to be due to the compatibility of the materials at the interface. The thermal stability of the device is also greatly improved. This is believed to be due to oxygen being retained in the crystal lattice and Mn being thermally stable next to the oxygen atom. General references in the field of spintronics also include Park et al., Science 295, page 651 (2002), Qian et al., Phys. Rev. Lett. There are 96 volumes of 027211 pages (2006) and Ono et al., Nature volume 402 pages of 790 pages (1999).

  Those skilled in the art who have benefited from the teachings presented in the foregoing description and the accompanying drawings will envision numerous modifications and other embodiments of the invention. Thus, the present invention is not limited to the specific embodiments disclosed herein, and such modifications and embodiments are intended to be included within the scope of the present invention.

It is the schematic which shows the spin valve which concerns on the prior art in a low resistance state. 1B is a schematic diagram illustrating the prior art spin valve of FIG. 1A in a high resistance state. FIG. It is a perspective view which shows schematically the spin FET which concerns on a prior art. It is the schematic which shows the qubit device which concerns on a prior art. It is the schematic which shows the magnetic material which concerns on a prior art. It is the schematic which shows the dilution magnetic material which concerns on a prior art. It is the schematic which shows the nonmagnetic material which concerns on a prior art. 1 is an atomic diagram schematically showing a digital ferromagnetic heterostructure according to the prior art. A and B are a schematic diagram showing a DFH according to the present invention and an energy level diagram of the DFH, respectively. 1 is an atomic diagram schematically showing a DFH structure according to the present invention. FIG. 1 is an atomic diagram schematically showing a part of a superlattice for a spintronic device according to the present invention. FIG. FIG. 9 is a bond energy diagram for the superlattice shown in FIG. 8. AC is an atomic diagram schematically showing the relative atomic positions of Si, O and Mn in the spintronic device according to the present invention. 1 is a cross-sectional view schematically showing a spintronic FET according to the present invention. 1 is a cross-sectional view schematically showing a spin valve according to the present invention.

Claims (42)

At least one superlattice; and at least one electrical contact coupled to the at least one superlattice;
A spintronic device having:
The at least one superlattice has a plurality of layer groups, each layer group:
A plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice;
At least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer;
Having
Spintronic devices.   The spintronic device of claim 1, wherein the spintronic dopant has at least one spintronic dopant monolayer adjacent to the at least one non-semiconductor monolayer.   The spintronic device of claim 1, wherein the spintronic dopant comprises a transition metal.   The spintronic device of claim 1, wherein the spintronic dopant comprises manganese.   4. The spintronic device of claim 3, wherein the at least one transition metal comprises one or more of manganese, iron and chromium.   The spintronic device of claim 1, wherein the spintronic dopant comprises a rare earth element.   The spintronic device of claim 6, wherein the rare earth element comprises a rare earth lanthanide.   The spintronic device of claim 1, wherein the non-semiconductor comprises oxygen.   The spintronic device of claim 1, wherein the non-semiconductor comprises one or more of oxygen, nitrogen, fluorine, carbon-oxygen, and sulfur.   The spintronic device of claim 1, wherein the semiconductor comprises silicon.   The spintronic device of claim 1, wherein the semiconductor comprises a semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. The at least one superlattice has a pair of superlattices, and the spintronic device is:
A substrate carrying the pair of superlattices spaced apart so as to define a source and a drain;
A channel between the source and the drain; and a gate adjacent to the channel;
The spintronic device of claim 1, further comprising: a spintronic field effect transistor. The at least one superlattice has a pair of superlattices, and the spintronic device is:
A substrate carrying the pair of superlattices spaced apart from each other; and a spacer between the pair of superlattices;
The spintronic device of claim 1, further comprising: a spintronic valve.   The spintronic device according to claim 1, wherein the at least one superlattice exhibits a Curie temperature equal to or higher than room temperature. A plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice;
At least one non-semiconductor monolayer constrained within the crystal lattice;
A spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer; and an electrical contact coupled to the base semiconductor portion;
Spintronic device with   16. The spintronic device of claim 15, wherein the spintronic dopant has at least one spintronic dopant monolayer adjacent to the at least one non-semiconductor monolayer.   The spintronic device of claim 15, wherein the spintronic dopant comprises at least one of a transition metal and a rare earth element.   The spintronic device of claim 15, wherein the non-semiconductor comprises one or more of oxygen, nitrogen, fluorine, carbon-oxygen, and sulfur.   16. The spintronic device of claim 15, wherein the semiconductor comprises a semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor.   The spintronic device of claim 15, further comprising a substrate carrying the base semiconductor portion.   The spintronic device according to claim 15, wherein the base semiconductor portion exhibits a Curie temperature equal to or higher than room temperature. Forming at least one superlattice; and forming at least one electrical contact coupled to the at least one superlattice;
A method of manufacturing a spintronic device having:
The at least one superlattice has a plurality of layer groups, each layer group:
A plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice;
At least one non-semiconductor monolayer constrained within the crystal lattice of adjacent base semiconductor portions, and a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer;
Having
Spintronic devices.   23. The method of claim 22, wherein the spintronic dopant has at least one spintronic dopant monolayer adjacent to the at least one non-semiconductor monolayer.   23. The method of claim 22, wherein the spintronic dopant comprises a transition metal.   24. The method of claim 22, wherein the spintronic dopant comprises manganese.   25. The method of claim 24, wherein the at least one transition metal comprises one or more of manganese, iron and chromium.   23. The method of claim 22, wherein the spintronic dopant comprises a rare earth element.   28. The method of claim 27, wherein the rare earth element comprises a rare earth lanthanide.   24. The method of claim 22, wherein the non-semiconductor comprises oxygen.   24. The method of claim 22, wherein the non-semiconductor comprises one or more of oxygen, nitrogen, fluorine, carbon-oxygen, and sulfur.   The method of claim 22, wherein the semiconductor comprises silicon.   23. The method of claim 22, wherein the semiconductor comprises a semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. The step of forming the at least one superlattice comprises forming a pair of superlattices, and the method includes:
Providing a substrate carrying the pair of superlattices spaced apart so as to define a source and a drain;
Forming a channel between the source and the drain; and forming a gate adjacent to the channel;
23. The method of claim 22, further comprising: wherein the spintronic device defines a spintronic field effect transistor. The step of forming the at least one superlattice comprises the step of forming a pair of superlattices, and the method includes:
Providing a substrate carrying the pair of superlattices spaced apart from each other; and forming a spacer between the pair of superlattices;
23. The method of claim 22, further comprising: wherein the spintronic device defines a spintronic valve.   23. The method of claim 22, wherein the at least one superlattice exhibits a Curie temperature that is greater than or equal to room temperature. Forming a plurality of stacked base semiconductor monolayers defining a base semiconductor portion having a crystal lattice;
Forming at least one non-semiconductor monolayer constrained within the crystal lattice;
Providing a spintronic dopant constrained within the crystal lattice of the base semiconductor portion by the at least one non-semiconductor monolayer; and forming an electrical contact coupled to the base semiconductor portion;
A method of manufacturing a spintronic device having:   37. The method of claim 36, wherein the spintronic dopant has at least one spintronic dopant monolayer adjacent to the at least one non-semiconductor monolayer.   40. The method of claim 36, wherein the spintronic dopant comprises at least one of a transition metal and a rare earth element.   40. The method of claim 36, wherein the non-semiconductor comprises one or more of oxygen, nitrogen, fluorine, carbon-oxygen, and sulfur.   37. The method of claim 36, wherein the semiconductor comprises a semiconductor selected from the group consisting of a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor.   38. The method of claim 36, further comprising providing a substrate carrying the base semiconductor portion.   37. The method of claim 36, wherein the base semiconductor portion exhibits a Curie temperature that is greater than or equal to room temperature.

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