JP2009512090A - 埋め込み型マスキングを備える高速ローテータ及びその方法 - Google Patents

埋め込み型マスキングを備える高速ローテータ及びその方法 Download PDF

Info

Publication number
JP2009512090A
JP2009512090A JP2008536674A JP2008536674A JP2009512090A JP 2009512090 A JP2009512090 A JP 2009512090A JP 2008536674 A JP2008536674 A JP 2008536674A JP 2008536674 A JP2008536674 A JP 2008536674A JP 2009512090 A JP2009512090 A JP 2009512090A
Authority
JP
Japan
Prior art keywords
operand
rotator
decoder
input
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2008536674A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009512090A5 (enExample
Inventor
ヌニュス，リンカーン・アール
ダニシュ，アルバート・エヌ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JP2009512090A publication Critical patent/JP2009512090A/ja
Publication of JP2009512090A5 publication Critical patent/JP2009512090A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/764—Masking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/017—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising using recirculating storage elements
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/768—Data position reversal, e.g. bit reversal, byte swapping

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Executing Machine-Instructions (AREA)
JP2008536674A 2005-10-17 2006-10-04 埋め込み型マスキングを備える高速ローテータ及びその方法 Pending JP2009512090A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/252,061 US20070088772A1 (en) 2005-10-17 2005-10-17 Fast rotator with embedded masking and method therefor
PCT/US2006/039180 WO2007047167A2 (en) 2005-10-17 2006-10-04 Fast rotator with embedded masking and method therefor

Publications (2)

Publication Number Publication Date
JP2009512090A true JP2009512090A (ja) 2009-03-19
JP2009512090A5 JP2009512090A5 (enExample) 2009-11-19

Family

ID=37949361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008536674A Pending JP2009512090A (ja) 2005-10-17 2006-10-04 埋め込み型マスキングを備える高速ローテータ及びその方法

Country Status (4)

Country Link
US (1) US20070088772A1 (enExample)
JP (1) JP2009512090A (enExample)
KR (1) KR20080049825A (enExample)
WO (1) WO2007047167A2 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011013920A (ja) * 2009-07-01 2011-01-20 Fujitsu Ltd シフト演算器

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE602006005020D1 (de) * 2005-05-04 2009-03-19 St Microelectronics Sa Ringschieberegister
FR2914447B1 (fr) * 2007-03-28 2009-06-26 St Microelectronics Sa Dispositif electronique de decalage de donnees en particulier pour du codage/decodage avec un code ldpc
US8041755B2 (en) * 2007-06-08 2011-10-18 Apple Inc. Fast static rotator/shifter with non two's complemented decode and fast mask generation
US8356145B2 (en) * 2010-01-15 2013-01-15 Qualcomm Incorporated Multi-stage multiplexing operation including combined selection and data alignment or data replication
US8768989B2 (en) * 2011-03-18 2014-07-01 Apple Inc. Funnel shifter implementation
US8972469B2 (en) 2011-06-30 2015-03-03 Apple Inc. Multi-mode combined rotator
US20130151820A1 (en) * 2011-12-09 2013-06-13 Advanced Micro Devices, Inc. Method and apparatus for rotating and shifting data during an execution pipeline cycle of a processor
US10289382B2 (en) 2012-12-20 2019-05-14 Wave Computing, Inc. Selectively combinable directional shifters
US9933996B2 (en) * 2012-12-20 2018-04-03 Wave Computing, Inc. Selectively combinable shifters
US9419792B2 (en) * 2012-12-28 2016-08-16 Intel Corporation Instruction for accelerating SNOW 3G wireless security algorithm
US9490971B2 (en) * 2012-12-28 2016-11-08 Intel Corporation Instruction for fast ZUC algorithm processing
US9904511B2 (en) * 2014-11-14 2018-02-27 Cavium, Inc. High performance shifter circuit
US9904545B2 (en) * 2015-07-06 2018-02-27 Samsung Electronics Co., Ltd. Bit-masked variable-precision barrel shifter
GB2637295A (en) * 2024-01-10 2025-07-23 Imagination Tech Ltd Vector bitwise rotations

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5350629A (en) * 1976-10-18 1978-05-09 Burroughs Corp High speed shift network
JPH02197919A (ja) * 1989-01-27 1990-08-06 Matsushita Electric Ind Co Ltd 異種サイズ対応ローテータとシフタ
JP2002512398A (ja) * 1998-04-23 2002-04-23 インフィニオン テクノロジーズ ノース アメリカ コーポレイション パックデータ上でシフト演算を実行するための方法および装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4396994A (en) * 1980-12-31 1983-08-02 Bell Telephone Laboratories, Incorporated Data shifting and rotating apparatus
US4653019A (en) * 1984-04-19 1987-03-24 Concurrent Computer Corporation High speed barrel shifter
US5961635A (en) * 1993-11-30 1999-10-05 Texas Instruments Incorporated Three input arithmetic logic unit with barrel rotator and mask generator
US6116768A (en) * 1993-11-30 2000-09-12 Texas Instruments Incorporated Three input arithmetic logic unit with barrel rotator
US5652718A (en) * 1995-05-26 1997-07-29 National Semiconductor Corporation Barrel shifter
US5729482A (en) * 1995-10-31 1998-03-17 Lsi Logic Corporation Microprocessor shifter using rotation and masking operations
US5844825A (en) * 1996-09-03 1998-12-01 Wang; Song-Tine Bidirectional shifter circuit
US5822231A (en) * 1996-10-31 1998-10-13 Samsung Electronics Co., Ltd. Ternary based shifter that supports multiple data types for shift functions
US6260055B1 (en) * 1997-10-15 2001-07-10 Kabushiki Kaisha Toshiba Data split parallel shifter and parallel adder/subtractor
US6393446B1 (en) * 1999-06-30 2002-05-21 International Business Machines Corporation 32-bit and 64-bit dual mode rotator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5350629A (en) * 1976-10-18 1978-05-09 Burroughs Corp High speed shift network
JPH02197919A (ja) * 1989-01-27 1990-08-06 Matsushita Electric Ind Co Ltd 異種サイズ対応ローテータとシフタ
JP2002512398A (ja) * 1998-04-23 2002-04-23 インフィニオン テクノロジーズ ノース アメリカ コーポレイション パックデータ上でシフト演算を実行するための方法および装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011013920A (ja) * 2009-07-01 2011-01-20 Fujitsu Ltd シフト演算器

Also Published As

Publication number Publication date
KR20080049825A (ko) 2008-06-04
US20070088772A1 (en) 2007-04-19
WO2007047167A2 (en) 2007-04-26
WO2007047167A3 (en) 2008-01-17

Similar Documents

Publication Publication Date Title
US20190199370A1 (en) Floating point to fixed point conversion
US8909901B2 (en) Permute operations with flexible zero control
US6671797B1 (en) Microprocessor with expand instruction for forming a mask from one bit
CN107273095B (zh) 用于对齐寄存器的系统、装置和方法
CN102169427B (zh) 实施混洗指令的设备、方法和操纵数据操作数的设备
CN108563465B (zh) 用于响应于单个指令来执行循环和异或的系统、装置和方法
CN118132146A (zh) 用于下转换以及交错多个浮点值的装置和方法
JP2009512090A (ja) 埋め込み型マスキングを備える高速ローテータ及びその方法
WO2008036946A1 (en) Method and apparatus for performing logical compare operation
US10459728B2 (en) Apparatus and method of improved insert instructions
TWI637317B (zh) 用於將遮罩擴充為遮罩值之向量的處理器、方法、系統及裝置
CN106605206A (zh) 位组交织处理器、方法、系统及指令
CN104094182A (zh) 掩码置换指令的装置和方法
US5787025A (en) Method and system for performing arithmetic operations with single or double precision
JPH0916397A (ja) 複数のコンピュータ・ワードにパックされている複数のサブ・ワード・アイテムの選択混合システム
WO2012040552A2 (en) Method and apparatus for universal logical operations
CN108139911A (zh) 在vliw处理器的同一执行包中使用有条件扩展槽的指令的有条件执行规格
US10719317B2 (en) Hardware apparatuses and methods relating to elemental register accesses
US20200249955A1 (en) Pair merge execution units for microinstructions
CN111352658A (zh) 用于在从存储器加载时在进行中转置向量的系统和方法
US20030037085A1 (en) Field processing unit
US20160139924A1 (en) Machine Level Instructions to Compute a 4D Z-Curve Index from 4D Coordinates
KR102528073B1 (ko) 벡터 비트 수집을 수행하기 위한 방법 및 장치
US20170161069A1 (en) Microprocessor including permutation instructions
US20080148018A1 (en) Shift Processing Unit

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091001

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20091001

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110726

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120112