JP2009506553A - Microelectronic device package, stacked microelectronic device package, and method of manufacturing microelectronic device - Google Patents

Microelectronic device package, stacked microelectronic device package, and method of manufacturing microelectronic device Download PDF

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JP2009506553A
JP2009506553A JP2008528182A JP2008528182A JP2009506553A JP 2009506553 A JP2009506553 A JP 2009506553A JP 2008528182 A JP2008528182 A JP 2008528182A JP 2008528182 A JP2008528182 A JP 2008528182A JP 2009506553 A JP2009506553 A JP 2009506553A
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substrate
die
microelectronic
package
microelectronic package
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JP5522561B2 (en
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キム ダルソン イエ，セン
ホイ チョン，チン
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マイクロン テクノロジー， インク．
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    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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Abstract

積み重ね可能なマイクロ電子パッケージが、第１の基板に取り付けられ、ならびに第１の基板と電気的に接続する第１のマイクロ電子ダイを含む。第２のマイクロ電子ダイは、一方の面が第１のダイに、他方の面が第２の基板に取り付けられる。第１のダイと第１の基板との間、第２のダイと第２の基板との間、および第１の基板と第２の基板との間の電気的接続が、例えばワイヤボンディングによって行われる。電気的接続要素は、モールドコンパウンドで有利に覆われる。モールドコンパウンドで覆われていない第１および／または第２の基板上の露出コンタクトは、パッケージとパッケージ上に積み重ねられる他のパッケージとの間の電気的接続を可能にする。パッケージは、共平面性ファクタを回避することができ、既存の設備を用いて製造することができ、中間試験を可能にし、およびより薄いパッケージ高さを提供することもできる。
【選択図】図１A stackable microelectronic package includes a first microelectronic die attached to the first substrate and electrically connected to the first substrate. The second microelectronic die has one surface attached to the first die and the other surface attached to the second substrate. The electrical connection between the first die and the first substrate, between the second die and the second substrate, and between the first substrate and the second substrate is performed, for example, by wire bonding. Is called. The electrical connection element is advantageously covered with a mold compound. Exposed contacts on the first and / or second substrate that are not covered by the mold compound allow for electrical connection between the package and other packages stacked on the package. The package can avoid coplanarity factors, can be manufactured using existing equipment, can allow intermediate testing, and can also provide a thinner package height.
[Selection] Figure 1

Description

本発明は、マイクロ電子デバイスパッケージ（ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ ｄｅｖｉｃｅ ｐａｃｋａｇｅ）、積重ね型マイクロ電子デバイスパッケージ（ｓｔａｃｋｅｄ ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ ｄｅｖｉｃｅ ｐａｃｋａｇｅ）、およびマイクロ電子デバイスを製造する方法に関する。   The present invention relates to a microelectronic device package, a stacked microelectronic device package, and a method of manufacturing a microelectronic device.

マイクロ電子デバイスは一般に、高密度の微小構成要素を有する集積回路を含むダイ（すなわちチップ）を有する。典型的なプロセスでは、多数のダイが、様々な段階（例えば、注入、ドーピング、フォトリソグラフィ、化学気相成長、プラズマ気相成長、めっき、平坦化、エッチングなど）で繰り返すことができる様々なプロセスを用いて、単一ウェハ上に製造される。ダイは一般に、集積回路に電気的に結合される微小ボンドパッドの配列を含む。ボンドパッドは、供給電圧、信号などが、それを通って集積回路に往復伝送される、ダイ上の外部電気コンタクトである。次に、ダイは、ウェハをダイシングし個々のダイを裏面研削することによって、互いに分離される（すなわち個片化される）。ダイは一般に、個片化された後、ボンドパッドを、様々な電源線、信号線、および接地線により容易に結合されうるより大きな配列の電気端子に結合させるために、「パッケージ化」される。   Microelectronic devices typically have a die (or chip) that includes an integrated circuit having a high density of microcomponents. In a typical process, various dies can be repeated in various stages (eg, implantation, doping, photolithography, chemical vapor deposition, plasma vapor deposition, plating, planarization, etching, etc.). Are manufactured on a single wafer. The die generally includes an array of micro bond pads that are electrically coupled to the integrated circuit. A bond pad is an external electrical contact on a die through which supply voltages, signals, etc. are transferred back and forth to an integrated circuit. The dies are then separated from one another (ie, singulated) by dicing the wafer and backgrinding the individual dies. The dies are generally “packaged” after being singulated to bond the bond pads to a larger array of electrical terminals that can be easily coupled by various power, signal and ground lines. .

個々のダイは、ダイ上のボンドパッドをピン、ボールパッドまたは他のタイプの電気端子の配列に電気的に結合し、次いでダイをモールドコンパウンド内に封止して、ダイを環境因子（例えば、湿気、粒子、静電気、および物理的衝撃）から保護し、ならびにマイクロ電子デバイスパッケージを形成することによって、パッケージ化されうる。１つの応用例では、ボンドパッドは、ボールパッド配列を有するインタポーザ基板上のコンタクトに電気的に接続される。   Individual dies electrically couple bond pads on the die to an array of pins, ball pads, or other types of electrical terminals, and then seal the die in a mold compound to make the die an environmental factor (e.g., It can be packaged by protecting it from moisture, particles, static electricity, and physical shock) and forming a microelectronic device package. In one application, the bond pads are electrically connected to contacts on an interposer substrate having a ball pad array.

電子製品は、非常に限られた空間に極めて高密度の構成要素を有するために、パッケージ化したマイクロ電子デバイスを必要とする。例えば、記憶装置、プロセッサ、表示装置、および他のマイクロ電子構成要素のために使用可能な空間は、携帯電話、ＰＤＡ、携帯用コンピュータ、および他の多くの製品内で極めて限定される。したがって、プリント回路板上のマイクロ電子デバイスの表面積すなわち「フットプリント」を縮小するために、強力な動因がある。マイクロ電子デバイスのサイズを縮小するのは、困難となりうる。というのは、高性能のマイクロ電子デバイスは一般に、より多くのボンドパッドを有し、それによってボールグリッドアレイが大きくなり、したがってフットプリントが大きくなるからである。所与のフットプリント内のマイクロ電子デバイスの密度を増大させるために用いられる１つの技法は、１つのマイクロ電子デバイスパッケージを他のパッケージの上に積み重ねることである。しかし、こうした既存の積重ね設計にはいくつかの欠点がありうる。例えば、それらは、相互接続のために基板上に余分な空間を必要としたり、デバイスの個別の品質管理試験を妨げたり、あるいは他の欠点を有する可能性がある。   Electronic products require packaged microelectronic devices in order to have very high density components in a very limited space. For example, the space available for storage devices, processors, display devices, and other microelectronic components is very limited within cell phones, PDAs, portable computers, and many other products. Thus, there is a strong drive to reduce the surface area or “footprint” of the microelectronic device on the printed circuit board. It can be difficult to reduce the size of a microelectronic device. This is because high performance microelectronic devices typically have more bond pads, which results in a larger ball grid array and therefore a larger footprint. One technique used to increase the density of microelectronic devices within a given footprint is to stack one microelectronic device package on top of another. However, these existing stack designs can have several drawbacks. For example, they may require extra space on the substrate for interconnection, interfere with individual quality control testing of the device, or have other drawbacks.

マイクロ電子パッケージは、単一パッケージ内に２つのチップまたはダイを有利に含む。これは、場所を取らない設計を可能にする。ある設計では、より薄いパッケージを実現することもできる。パッケージは、ダイが積重ねアセンブリに配置される前に個別に試験
されうるように、設計することができる。ダイは、共平面性の欠点をよりうまく回避するために、任意で背中合わせに配置することもできる。一実施形態では、マイクロ電子パッケージは、第１の基板と電気的に接続する第１のマイクロ電子ダイと、第１の基板と電気的に接続する第２の基板と、第２の基板と電気的に接続する第２のマイクロ電子ダイとを有する。電気的接続がワイヤボンディングによって行われる設計では、一方の基板が他方の基板よりも大きいことが有利である。 The microelectronic package advantageously includes two chips or dies in a single package. This allows for a space-saving design. In some designs, thinner packages can be realized. The package can be designed so that the dies can be individually tested before being placed in the stack assembly. The dies can optionally be placed back to back to better avoid the coplanarity drawbacks. In one embodiment, the microelectronic package includes a first microelectronic die that is electrically connected to the first substrate, a second substrate that is electrically connected to the first substrate, and a second substrate that is electrically connected to the second substrate. And a second microelectronic die that are connected together. In designs where the electrical connection is made by wire bonding, it is advantageous that one substrate is larger than the other substrate.

マイクロ電子パッケージは、積重ねアセンブリを形成するために、他のすなわち第２のマイクロ電子パッケージに積み重ねる、または取り付けることができる。一方のマイクロ電子パッケージの第１の基板上のコンタクトを、他方のマイクロ電子パッケージの第２の基板上のコンタクトに電気的に接続または連接することにより、２つのマイクロ電子パッケージアセンブリを電気的に接続することができる。積み重ねられるパッケージは、回路板に取り付けられ、どちらか一方のパッケージの別の基板上のコンタクトを介して回路板に電気的に接続されうる。   The microelectronic package can be stacked or attached to another or second microelectronic package to form a stack assembly. Electrical connection between two microelectronic package assemblies by electrically connecting or connecting contacts on the first substrate of one microelectronic package to contacts on the second substrate of the other microelectronic package can do. The stacked packages are attached to the circuit board and can be electrically connected to the circuit board via contacts on another substrate of either package.

本発明のいくつかの実施形態の多くの具体的な詳細について、複数のマイクロ電子デバイスを単一アセンブリに一体に形成することに関して以下に説明するが、他の実施形態では、各デバイスを別々に形成することができる。本発明によるいくつかの実施形態は、図面に記載されている。しかし、図面は、説明だけのために提供される。それらは、本発明の範囲を限定して示すものではない。以下の文章は、本発明の特定の実施形態を十分理解できるように提供される。しかし、当業者なら、本発明が追加の実施形態を有しうること、あるいは、本発明が、図面に記載されている、または示される詳細のうちのいくつかがなくても実施されうることを理解する。   Many specific details of some embodiments of the invention are described below with respect to integrally forming a plurality of microelectronic devices in a single assembly, but in other embodiments, each device is separately Can be formed. Several embodiments according to the invention are described in the drawings. However, the drawings are provided for illustration only. They are not intended to limit the scope of the invention. The following text is provided to provide a thorough understanding of certain embodiments of the invention. However, one of ordinary skill in the art appreciates that the present invention may have additional embodiments or that the invention may be practiced without some of the details described or illustrated in the drawings. to understand.

ここで図１を参照すると、積み重ね可能なマイクロ電子パッケージ（ｓｔａｃｋａｂｌｅ ｍｉｃｒｏｅｌｅｃｔｒｏｎｉｃ ｐａｃｋａｇｅ）１０が、開口または溝１４を有する第１の基板１２を有する。開口１４は、基板１２のほぼ中心に有利に位置することができる。第１のマイクロ電子ダイまたはチップ１８は、活性面４０および裏面４２を有する。活性面４０は、第１の基板１２に取り付けられるか、または隣接している。ダイ１８の活性面４０は、基板１２の第２の面（ここでは上面として示される）上のコンタクトと電気的に接続する端子（例えばボンドパッド）を有する。端子およびコンタクトは、典型的にはアレイ状に配置される。基板１２上のコンタクトは一般に、基板１２の第１の面（ここでは底面として示される）上の他のコンタクトに電気的に接続されて、アセンブリ１０を回路板または他の上位アセンブリと電気的に接続できるようにする。   Referring now to FIG. 1, a stackable microelectronic package 10 has a first substrate 12 having an opening or groove 14. The opening 14 can advantageously be located approximately in the center of the substrate 12. The first microelectronic die or chip 18 has an active surface 40 and a back surface 42. The active surface 40 is attached to or adjacent to the first substrate 12. The active surface 40 of the die 18 has terminals (eg, bond pads) that are electrically connected to contacts on a second surface (shown here as the top surface) of the substrate 12. Terminals and contacts are typically arranged in an array. Contacts on the substrate 12 are typically electrically connected to other contacts on the first side of the substrate 12 (shown here as the bottom side) to electrically connect the assembly 10 with a circuit board or other upper assembly. Enable connection.

第２のマイクロ電子ダイまたはチップ２２は、第１のダイ１８の裏面に、好ましくは接着剤２０で取り付けられる裏面４２を有する。この取付け（ならびに本明細書で記載される他の取付け）は、直接でも間接でもよく、すなわち、それらの間に１つ以上の中間要素があってもなくてもよい。各ダイ１８および２２は一般に、２５に破線で概略的に示される１つ以上の集積回路を有する。第２の基板２４は、第２のダイ２２の活性面４０に取り付けられる。   The second microelectronic die or chip 22 has a back surface 42 that is preferably attached to the back surface of the first die 18 with an adhesive 20. This attachment (as well as other attachments described herein) may be direct or indirect, i.e., with or without one or more intermediate elements therebetween. Each die 18 and 22 generally has one or more integrated circuits indicated schematically at 25 by dashed lines. The second substrate 24 is attached to the active surface 40 of the second die 22.

第１の基板１２は、第２の基板２４よりも大きく（すなわち、幅が広くおよび／または長さが長い）、これは、図１に示されるように、第１の基板１２が第２の基板２４から外に広がることを意味する。第１の基板１２の上面すなわち第２の面上のパッドまたはコンタクト３４を、第２の基板２４の上面すなわち第２の面上のパッドまたはコンタクト３４に接続することによって、第１の基板と第２の基板との間で電気的接続が行われる。これらの接続は、ワイヤボンド２６によって行うことができる。第１の基板上のコンタクト３４は、第２の基板２４から外に広がる第１の基板１２の領域上に位置するので、それらの
間のボンド接続は、既存の技法を用いて行うことができる。パッドまたはコンタクト３４および３８は、説明のために、図１に破線で拡大して不釣り合いに示される。 The first substrate 12 is larger (i.e., wider and / or longer) than the second substrate 24 so that the first substrate 12 is second as shown in FIG. It means to spread out from the substrate 24. By connecting a pad or contact 34 on the upper surface or second surface of the first substrate 12 to a pad or contact 34 on the upper surface or second surface of the second substrate 24, Electrical connection is made between the two substrates. These connections can be made by wire bonds 26. Since the contacts 34 on the first substrate are located on a region of the first substrate 12 that extends out of the second substrate 24, the bond connection between them can be made using existing techniques. . Pads or contacts 34 and 38 are shown disproportionately enlarged in FIG.

第２の基板２４の上のコンタクトと第２のダイ２２の活性面上の端子との間で、電気的接続が行われる。図１に示されるように、第２の基板２４は、貫通する開口または溝１４を有する。したがって、ワイヤボンド２６または他の接続要素が開口１４を通って延びて、第２の基板２４と第２のダイ２２の間の接続を行うことができる。第２のダイ２２に対するワイヤボンド手順は、第１のダイ１８に対するワイヤボンド手順と比べると逆であり、したがって、ピンアサインは、ボールピン配列に相当する。   Electrical connections are made between contacts on the second substrate 24 and terminals on the active surface of the second die 22. As shown in FIG. 1, the second substrate 24 has an opening or groove 14 therethrough. Thus, a wire bond 26 or other connecting element can extend through the opening 14 to provide a connection between the second substrate 24 and the second die 22. The wire bond procedure for the second die 22 is the opposite as compared to the wire bond procedure for the first die 18, and thus the pin assignment corresponds to a ball pin arrangement.

第１の基板１２と第１のダイ１８上の端子との間の電気的接続も、同じ方法で行うことができる。図１に示されるパッケージ１０は、左右対称とすることができる。ダイ１８および２２は、同じ幅または長さを有するものとして示されるが、ダイは、同じでもよく、あるいは電気的および／または機械的に互いに異なってもよい。基板１２および２４は、ダイを保持し、かつ電気的相互接続を可能にするために、プリント回路板または他のタイプの基板とすることができる。基板上のパッド１３４は一般に、同等のまたは対応する配列の電気的結合部（例えば、はんだボールまたは他のはんだ要素）を受けるように、アレイ状に配置される。第１のダイ１８および第１の基板１２は、ボードオンチップ構造を形成する。同様に、第２のダイ２２および第２の基板２２もまた、ボードオンチップ構造を形成する。   The electrical connection between the first substrate 12 and the terminals on the first die 18 can also be made in the same way. The package 10 shown in FIG. 1 can be symmetrical. Although dies 18 and 22 are shown as having the same width or length, the dies may be the same or may be electrically and / or mechanically different from each other. Substrates 12 and 24 can be printed circuit boards or other types of substrates to hold the dies and allow electrical interconnection. The pads 134 on the substrate are generally arranged in an array to receive an equivalent or corresponding arrangement of electrical couplings (eg, solder balls or other solder elements). The first die 18 and the first substrate 12 form a board-on-chip structure. Similarly, the second die 22 and the second substrate 22 also form a board on chip structure.

ワイヤボンド接続２６が行われた後、モールドコンパウンド２８が、図１に示される各領域内のワイヤボンド２６を覆うように塗布される。ワイヤボンド２６と、基板の内端または外端に隣接するコンタクト３４と、それらが接続する対象であるダイ上の端子とが、モールドコンパウンド２８で覆われる。ダイ１８および２２のすべての面を、基板およびモールドコンパウンドで完全に密封する、または覆うことができる。第１の基板１２の下側は、開口１４でのワイヤボンドを除いて、モールドコンパウンド２８で覆われていないことが有利である。第２の基板２４上のワイヤボンドコンタクト３４間に位置する露出コンタクト３８は、モールドコンパウンドで覆われない。これにより、パッケージ１０上に積み重ねられる他のパッケージとの電気的接続を行う際に使用するために、第１の基板の下面上の露出コンタクト３８を覆われないままにしておく。   After the wire bond connection 26 is made, a mold compound 28 is applied over the wire bond 26 in each region shown in FIG. Wire bonds 26, contacts 34 adjacent to the inner or outer edge of the substrate, and terminals on the die to which they are connected are covered with mold compound 28. All faces of dies 18 and 22 can be completely sealed or covered with a substrate and mold compound. Advantageously, the underside of the first substrate 12 is not covered by the mold compound 28 except for wire bonds at the openings 14. The exposed contacts 38 located between the wire bond contacts 34 on the second substrate 24 are not covered with mold compound. This leaves the exposed contact 38 on the lower surface of the first substrate uncovered for use in making electrical connections with other packages stacked on the package 10.

次いで、すべてのコンタクトおよび端子は、依然として試験装置によってアクセス可能であるので、パッケージ１０を試験することができる。これにより、パッケージの積重ねアセンブリへの最終組立ての前に、欠陥パッケージを検出し除去することが可能になる。したがって、積重ねアセンブリは、既知の良好なアセンブリパッケージで製作することができる。これは、製造時の歩留りを改善する。   All contacts and terminals are then still accessible by the test equipment so that the package 10 can be tested. This allows defective packages to be detected and removed prior to final assembly into a package stack assembly. Thus, the stack assembly can be made in a known good assembly package. This improves the yield during manufacturing.

パッケージ１０が回路板または他の上位アセンブリに取り付けられる用途では、パッケージ１０は、図１の向きに、すなわち第１の基板１２が回路板上にある状態で、取り付けることができる。次いで、露出コンタクト３８が回路板上のコンタクト、パッドまたは端子に連接することにより、パッケージ１０と回路板との間で電気的接続を行うことができる。これらの接続を行うために、リフローはんだボール１６を使用することができる。パッケージ上１０に追加のパッケージが積み重ねられない場合、回路板への接続は、代替的または付加的に、第２の基板２４上の露出コンタクト３８を介して行うことができる。図２に示されるように、１つ以上の追加のパッケージがパッケージ１０上に積み重ねられる場合、回路板への接続は、代替的または付加的に、スタックの最上部のパッケージ上の露出コンタクトがあればそれを介して行うことができる。   In applications where the package 10 is attached to a circuit board or other upper assembly, the package 10 can be attached in the orientation of FIG. 1, i.e., with the first substrate 12 on the circuit board. The exposed contact 38 is then connected to a contact, pad or terminal on the circuit board so that electrical connection can be made between the package 10 and the circuit board. Reflow solder balls 16 can be used to make these connections. If no additional packages are stacked on the package 10, the connection to the circuit board can alternatively or additionally be made via exposed contacts 38 on the second substrate 24. As shown in FIG. 2, when one or more additional packages are stacked on the package 10, the connection to the circuit board may alternatively or additionally be exposed contacts on the top package of the stack. Can be done through it.

図２は、第１のパッケージ１０の上に積み重ねられる第２のパッケージ１０を示す。２
つの積み重ねられるパッケージの間の電気的接続を行うために、はんだボールまたは要素１６をランドグリッドアレイ上で使用することができる。さらに、上部パッケージの第１の基板１２と下部パッケージ上のモールドコンパウンド２８との間、および／または積重ねアセンブリ３６の中心に示される隣接するモールドコンパウンド突出部４４相互間で、パッケージ１０の機械的取付けを接着剤で行うことができる。第２のパッケージは、相互間で必要な電気的接続を行うことができるのであれば、第１のパッケージと電気的かつ機械的に同じでも異なっていてもよい。図２は、２つのパッケージ１０を有する積重ねアセンブリ３６を示すが、もちろん、積重ねアセンブリ３６は、例えば３つ、４つ、５つまたはそれ以上のパッケージを有することもできる。 FIG. 2 shows the second package 10 stacked on the first package 10. 2
Solder balls or elements 16 can be used on the land grid array to make electrical connections between the two stacked packages. Further, the mechanical attachment of the package 10 between the first substrate 12 of the upper package and the mold compound 28 on the lower package and / or between adjacent mold compound protrusions 44 shown in the center of the stack assembly 36. Can be performed with an adhesive. The second package may be the same as or different from the first package electrically and mechanically as long as the necessary electrical connection can be made between them. Although FIG. 2 shows a stack assembly 36 having two packages 10, of course, the stack assembly 36 may have, for example, three, four, five, or more packages.

図３は、他の実施形態４８を示し、第１の基板５２上の第１のダイ１８が、チップオンボード構造を形成する。図１に示される第１の基板１２とは異なり、図３内の第１の基板５２は、開口または溝を有さない。スペーサまたはエポキシパッド５０が、第１のダイ１８上に設けられる。第２のダイ２２が、スペーサ５０上に設けられる。これらのダイは、接着剤２０によってスペーサに取り付けることができる。第２のダイ２２に第２の基板２４が取り付けられて、図１内の第２のダイおよび第２の基板に類似のボードオンチップ構造を形成する。スペーサ５０は、第１のダイ１８の活性面の上に空間をもたらして、第１のダイ１８と第１の基板５２との間でワイヤボンディングまたは同様の接続を行うことが可能になる。   FIG. 3 shows another embodiment 48 in which the first die 18 on the first substrate 52 forms a chip-on-board structure. Unlike the first substrate 12 shown in FIG. 1, the first substrate 52 in FIG. 3 does not have openings or grooves. A spacer or epoxy pad 50 is provided on the first die 18. A second die 22 is provided on the spacer 50. These dies can be attached to the spacer by an adhesive 20. A second substrate 24 is attached to the second die 22 to form a board-on-chip structure similar to the second die and the second substrate in FIG. The spacer 50 provides a space above the active surface of the first die 18 to allow wire bonding or similar connection between the first die 18 and the first substrate 52.

第２のダイ２２が第１のダイ１８よりも小さい場合、スペーサ５０は、ワイヤボンディングのために必要ないので、省略することができる。この場合、第２のダイ２２は、図１と同様に、第１のダイ１８に直接取り付けることができる。第１および第２のダイの間の接続は、第２の基板のボンドフィンガから第１の基板のボンドフィンガまでの周辺ワイヤボンディングによって行うことができる。第２の基板２４と第２のダイ２２との間、および第２の基板２４と第１の基板との間のワイヤボンディングまたは他の電気的接続、ならびにモールドコンパウンド２８は、上述したように、図１と同じように行う、または使用することができる。図３に示されるパッケージ４８は、追加の他のマイクロ電子パッケージ（パッケージ４８と同じでも異なっていてもよい）の上に積み重ねられて、図２に示される概念と同様の積重ねアセンブリ３６を形成することができる。   If the second die 22 is smaller than the first die 18, the spacer 50 is not necessary for wire bonding and can be omitted. In this case, the second die 22 can be directly attached to the first die 18 as in FIG. The connection between the first and second dies can be made by peripheral wire bonding from the bond finger of the second substrate to the bond finger of the first substrate. Wire bonding or other electrical connection between the second substrate 24 and the second die 22, and between the second substrate 24 and the first substrate, and the mold compound 28, as described above, It can be performed or used in the same way as in FIG. The package 48 shown in FIG. 3 is stacked on top of another additional microelectronic package (which may be the same as or different from the package 48) to form a stack assembly 36 similar to the concept shown in FIG. be able to.

図４は、図３に示す設計とほぼ同様であるが、第１のダイ６０がフリップチップパッケージ構造である、他の実施形態５８を示す。第１のダイ６０は、活性面を下にして第１の基板５２に取り付けられる。第１のダイ６０と第１の基板５２との間の電気的接続は、下向きの活性面上の導電性バンプまたは電気的結合部を介して行われる。バンプは、第１の基板５２上の目標パッドまたはコンタクトと一致しかつ接触する。第２のダイ２２の裏面は、第１のダイ６０の裏面に取り付けられる。第２の基板２４は、第２のダイ２２の活性面の上に取り付けられて、ボードオンチップ構造を形成する。第２のダイ２２と第２の基板２４との間、および第１の基板５２と第２の基板２４との間の電気的接続、ならびにモールドコンパウンド２８は、図１または３を参照して上述したのと同じように行うことができる。パッケージ５８は、図１〜３に関連して上述したように、積み重ねられて、複数パッケージの積重ねアセンブリ３６を形成することができる。   FIG. 4 shows another embodiment 58 that is similar to the design shown in FIG. 3, but in which the first die 60 is a flip chip package structure. The first die 60 is attached to the first substrate 52 with the active surface down. The electrical connection between the first die 60 and the first substrate 52 is made through conductive bumps or electrical couplings on the downward active surface. The bump coincides with and contacts the target pad or contact on the first substrate 52. The back surface of the second die 22 is attached to the back surface of the first die 60. The second substrate 24 is mounted on the active surface of the second die 22 to form a board on chip structure. The electrical connection between the second die 22 and the second substrate 24, and between the first substrate 52 and the second substrate 24, and the mold compound 28 are described above with reference to FIG. You can do it as you did. The packages 58 can be stacked to form a multi-package stack assembly 36 as described above in connection with FIGS.

図５は、図４に示す設計とほぼ同様であるが、フリップチップを小さい方の基板７４に取り付けられる第２のダイ６０として用いた、他の実施形態６８を示す。第１のダイ７２が、ボードオンチップ構造の形で第１の基板７０に取り付けられる。第２のダイ６０は、接着剤２０を用いて、第１のダイ７２の上に背中合わせに取り付けることができる。第２の基板７４は、第２のダイ６０に取り付けられる。第２のダイ６０はフリップチップであるので、図４内の第１のダイ６０を参照して上述したように、電気的接続が、第２のダイと第２の基板との間で第２のダイ上のバンプを介して行われる。第２のダイ６０に取り付
けられる第２の基板７４は、第１の基板７０よりも小さい。第１および第２の基板の間、および第１のダイ７２と第１の基板７０との間の電気的接続は、ワイヤボンド２６を介して行うことができる。 FIG. 5 shows another embodiment 68 that is similar to the design shown in FIG. 4 but uses a flip chip as the second die 60 attached to the smaller substrate 74. A first die 72 is attached to the first substrate 70 in the form of a board-on-chip structure. The second die 60 can be attached back to back on the first die 72 using the adhesive 20. The second substrate 74 is attached to the second die 60. Since the second die 60 is a flip chip, the electrical connection is second between the second die and the second substrate as described above with reference to the first die 60 in FIG. This is done via bumps on the die. The second substrate 74 attached to the second die 60 is smaller than the first substrate 70. Electrical connections between the first and second substrates and between the first die 72 and the first substrate 70 can be made via wire bonds 26.

上述の設計は、同一平面性の問題を（ダイが背中合わせになっているため）回避すること、既存の設備を用いてアセンブリが可能であること、第１および第２の基板が、業界標準（ＪＥＤＥＣ）に適合するボールピン配列のアサインを有することができること、構成要素を、最終アセンブリの前に個別に試験することができること、より薄いパッケージ高さを達成できること、などの利点を提供することができる。もちろん、様々な実施形態を用いて様々な方法で本発明を実施して、これらの利点それぞれを実現する場合もあり、そうでない場合もある。本発明は、それぞれの利点をかならずしも達成することなく使用することもできる。   The above design avoids coplanarity issues (because the dies are back to back), allows assembly using existing equipment, and the first and second substrates are industry standard ( Providing advantages such as being able to have ball pin array assignments that conform to JEDEC), components can be individually tested prior to final assembly, thinner package heights can be achieved, etc. it can. Of course, the present invention may be implemented in various ways using various embodiments to achieve each of these advantages, or not. The present invention can also be used without necessarily achieving the respective advantages.

パッド、コンタクト、端子、バンプ、電気的結合部などの用語は、電気的な接続を行うために用いられる特徴を制限なしに表現するためのものであり、特定の排他的な意味を有するものではない。本明細書で用いられているような、取り付けられる（ａｔｔａｃｈｅｄ）という用語は、直接間接を問わず、接合される、接着される、連接される、ボンディングされる、あるいはその他の方法で支持されることを意味する。基板という用語は、ここではダイが取り付けられる要素または基部を意味し、基板は、典型的には回路板を含むが、それに限らない。間（ｂｅｔｗｅｅｎ）という用語は、周辺ワイヤボンディングと同様に、第１の要素と第２の要素との間の直接接続を意味するが、他のタイプの直接的または間接的電気的接続も含む。   Terms such as pads, contacts, terminals, bumps, electrical couplings, etc. are meant to express the characteristics used to make the electrical connection without limitation, and have no specific exclusive meaning. Absent. As used herein, the term attached is used directly or indirectly to be joined, glued, articulated, bonded, or otherwise supported. Means that. The term substrate here refers to the element or base to which the die is attached, and the substrate typically includes, but is not limited to, a circuit board. The term between, like peripheral wire bonding, means a direct connection between a first element and a second element, but also includes other types of direct or indirect electrical connections.

したがって、いくつかの実施形態、およびそれらを製作する方法について示し、説明してきた。本発明の精神および範囲から逸脱することなく、様々な変更および置換を行うことができる。したがって、本発明は、特許請求の範囲とその同等物による以外は限定されるべきでない。   Accordingly, several embodiments and methods for making them have been shown and described. Various changes and substitutions can be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited except as by the appended claims and their equivalents.

積み重ね可能なマイクロ電子マルチダイパッケージの概略断面図である。1 is a schematic cross-sectional view of a stackable microelectronic multi-die package. 図１に示される２つのパッケージが、積重ねアセンブリを形成するように互いに取り付けられるものの概略断面図である。FIG. 2 is a schematic cross-sectional view of the two packages shown in FIG. 1 being attached together to form a stack assembly. 他の積み重ね可能なマルチダイパッケージの概略断面図である。FIG. 6 is a schematic cross-sectional view of another stackable multi-die package. 他の積み重ね可能なマルチダイパッケージの概略断面図である。FIG. 6 is a schematic cross-sectional view of another stackable multi-die package. さらに他の積み重ね可能なマルチダイパッケージの概略断面図である。FIG. 6 is a schematic cross-sectional view of still another stackable multi-die package.

Claims (62)

第１の基板と、
前記第１の基板と電気的に接続する第１のマイクロ電子ダイと、
前記第１の基板と電気的に接続する第２の基板と、
前記第２の基板と電気的に接続する第２のマイクロ電子ダイと
を含むマイクロ電子パッケージ。 A first substrate;
A first microelectronic die electrically connected to the first substrate;
A second substrate electrically connected to the first substrate;
A microelectronic package comprising a second microelectronic die electrically connected to the second substrate. 前記第１の基板の第２の面を前記第２の基板の第２の面に接続する第１の組のワイヤと、前記第１の基板の第１の面を前記第１のマイクロ電子ダイの中心領域に接続する第２の組又はワイヤと、前記第２の基板の第２の面を前記第２のマイクロ電子ダイに接続する第３の組のワイヤとをさらに含む、請求項１に記載のマイクロ電子パッケージ。   A first set of wires connecting a second surface of the first substrate to a second surface of the second substrate; and a first surface of the first substrate as the first microelectronic die. 2 further comprising a second set or wires connecting to a central region of the first substrate and a third set of wires connecting a second surface of the second substrate to the second microelectronic die. The described microelectronic package. 前記第１の基板が、前記第２の基板よりも大きい、請求項１に記載のマイクロ電子パッケージ。   The microelectronic package of claim 1, wherein the first substrate is larger than the second substrate. 前記第１の基板が、前記第２の基板にワイヤボンディングによって電気的に接続する、請求項３に記載のマイクロ電子パッケージ。   The microelectronic package of claim 3, wherein the first substrate is electrically connected to the second substrate by wire bonding. 前記第１のマイクロ電子ダイが、ボードオンチップパッケージ構造を含む、請求項１に記載のマイクロ電子パッケージ。   The microelectronic package of claim 1, wherein the first microelectronic die includes a board-on-chip package structure. 前記第２のマイクロ電子ダイが、ボードオンチップパッケージ構造を含む、請求項１に記載のマイクロ電子パッケージ。   The microelectronic package of claim 1, wherein the second microelectronic die includes a board on chip package structure. 前記第２の基板が、２つ以上のパッケージアセンブリからなる積重ねアセンブリを可能にするために、露出する電気コンタクトのグリッドアレイを有する、請求項１に記載のマイクロ電子パッケージ。   The microelectronic package of claim 1, wherein the second substrate has a grid array of exposed electrical contacts to allow a stacked assembly of two or more package assemblies. 前記第１および第２のマイクロ電子ダイがそれぞれ、複数の活性端子を含む活性面と、裏面とを含み、前記第１のマイクロ電子ダイの前記裏面が、前記第２のマイクロ電子ダイの前記裏面に取り付けられる、請求項１に記載のマイクロ電子パッケージ。   Each of the first and second microelectronic dies includes an active surface including a plurality of active terminals and a back surface, and the back surface of the first microelectronic die is the back surface of the second microelectronic die. The microelectronic package of claim 1, attached to the microelectronic package. 前記第１の基板が第１の面および第２の面を有し、前記第２の面が前記第１のマイクロ電子ダイに隣接し、前記基板の前記第１の面が複数のコンタクトを有し、前記第１の基板が貫通開口部を有し、前記基板の前記第１の面上の前記複数のコンタクトから前記第１のマイクロ電子ダイまで延びるワイヤをさらに含む、請求項１に記載のマイクロ電子パッケージ。   The first substrate has a first surface and a second surface, the second surface is adjacent to the first microelectronic die, and the first surface of the substrate has a plurality of contacts. The first substrate further comprising a wire having a through opening and extending from the plurality of contacts on the first surface of the substrate to the first microelectronic die. Micro electronic package. 前記第２の基板が第１の面および第２の面を有し、前記第１の面が前記第２のマイクロ電子ダイに隣接し、前記第２の基板が貫通開口部を有し、前記第２のダイ上の複数のコンタクトから前記第２の基板の前記第２の面まで延びるワイヤをさらに含む、請求項９に記載のマイクロ電子パッケージ。   The second substrate has a first surface and a second surface; the first surface is adjacent to the second microelectronic die; the second substrate has a through opening; The microelectronic package of claim 9, further comprising a wire extending from a plurality of contacts on a second die to the second surface of the second substrate. 前記第１、第２および第３の組のワイヤを封止するモールドコンパウンドをさらに含む、請求項２に記載のマイクロ電子パッケージ。   The microelectronic package of claim 2, further comprising a mold compound that seals the first, second, and third sets of wires. 前記第１のダイが前記第１の基板に隣接し、前記第２のダイが前記第２の基板に隣接し、前記第１のダイが前記第２のダイに隣接する、請求項１に記載のマイクロ電子パッケージ。   The first die is adjacent to the first substrate, the second die is adjacent to the second substrate, and the first die is adjacent to the second die. Micro electronic package. 前記第１のダイが、前記第１の基板の第２の面と接触する、前記第１のダイの活性面上の複数の電気端子を介して、前記第１のダイに電気的に接続される、請求項１に記載のマイクロ電子パッケージ。   The first die is electrically connected to the first die via a plurality of electrical terminals on the active surface of the first die that contact a second surface of the first substrate. The microelectronic package according to claim 1. 第１の基板と、
前記第１の基板と電気的に接続する第１のマイクロ電子ダイと、
前記第１の基板と電気的に接続する第２の基板と、
前記第２の基板と電気的に接続する第２のマイクロ電子ダイと
を含む
第１のマイクロ電子パッケージ、ならびに
第３の基板と、
前記第３の基板と電気的に接続する第３のマイクロ電子ダイと、
前記第２および第３の基板の間の複数の電気接続部と
を含む第２のマイクロ電子パッケージ
を含む、積重ね型マイクロ電子パッケージアセンブリ。 A first substrate;
A first microelectronic die electrically connected to the first substrate;
A second substrate electrically connected to the first substrate;
A first microelectronic package comprising: a second microelectronic die electrically connected to the second substrate; and a third substrate;
A third microelectronic die electrically connected to the third substrate;
A stacked microelectronic package assembly comprising a second microelectronic package including a plurality of electrical connections between the second and third substrates. 前記第１のマイクロ電子パッケージアセンブリに付随する第１、第２および第３の組のワイヤであって、前記第１の組のワイヤが、前記第１の基板の第２の面を前記第２の基板の第２の面に接続し、前記第２の組又はワイヤが、前記第１の基板の第１の面を前記第１のマイクロ電子ダイの中心領域に接続し、前記第３の組のワイヤが、前記第２の基板の前記第２の面を前記第２のマイクロ電子ダイに接続する、第１、第２および第３の組のワイヤと、
前記第３の基板と電気的に接続する第４の基板と、
前記第２のマイクロ電子パッケージアセンブリに付随する第４、第５および第６の組のワイヤであって、前記第４の組のワイヤが、前記第３の基板の第２の面を前記第４の基板の第２の面に接続し、前記第５の組又はワイヤが、前記第３の基板の第１の面を前記第３のマイクロ電子ダイの中心領域に接続し、前記第６の組のワイヤが、前記第４の基板の前記第２の面を前記第４のマイクロ電子ダイに接続する、第４、第５および第６の組のワイヤと
をさらに含む、請求項１４に記載の積重ね型マイクロ電子パッケージアセンブリ。 A first, second and third set of wires associated with the first microelectronic package assembly, wherein the first set of wires extends the second surface of the first substrate to the second. The second set or wire connects the first side of the first substrate to a central region of the first microelectronic die, and the third set. First, second and third sets of wires connecting the second surface of the second substrate to the second microelectronic die; and
A fourth substrate electrically connected to the third substrate;
A fourth, fifth and sixth set of wires associated with the second microelectronic package assembly, wherein the fourth set of wires extends the second surface of the third substrate to the fourth. The fifth set or wire connects the first side of the third substrate to the central region of the third microelectronic die and connects to the second side of the third substrate. 15. The wire of claim 14, further comprising a fourth, fifth, and sixth set of wires that connect the second surface of the fourth substrate to the fourth microelectronic die. Stacked microelectronic package assembly. 前記第１および第２のマイクロ電子パッケージアセンブリの間の前記複数の電気接続部が、前記第２および第３の基板の間にはんだボールを含む、請求項１４に記載の積重ね型マイクロ電子パッケージアセンブリ。   The stacked microelectronic package assembly of claim 14, wherein the plurality of electrical connections between the first and second microelectronic package assemblies include solder balls between the second and third substrates. . 前記第１の基板が、前記第２の基板よりも大きい、請求項１４に記載の積重ね型マイクロ電子パッケージアセンブリ。   The stacked microelectronic package assembly of claim 14, wherein the first substrate is larger than the second substrate. 第１の基板上の第１のダイと、
第２のダイ上の第２の基板と、
前記第１および第２のダイの間のスペーサと、
前記第１のダイを前記第１の基板に接続する第１の組のワイヤと、
前記第２の基板を前記第１の基板に接続する第２の組のワイヤと
を含む、積み重ね可能なマルチ電子ダイパッケージ。 A first die on a first substrate;
A second substrate on a second die;
A spacer between the first and second dies;
A first set of wires connecting the first die to the first substrate;
A stackable multi-electronic die package comprising a second set of wires connecting the second substrate to the first substrate. 前記第２のダイを、前記第２の基板内の開口を通って前記第２の基板に接続する第３の組のワイヤをさらに含む、請求項１８に記載の積み重ね可能なマルチ電子ダイパッケージ。   19. The stackable multi-electronic die package of claim 18, further comprising a third set of wires connecting the second die to the second substrate through an opening in the second substrate. 前記第１のダイおよび第１の基板が、チップオンボードパッケージ構造を含み、前記第２のダイおよび第２の基板が、ボードオンチップパッケージ構造を含む、請求項１８に記載の積み重ね可能なマルチ電子ダイパッケージ。   19. The stackable multi of claim 18, wherein the first die and first substrate comprise a chip on board package structure, and the second die and second substrate comprise a board on chip package structure. Electronic die package. 前記第１の基板が、前記第２の基板よりも大きい、請求項１８に記載の積み重ね可能なマルチ電子ダイパッケージ。   The stackable multi-electronic die package of claim 18, wherein the first substrate is larger than the second substrate. 第１の基板と、
前記第１の基板と電気的に接続する、前記第１の基板上の第１のダイと、
前記第１のダイの上に取り付けられる第２のダイと、
前記第２のダイ上の第２の基板と、
前記第１の基板を前記第２の基板に接続する第１の組のワイヤと、
前記第２の基板を前記第２のダイに接続する第２の組のワイヤと
を含む、積み重ね可能なマルチ電子ダイパッケージ。 A first substrate;
A first die on the first substrate in electrical connection with the first substrate;
A second die mounted on the first die;
A second substrate on the second die;
A first set of wires connecting the first substrate to the second substrate;
A stackable multi-electronic die package including a second set of wires connecting the second substrate to the second die. 前記第１の基板および前記第１のダイが、フリップチップパッケージ構造を形成し、前記第２の基板および前記第２のダイが、ボードオンチップパッケージ構造を形成する、請求項２２に記載の積み重ね可能なマルチ電子ダイパッケージ。   23. The stack of claim 22, wherein the first substrate and the first die form a flip chip package structure, and the second substrate and the second die form a board on chip package structure. Possible multi-electronic die package. 前記第１の基板の上に積み重ねられるダイパッケージの基板と電気的に接続するように構成された、前記第１の基板の第１の面上の第１のコンタクト配列をさらに含む、請求項２２に記載の積み重ね可能なマルチ電子ダイパッケージ。   23. The method further comprises a first contact arrangement on a first surface of the first substrate configured to be electrically connected to a substrate of a die package that is stacked on the first substrate. Stackable multi-electronic die package as described in. 前記第１の組のワイヤが、前記第１の基板の第２の面を前記第２の基板の第２の面に接続する、請求項２４に記載の積み重ね可能なマルチ電子ダイパッケージ。   25. The stackable multi-electronic die package of claim 24, wherein the first set of wires connects a second surface of the first substrate to a second surface of the second substrate. 前記第１の基板が、前記第２の基板よりも大きい、請求項２２に記載の積み重ね可能なマルチ電子ダイパッケージ。   The stackable multi-electronic die package of claim 22, wherein the first substrate is larger than the second substrate. 前記第２の基板が、前記第１の基板よりも大きい、請求項２２に記載の積み重ね可能なマルチ電子ダイパッケージ。   23. The stackable multi-electronic die package of claim 22, wherein the second substrate is larger than the first substrate. 前記第１および第２の基板の少なくとも一部を覆うケーシングをさらに含む、請求項２２に記載の積み重ね可能なマルチ電子ダイパッケージ。   The stackable multi-electronic die package of claim 22, further comprising a casing covering at least a portion of the first and second substrates. 前記ケーシングが、他のパッケージの基板と接続するように構成された電気コンタクトを有する前記第２の基板の領域を露出させる開口を有する、請求項２８に記載の積み重ね可能なマルチ電子ダイパッケージ。   29. The stackable multi-electronic die package of claim 28, wherein the casing has an opening exposing an area of the second substrate having electrical contacts configured to connect with substrates of other packages. 前記第１および第２の組のワイヤが、ワイヤボンドを含む、請求項２２に記載の積み重ね可能なマルチ電子ダイパッケージ。   23. The stackable multi-electronic die package of claim 22, wherein the first and second sets of wires comprise wire bonds. マイクロ電子パッケージを製造する方法であって、
第１のダイを第１の基板に取り付けるステップと、
第２のダイを前記第１のダイに取り付けるステップと、
第２の基板を前記第２のダイに取り付けるステップと、
前記第１の基板と前記第２の基板との間の第１の組の電気的接続を行うステップと、
前記第１のダイと前記第１の基板との間の第２の組の電気的接続を行うステップと、
前記第２のダイと前記第２の基板との間の第３の組の電気的接続を行うステップと
を含む方法。 A method of manufacturing a microelectronic package comprising:
Attaching a first die to a first substrate;
Attaching a second die to the first die;
Attaching a second substrate to the second die;
Making a first set of electrical connections between the first substrate and the second substrate;
Making a second set of electrical connections between the first die and the first substrate;
Making a third set of electrical connections between the second die and the second substrate. 前記第１、第２および第３の組の電気的接続が、ワイヤボンド接続である、請求項３１に記載の方法。   32. The method of claim 31, wherein the first, second and third sets of electrical connections are wire bond connections. 前記第２の組の電気的接続が、前記第１の基板内の開口を通って延びるワイヤによって行われる、請求項３１に記載の方法。   32. The method of claim 31, wherein the second set of electrical connections is made by wires extending through openings in the first substrate. 前記第３の組の電気的接続が、前記第２の基板内の開口を通って延びるワイヤによって行われる、請求項３３に記載の方法。   34. The method of claim 33, wherein the third set of electrical connections is made by wires extending through openings in the second substrate. 前記第１、第２および第３の組の電気的接続をモールドコンパウンド内に密封するステップをさらに含む、請求項３２に記載の方法。   35. The method of claim 32, further comprising sealing the first, second and third sets of electrical connections in a mold compound. 前記第１の組のワイヤボンドが、前記第１の基板の第２の面上のコンタクトを、前記第２の基板の第２の面上のコンタクトに接続する、請求項３２に記載の方法。   35. The method of claim 32, wherein the first set of wire bonds connect contacts on a second surface of the first substrate to contacts on a second surface of the second substrate. 前記第２の組のワイヤボンドが、前記第１の基板の第１の面上のコンタクトを、前記第１のダイの第１の面上の端子に接続する、請求項３２に記載の方法。   35. The method of claim 32, wherein the second set of wire bonds connect contacts on the first surface of the first substrate to terminals on the first surface of the first die. 前記第３の組のワイヤボンドが、前記基板の第２の面上のコンタクトを、前記第２のダイの第２の面上のコンタクトに接続する、請求項３２に記載の方法。   35. The method of claim 32, wherein the third set of wire bonds connects contacts on the second side of the substrate to contacts on the second side of the second die. 前記第１の基板が、前記第２の基板よりも大きい、請求項３１に記載の方法。   32. The method of claim 31, wherein the first substrate is larger than the second substrate. 前記第１のダイが、ボードオンチップパッケージ構造を含む、請求項３１に記載の方法。   32. The method of claim 31, wherein the first die comprises a board on chip package structure. 前記第２のマイクロ電子ダイが、ボードオンチップパッケージ構造を含む、請求項３１に記載の方法。   32. The method of claim 31, wherein the second microelectronic die comprises a board on chip package structure. 前記マイクロ電子パッケージを他のマイクロ電子パッケージ上に積み重ねることができるようにするために、前記モールドコンパウンドを前記第２の基板の各領域から除外して、電気コンタクトのグリッドアレイを露出したままにするステップをさらに含む、請求項３５に記載の方法。   In order to allow the microelectronic package to be stacked on top of another microelectronic package, the mold compound is excluded from each region of the second substrate, leaving the grid array of electrical contacts exposed. 36. The method of claim 35, further comprising a step. 前記マイクロ電子パッケージを他のマイクロ電子パッケージ上に積み重ねることができるようにするために、前記モールドコンパウンドを前記第１の基板の各領域から除外して、電気コンタクトのグリッドアレイを露出したままにするステップをさらに含む、請求項３５に記載の方法。   In order to allow the microelectronic package to be stacked on top of another microelectronic package, the mold compound is excluded from each region of the first substrate, leaving the grid array of electrical contacts exposed. 36. The method of claim 35, further comprising a step. 前記第１のダイの裏面を接着剤によって前記第２のダイの裏面に取り付けるステップをさらに含む、請求項３１に記載の方法。   32. The method of claim 31, further comprising attaching the back surface of the first die to the back surface of the second die with an adhesive. 積重ね型マイクロ電子パッケージアセンブリを製造する方法であって、
第１のダイを第１の基板に取り付けるステップと、
第２のダイを前記第１のダイに取り付けるステップと、
第２の基板を前記第２のダイに取り付けるステップと、
前記第１の基板と前記第２の基板との間の第１の組の電気的接続を行うステップと、
前記第１のダイと前記第１の基板との間の第２の組の電気的接続を行うステップと、
前記第２のダイと前記第２の基板との間の第３の組の電気的接続を行うステップと
によって第１のマイクロ電子パッケージを製作するステップ、ならびに
第２のマイクロ電子パッケージを前記第１のマイクロ電子パッケージアセンブリに取り付けるステップ
を含む方法。 A method of manufacturing a stacked microelectronic package assembly comprising:
Attaching a first die to a first substrate;
Attaching a second die to the first die;
Attaching a second substrate to the second die;
Making a first set of electrical connections between the first substrate and the second substrate;
Making a second set of electrical connections between the first die and the first substrate;
Making a third set of electrical connections between the second die and the second substrate, and making a second microelectronic package the first microelectronic package. Attaching to a microelectronic package assembly. 前記第２のマイクロ電子パッケージのコンタクトを前記第１の基板上のコンタクトに接続することによって、前記第１および第２のマイクロ電子パッケージの間の電気的接続を行うステップをさらに含む、請求項４５に記載の方法。   46. The method further comprises making an electrical connection between the first and second microelectronic packages by connecting a contact of the second microelectronic package to a contact on the first substrate. The method described in 1. 前記第１および第２のマイクロ電子パッケージの間の電気的接続をはんだ要素によって行うステップをさらに含む、請求項４６に記載の方法。   47. The method of claim 46, further comprising the step of making an electrical connection between the first and second microelectronic packages with a solder element. 前記第２のマイクロ電子パッケージを前記第１のマイクロ電子パッケージに取り付ける前に、前記第１および第２のマイクロ電子パッケージの少なくとも一方を試験するステップをさらに含む、請求項４５に記載の方法。   46. The method of claim 45, further comprising testing at least one of the first and second microelectronic packages before attaching the second microelectronic package to the first microelectronic package. 前記第２の組の電気的接続が、前記第１の基板内の開口を通って延びるワイヤボンドによって行われる、請求項４５に記載の方法。   46. The method of claim 45, wherein the second set of electrical connections is made by wire bonds extending through openings in the first substrate. 前記第３の組の電気的接続が、前記第２の基板内の開口を通って延びるワイヤボンドによって行われる、請求項４５に記載の方法。   46. The method of claim 45, wherein the third set of electrical connections is made by wire bonds extending through openings in the second substrate. 前記第２のマイクロ電子パッケージアセンブリを前記第１のマイクロ電子パッケージに取り付ける前に、前記第１、第２および第３の組の電気的接続をモールドコンパウンド内に密封するステップをさらに含む、請求項４５に記載の方法。   The method further comprises sealing the first, second and third sets of electrical connections in a mold compound prior to attaching the second microelectronic package assembly to the first microelectronic package. 45. The method according to 45. 前記第１の基板が前記第２の基板よりも大きく、前記第１の組の電気的接続を、前記第１の基板の第２の面のコンタクトを前記第２の基板の第２の面上のコンタクトにワイヤボンディングすることによって行うステップをさらに含む、請求項４５に記載の方法。   The first substrate is larger than the second substrate, the first set of electrical connections, the second surface contact of the first substrate on the second surface of the second substrate. 46. The method of claim 45, further comprising performing by wire bonding to the contacts. 第３のマイクロ電子パッケージを前記第１のマイクロ電子パッケージに取り付けるステップと、前記第３のマイクロ電子パッケージのコンタクトを前記第２の基板上のコンタクトに接続することによって、前記第１および第３のマイクロ電子パッケージの間の電気的接続を行うステップとをさらに含む、請求項４６に記載の方法。   Attaching a third microelectronic package to the first microelectronic package; and connecting a contact of the third microelectronic package to a contact on the second substrate; 47. The method of claim 46, further comprising the step of making an electrical connection between the microelectronic packages. 前記第１の基板上の前記コンタクトが、前記第１の基板の縁部から離れて配置される、請求項４６に記載の方法。   47. The method of claim 46, wherein the contact on the first substrate is disposed away from an edge of the first substrate. 前記第２のマイクロ電子パッケージが、前記第１のマイクロ電子パッケージアセンブリと同じである、請求項４５に記載の方法。   46. The method of claim 45, wherein the second microelectronic package is the same as the first microelectronic package assembly. マイクロ電子パッケージを製造する方法であって、
第１のダイを第１の基板に取り付けるステップと、
スペーサを前記第１のダイに取り付けるステップと、
第２のダイを前記スペーサに取り付けるステップと、
第２の基板を前記第２のダイに取り付けるステップと、
前記第１の基板と前記第２の基板との間の第１の組の電気的接続を行うステップと、
前記第１のダイと前記第１の基板との間の第２の組の電気的接続を行うステップと、
前記第２のダイと前記第２の基板との間の第３の組の電気的接続を行うステップと
を含む方法。 A method of manufacturing a microelectronic package comprising:
Attaching a first die to a first substrate;
Attaching a spacer to the first die;
Attaching a second die to the spacer;
Attaching a second substrate to the second die;
Making a first set of electrical connections between the first substrate and the second substrate;
Making a second set of electrical connections between the first die and the first substrate;
Making a third set of electrical connections between the second die and the second substrate. 前記第１のダイの裏面を前記第１の基板の第２の面に取り付けるステップと、前記第１のダイの活性面上の端子と前記第１の基板の前記第２の面上のコンタクトとの間の前記第２の組の電気的接続を行うステップとをさらに含む、請求項５６に記載の方法。   Attaching the back surface of the first die to the second surface of the first substrate; terminals on the active surface of the first die; and contacts on the second surface of the first substrate. 57. The method of claim 56, further comprising: making the second set of electrical connections between. 前記第２のダイの活性面上のほぼ中心に配置される端子と前記第２の基板の第２の面上のコンタクトとの間の前記第３の組の電気的接続を、前記第２の基板内の開口を通って延びるワイヤによって行うステップをさらに含む、請求項５６に記載の方法。   The third set of electrical connections between a terminal located substantially centrally on the active surface of the second die and a contact on the second surface of the second substrate, 57. The method of claim 56, further comprising performing with a wire extending through an opening in the substrate. 第２のマイクロ電子パッケージを前記第１の基板または前記第２の基板に取り付けるステップをさらに含む、請求項５６に記載の方法。   57. The method of claim 56, further comprising attaching a second microelectronic package to the first substrate or the second substrate. 積み重ね可能なマルチ電子パッケージを製作する方法であって、
第１のダイを第１の基板の上に取り付けるステップであって、前記第１のダイが、前記第１の基板上のパッドに物理的に接触する電気的結合部を有するステップと、
前記第１のダイ上に第２のダイを取り付けるステップと、
前記第２のダイ上に第２の基板を取り付けるステップと、
前記第１の基板上の第１のコンタクトを前記第２の基板上の第１のコンタクトにワイヤボンディングするステップと、
前記第２のダイ上の接続端子を前記第２の基板上の第２のコンタクトにワイヤボンディングするステップと
を含む方法。 A method of making a stackable multi-electronic package,
Mounting a first die on a first substrate, wherein the first die has an electrical coupling that physically contacts a pad on the first substrate;
Mounting a second die on the first die;
Mounting a second substrate on the second die;
Wire bonding a first contact on the first substrate to a first contact on the second substrate;
Wire bonding a connection terminal on the second die to a second contact on the second substrate. 前記第１の基板上の前記第１のコンタクトが、前記第１の基板の縁部に隣接し、前記第２の基板上の前記第１のコンタクトが、前記第２の基板の縁部に隣接する、請求項６０に記載の方法。   The first contact on the first substrate is adjacent to an edge of the first substrate, and the first contact on the second substrate is adjacent to an edge of the second substrate. 61. The method of claim 60. 前記第２の基板上の前記第２のコンタクトが、前記第２の基板内の開口に隣接する、請求項６０に記載の方法。   61. The method of claim 60, wherein the second contact on the second substrate is adjacent to an opening in the second substrate.
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