JP2009506553A - Microelectronic device packages, stacked microelectronic device packages, and methods of manufacturing a microelectronic device - Google Patents

Microelectronic device packages, stacked microelectronic device packages, and methods of manufacturing a microelectronic device Download PDF

Info

Publication number
JP2009506553A
JP2009506553A JP2008528182A JP2008528182A JP2009506553A JP 2009506553 A JP2009506553 A JP 2009506553A JP 2008528182 A JP2008528182 A JP 2008528182A JP 2008528182 A JP2008528182 A JP 2008528182A JP 2009506553 A JP2009506553 A JP 2009506553A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
substrate
die
microelectronic
package
set
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008528182A
Other languages
Japanese (ja)
Other versions
JP5522561B2 (en )
Inventor
キム ダルソン イエ,セン
ホイ チョン,チン
Original Assignee
マイクロン テクノロジー, インク.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136Covering only the central area of the surface to be connected, i.e. central arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0651Wire or wire-like electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1076Shape of the containers
    • H01L2225/1088Arrangements to limit the height of the assembly
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

積み重ね可能なマイクロ電子パッケージが、第1の基板に取り付けられ、ならびに第1の基板と電気的に接続する第1のマイクロ電子ダイを含む。 Stackable microelectronic package includes attached to the first substrate, and the first of the first microelectronic die connection substrate electrically. 第2のマイクロ電子ダイは、一方の面が第1のダイに、他方の面が第2の基板に取り付けられる。 The second microelectronic die, one face to the first die, the other surface is attached to the second substrate. 第1のダイと第1の基板との間、第2のダイと第2の基板との間、および第1の基板と第2の基板との間の電気的接続が、例えばワイヤボンディングによって行われる。 Between the first die and the first substrate, the line electrical connection, for example, by wire bonding between the second die and between the second substrate and the first substrate and the second substrate divide. 電気的接続要素は、モールドコンパウンドで有利に覆われる。 Electrical connection element is advantageously covered with mold compound. モールドコンパウンドで覆われていない第1および/または第2の基板上の露出コンタクトは、パッケージとパッケージ上に積み重ねられる他のパッケージとの間の電気的接続を可能にする。 The first and / or second exposed contacts on a substrate which is not covered by the molding compound, to allow electrical connection between the other packages are stacked on the package and the package. パッケージは、共平面性ファクタを回避することができ、既存の設備を用いて製造することができ、中間試験を可能にし、およびより薄いパッケージ高さを提供することもできる。 Package can be avoided coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also provide a thinner package height.
【選択図】図1 .FIELD 1

Description

本発明は、マイクロ電子デバイスパッケージ(microelectronic device package)、積重ね型マイクロ電子デバイスパッケージ(stacked microelectronic device package)、およびマイクロ電子デバイスを製造する方法に関する。 The present invention is a microelectronic device package (microelectronic device package), stacked microelectronic device packages (stacked microelectronic device package), and a method of manufacturing a microelectronic device.

マイクロ電子デバイスは一般に、高密度の微小構成要素を有する集積回路を含むダイ(すなわちチップ)を有する。 Microelectronic devices generally have a die (i.e., chip) that includes integrated circuitry having a high density of micro-components. 典型的なプロセスでは、多数のダイが、様々な段階(例えば、注入、ドーピング、フォトリソグラフィ、化学気相成長、プラズマ気相成長、めっき、平坦化、エッチングなど)で繰り返すことができる様々なプロセスを用いて、単一ウェハ上に製造される。 In a typical process, a large number of die, various stages (e.g., injection, doping, photolithography, chemical vapor deposition, plasma vapor deposition, plating, planarizing, etching, etc.) various processes can be repeated using, it is fabricated on a single wafer. ダイは一般に、集積回路に電気的に結合される微小ボンドパッドの配列を含む。 Die generally includes an array of micro-bond pad electrically coupled to the integrated circuit. ボンドパッドは、供給電圧、信号などが、それを通って集積回路に往復伝送される、ダイ上の外部電気コンタクトである。 Bond pad supply voltage, signals, etc., are reciprocally transmitted to the integrated circuit through which an external electrical contacts on the die. 次に、ダイは、ウェハをダイシングし個々のダイを裏面研削することによって、互いに分離される(すなわち個片化される)。 Next, the die, by back grinding the individual dies diced wafers, (is ie singulated) are separated from each other. ダイは一般に、個片化された後、ボンドパッドを、様々な電源線、信号線、および接地線により容易に結合されうるより大きな配列の電気端子に結合させるために、「パッケージ化」される。 Die generally after being singulated, the bond pad, various power lines, signal lines, and for coupling to electrical terminals of the larger sequence can be easily combined with ground lines are "packaged" .

個々のダイは、ダイ上のボンドパッドをピン、ボールパッドまたは他のタイプの電気端子の配列に電気的に結合し、次いでダイをモールドコンパウンド内に封止して、ダイを環境因子(例えば、湿気、粒子、静電気、および物理的衝撃)から保護し、ならびにマイクロ電子デバイスパッケージを形成することによって、パッケージ化されうる。 The individual die bond pads on the die pin electrically coupled to the array of ball pads or other types of electrical terminals, and then sealing the die in a molding compound, environmental factors die (e.g., moisture, by protecting particles, static electricity, and physical impact), and to form a microelectronic device package, can be packaged. 1つの応用例では、ボンドパッドは、ボールパッド配列を有するインタポーザ基板上のコンタクトに電気的に接続される。 In one application, the bond pads are electrically connected to contacts on an interposer substrate having a ball pad array.

電子製品は、非常に限られた空間に極めて高密度の構成要素を有するために、パッケージ化したマイクロ電子デバイスを必要とする。 Electronic products, in order to have a very high density of components has a very limited space, require microelectronic devices packaged. 例えば、記憶装置、プロセッサ、表示装置、および他のマイクロ電子構成要素のために使用可能な空間は、携帯電話、PDA、携帯用コンピュータ、および他の多くの製品内で極めて限定される。 For example, the space available for the storage device, a processor, a display device, and other microelectronic components, cellular phone, PDA, portable computers, and are very limited in many other products. したがって、プリント回路板上のマイクロ電子デバイスの表面積すなわち「フットプリント」を縮小するために、強力な動因がある。 Therefore, in order to reduce the surface area or "footprint" of the microelectronic device on a printed circuit board, there is a strong motive. マイクロ電子デバイスのサイズを縮小するのは、困難となりうる。 To reduce the size of microelectronic devices can be difficult. というのは、高性能のマイクロ電子デバイスは一般に、より多くのボンドパッドを有し、それによってボールグリッドアレイが大きくなり、したがってフットプリントが大きくなるからである。 Since the high-performance microelectronic devices generally have more bond pads, whereby since the ball grid array is increased, thus the footprint is increased. 所与のフットプリント内のマイクロ電子デバイスの密度を増大させるために用いられる1つの技法は、1つのマイクロ電子デバイスパッケージを他のパッケージの上に積み重ねることである。 One technique used to increase the density of microelectronic devices within a given footprint is to stack one microelectronic device package on top of other packages. しかし、こうした既存の積重ね設計にはいくつかの欠点がありうる。 However, there may be some drawbacks to these existing stacked designs. 例えば、それらは、相互接続のために基板上に余分な空間を必要としたり、デバイスの個別の品質管理試験を妨げたり、あるいは他の欠点を有する可能性がある。 For example, they may have or require extra space on the substrate for interconnection to impede individual quality control testing of the devices, or other drawbacks.

マイクロ電子パッケージは、単一パッケージ内に2つのチップまたはダイを有利に含む。 Microelectronic package advantageously includes two chips or dies in a single package. これは、場所を取らない設計を可能にする。 This allows a design that does not take place. ある設計では、より薄いパッケージを実現することもできる。 In one design, it is also possible to achieve a thinner package. パッケージは、ダイが積重ねアセンブリに配置される前に個別に試験されうるように、設計することができる。 Package, as can be tested individually before the die is placed in stacked assembly can be designed. ダイは、共平面性の欠点をよりうまく回避するために、任意で背中合わせに配置することもできる。 Die, in order to better avoid the disadvantages of the co-planarity can be placed back to back in any. 一実施形態では、マイクロ電子パッケージは、第1の基板と電気的に接続する第1のマイクロ電子ダイと、第1の基板と電気的に接続する第2の基板と、第2の基板と電気的に接続する第2のマイクロ電子ダイとを有する。 In one embodiment, microelectronic package includes a first microelectronic die to be connected to the first substrate and electrically, and the second substrate to connect the first substrate and electrically, the second substrate and electrically and a second microelectronic die to be connected. 電気的接続がワイヤボンディングによって行われる設計では、一方の基板が他方の基板よりも大きいことが有利である。 In the design electrical connections are made by wire bonding, it is advantageous one substrate is larger than the other substrate.

マイクロ電子パッケージは、積重ねアセンブリを形成するために、他のすなわち第2のマイクロ電子パッケージに積み重ねる、または取り付けることができる。 Microelectronic package, to form a stacked assembly, stacked on the other or second microelectronic package, or can be attached. 一方のマイクロ電子パッケージの第1の基板上のコンタクトを、他方のマイクロ電子パッケージの第2の基板上のコンタクトに電気的に接続または連接することにより、2つのマイクロ電子パッケージアセンブリを電気的に接続することができる。 A first contact on the substrate of one microelectronic package by electrically connecting or connected to the second contact on the substrate of the other microelectronic package electrically connects the two microelectronic package assembly can do. 積み重ねられるパッケージは、回路板に取り付けられ、どちらか一方のパッケージの別の基板上のコンタクトを介して回路板に電気的に接続されうる。 Stacked packages are attached to the circuit board can be electrically connected to the circuit board via another contact on the substrate of either package.

本発明のいくつかの実施形態の多くの具体的な詳細について、複数のマイクロ電子デバイスを単一アセンブリに一体に形成することに関して以下に説明するが、他の実施形態では、各デバイスを別々に形成することができる。 Some of the many specific details of an embodiment of the present invention, illustrating a plurality of microelectronic devices in the following terms be formed integrally into a single assembly, in other embodiments, each device separately it can be formed. 本発明によるいくつかの実施形態は、図面に記載されている。 Some embodiments according to the invention are described in the drawings. しかし、図面は、説明だけのために提供される。 However, the drawings are provided for illustration only. それらは、本発明の範囲を限定して示すものではない。 They are not shown to limit the scope of the present invention. 以下の文章は、本発明の特定の実施形態を十分理解できるように提供される。 The following text, specific embodiments of the present invention is provided as can be appreciated. しかし、当業者なら、本発明が追加の実施形態を有しうること、あるいは、本発明が、図面に記載されている、または示される詳細のうちのいくつかがなくても実施されうることを理解する。 However, those skilled in the art, that the present invention may have additional embodiments, or that the present invention may be practiced without several of the details shown or described in the drawings to understand.

ここで図1を参照すると、積み重ね可能なマイクロ電子パッケージ(stackable microelectronic package)10が、開口または溝14を有する第1の基板12を有する。 Referring now to FIG. 1, stackable microelectronic package (stackable microelectronic package) 10 has a first substrate 12 having an opening or groove 14. 開口14は、基板12のほぼ中心に有利に位置することができる。 Opening 14 can be located advantageously in the approximate center of the substrate 12. 第1のマイクロ電子ダイまたはチップ18は、活性面40および裏面42を有する。 The first microelectronic die or chip 18 has an active surface 40 and rear surface 42. 活性面40は、第1の基板12に取り付けられるか、または隣接している。 Active surface 40 is either attached to the first substrate 12, or are adjacent. ダイ18の活性面40は、基板12の第2の面(ここでは上面として示される)上のコンタクトと電気的に接続する端子(例えばボンドパッド)を有する。 Active surface 40 of the die 18 has a terminal (e.g., bond pads) for connecting the contacts electrically (shown as the upper surface in this case) the second surface of the substrate 12. 端子およびコンタクトは、典型的にはアレイ状に配置される。 Terminals and contacts are typically arranged in an array. 基板12上のコンタクトは一般に、基板12の第1の面(ここでは底面として示される)上の他のコンタクトに電気的に接続されて、アセンブリ10を回路板または他の上位アセンブリと電気的に接続できるようにする。 Contacts on the substrate 12 is typically the first surface of the substrate 12 are electrically connected to the other contacts on (here shown as the bottom surface), the assembly 10 of the circuit board or other higher assembly and electrically to be able to connect.

第2のマイクロ電子ダイまたはチップ22は、第1のダイ18の裏面に、好ましくは接着剤20で取り付けられる裏面42を有する。 The second microelectronic die or chip 22, to the rear surface of the first die 18 preferably has a rear surface 42 which is attached with an adhesive 20. この取付け(ならびに本明細書で記載される他の取付け)は、直接でも間接でもよく、すなわち、それらの間に1つ以上の中間要素があってもなくてもよい。 This attachment (as well as other attachment described herein) may be direct or indirect, i.e., may or may not have one or more intermediate elements between them. 各ダイ18および22は一般に、25に破線で概略的に示される1つ以上の集積回路を有する。 Each die 18 and 22 generally have one or more integrated circuits, schematically indicated by dashed lines 25. 第2の基板24は、第2のダイ22の活性面40に取り付けられる。 The second substrate 24 is attached to the active surface 40 of the second die 22.

第1の基板12は、第2の基板24よりも大きく(すなわち、幅が広くおよび/または長さが長い)、これは、図1に示されるように、第1の基板12が第2の基板24から外に広がることを意味する。 The first substrate 12 is larger than the second substrate 24 (i.e., longer wider and / or length), which, as shown in FIG. 1, the first substrate 12 of the second It means that spread from the substrate 24 to the outside. 第1の基板12の上面すなわち第2の面上のパッドまたはコンタクト34を、第2の基板24の上面すなわち第2の面上のパッドまたはコンタクト34に接続することによって、第1の基板と第2の基板との間で電気的接続が行われる。 A first pad or contact 34 on the top surface or second surface of the substrate 12, by connecting the second pad or contact 34 on the top surface or second surface of the substrate 24, a first substrate first electrical connection is made between the second substrate. これらの接続は、ワイヤボンド26によって行うことができる。 These connections can be made by wire bonds 26. 第1の基板上のコンタクト34は、第2の基板24から外に広がる第1の基板12の領域上に位置するので、それらの間のボンド接続は、既存の技法を用いて行うことができる。 First contacts 34 on the substrate, since the second substrate 24 located on a region of the first substrate 12 extending outside bond connections between them can be performed using existing techniques . パッドまたはコンタクト34および38は、説明のために、図1に破線で拡大して不釣り合いに示される。 Pads or contacts 34 and 38, for purposes of explanation, shown enlarged by a broken line in FIG. 1 disproportionately.

第2の基板24の上のコンタクトと第2のダイ22の活性面上の端子との間で、電気的接続が行われる。 Between the contact and the terminal on the active surface of the second die 22 on the second substrate 24, electrical connection is made. 図1に示されるように、第2の基板24は、貫通する開口または溝14を有する。 As shown in FIG. 1, the second substrate 24 has an opening or groove 14 penetrates. したがって、ワイヤボンド26または他の接続要素が開口14を通って延びて、第2の基板24と第2のダイ22の間の接続を行うことができる。 Therefore, the wire bonds 26 or other connection element extends through the opening 14, can be connected between the second substrate 24 of the second die 22. 第2のダイ22に対するワイヤボンド手順は、第1のダイ18に対するワイヤボンド手順と比べると逆であり、したがって、ピンアサインは、ボールピン配列に相当する。 Wire bonding procedure for the second die 22 is reversed as compared with the wire bonding procedure for the first die 18, therefore, the pin assignment corresponds to the ball pin array.

第1の基板12と第1のダイ18上の端子との間の電気的接続も、同じ方法で行うことができる。 The electrical connection between the terminals on the first substrate 12 first die 18 can also be carried out in the same way. 図1に示されるパッケージ10は、左右対称とすることができる。 Package 10 shown in FIG. 1 may be symmetrical. ダイ18および22は、同じ幅または長さを有するものとして示されるが、ダイは、同じでもよく、あるいは電気的および/または機械的に互いに異なってもよい。 Die 18 and 22 is shown as having the same width or length, the die may be the same, or electrical and / or mechanical may be different from each other. 基板12および24は、ダイを保持し、かつ電気的相互接続を可能にするために、プリント回路板または他のタイプの基板とすることができる。 Substrate 12 and 24, holds a die, and to allow electrical interconnection, may be a printed circuit board or other type of substrate. 基板上のパッド134は一般に、同等のまたは対応する配列の電気的結合部(例えば、はんだボールまたは他のはんだ要素)を受けるように、アレイ状に配置される。 Pads 134 on the substrate generally, the electrical coupling unit of equivalent or corresponding sequences (e.g., solder balls or other solder elements) to receive, are arranged in an array. 第1のダイ18および第1の基板12は、ボードオンチップ構造を形成する。 The first die 18 and first substrate 12 form a board-on-chip structure. 同様に、第2のダイ22および第2の基板22もまた、ボードオンチップ構造を形成する。 Similarly, also form a board on chip structure second die 22 and the second substrate 22.

ワイヤボンド接続26が行われた後、モールドコンパウンド28が、図1に示される各領域内のワイヤボンド26を覆うように塗布される。 After the wire bond connections 26 are made, mold compound 28 is applied over the wire bonds 26 in each region shown in Figure 1. ワイヤボンド26と、基板の内端または外端に隣接するコンタクト34と、それらが接続する対象であるダイ上の端子とが、モールドコンパウンド28で覆われる。 And wire bonds 26, a contact 34 adjacent the inner end or outer end of the substrate, and the terminals on the die is a target to which they are connected, are covered with mold compound 28. ダイ18および22のすべての面を、基板およびモールドコンパウンドで完全に密封する、または覆うことができる。 All aspects of the die 18 and 22 can be completely sealed with the substrate and the mold compound, or covers. 第1の基板12の下側は、開口14でのワイヤボンドを除いて、モールドコンパウンド28で覆われていないことが有利である。 Under the first substrate 12, except for the wire bonds at the opening 14, it is advantageous not covered by the molding compound 28. 第2の基板24上のワイヤボンドコンタクト34間に位置する露出コンタクト38は、モールドコンパウンドで覆われない。 Exposed contacts 38 located between the wire bond contacts 34 on the second substrate 24 is not covered with the molding compound. これにより、パッケージ10上に積み重ねられる他のパッケージとの電気的接続を行う際に使用するために、第1の基板の下面上の露出コンタクト38を覆われないままにしておく。 Thus, for use in making electrical connections with other packages stacked on the package 10, leaving uncovered the exposed contacts 38 on the lower surface of the first substrate.

次いで、すべてのコンタクトおよび端子は、依然として試験装置によってアクセス可能であるので、パッケージ10を試験することができる。 Then, all of the contacts and terminals are the still accessible by test equipment can test the package 10. これにより、パッケージの積重ねアセンブリへの最終組立ての前に、欠陥パッケージを検出し除去することが可能になる。 Thus, prior to the final assembly of the package of stacked assemblies, it is possible to remove and detect defects package. したがって、積重ねアセンブリは、既知の良好なアセンブリパッケージで製作することができる。 Accordingly, stacked assembly may be made of a known good assembly packages. これは、製造時の歩留りを改善する。 This improves the yield at the time of manufacture.

パッケージ10が回路板または他の上位アセンブリに取り付けられる用途では、パッケージ10は、図1の向きに、すなわち第1の基板12が回路板上にある状態で、取り付けることができる。 In applications where the package 10 is mounted on a circuit board or other higher-level assembly, the package 10 is in the orientation of FIG. 1, i.e. in a state the first substrate 12 is located on the circuit board, it can be attached. 次いで、露出コンタクト38が回路板上のコンタクト、パッドまたは端子に連接することにより、パッケージ10と回路板との間で電気的接続を行うことができる。 Then, by exposing the contact 38 is connected contacts on the circuit board, the pads or terminals, it is possible to perform the electrical connection between the package 10 and the circuit board. これらの接続を行うために、リフローはんだボール16を使用することができる。 To make these connections, it is possible to use the reflow solder balls 16. パッケージ上10に追加のパッケージが積み重ねられない場合、回路板への接続は、代替的または付加的に、第2の基板24上の露出コンタクト38を介して行うことができる。 If on the package 10 is not stacked additional package connected to the circuit board may alternatively or additionally, can be accomplished through the exposure contacts 38 on the second substrate 24. 図2に示されるように、1つ以上の追加のパッケージがパッケージ10上に積み重ねられる場合、回路板への接続は、代替的または付加的に、スタックの最上部のパッケージ上の露出コンタクトがあればそれを介して行うことができる。 As shown in FIG. 2, if one or more additional packages are stacked onto the package 10, connected to the circuit board may alternatively or additionally, the exposed contacts on the top of the package of the stack there if it is possible to perform it through.

図2は、第1のパッケージ10の上に積み重ねられる第2のパッケージ10を示す。 Figure 2 shows a second package 10 stacked on the first package 10. 2
つの積み重ねられるパッケージの間の電気的接続を行うために、はんだボールまたは要素16をランドグリッドアレイ上で使用することができる。 One of to make electrical connection between the stacked are packaged, can be used solder balls or elements 16 on the land grid array. さらに、上部パッケージの第1の基板12と下部パッケージ上のモールドコンパウンド28との間、および/または積重ねアセンブリ36の中心に示される隣接するモールドコンパウンド突出部44相互間で、パッケージ10の機械的取付けを接着剤で行うことができる。 Furthermore, the first between the substrate 12 and the mold compound 28 on the lower package, and / or stacked assembly 36 centered between the adjacent mold compound protrusions 44 cross as shown in the mechanical attachment of the package 10 of the upper package it can be carried out with an adhesive. 第2のパッケージは、相互間で必要な電気的接続を行うことができるのであれば、第1のパッケージと電気的かつ機械的に同じでも異なっていてもよい。 The second package, if it is possible to perform the necessary electrical connections between each other or may be different electrically and a first package even mechanically identical. 図2は、2つのパッケージ10を有する積重ねアセンブリ36を示すが、もちろん、積重ねアセンブリ36は、例えば3つ、4つ、5つまたはそれ以上のパッケージを有することもできる。 Figure 2 shows a stacked assembly 36 having two packages 10, of course, stacked assembly 36, for example three, four, may have five or more packages.

図3は、他の実施形態48を示し、第1の基板52上の第1のダイ18が、チップオンボード構造を形成する。 Figure 3 shows another embodiment 48, the first die 18 on the first substrate 52, to form a chip-on-board structure. 図1に示される第1の基板12とは異なり、図3内の第1の基板52は、開口または溝を有さない。 Unlike the first substrate 12 shown in FIG. 1, the first substrate 52 in FIG. 3 has no opening or groove. スペーサまたはエポキシパッド50が、第1のダイ18上に設けられる。 Spacer or epoxy pad 50 is provided on the first die 18. 第2のダイ22が、スペーサ50上に設けられる。 Second die 22 is provided on the spacer 50. これらのダイは、接着剤20によってスペーサに取り付けることができる。 These die may be attached to the spacer by an adhesive 20. 第2のダイ22に第2の基板24が取り付けられて、図1内の第2のダイおよび第2の基板に類似のボードオンチップ構造を形成する。 And a second substrate 24 is attached to the second die 22, forming a similar board on chip structure on the second die and the second substrate in FIG. スペーサ50は、第1のダイ18の活性面の上に空間をもたらして、第1のダイ18と第1の基板52との間でワイヤボンディングまたは同様の接続を行うことが可能になる。 The spacer 50 is brought space over the active surface of the first die 18, it is possible to perform wire bonding or similar connections between the first die 18 and first substrate 52.

第2のダイ22が第1のダイ18よりも小さい場合、スペーサ50は、ワイヤボンディングのために必要ないので、省略することができる。 If the second die 22 is smaller than the first die 18, the spacer 50 are not necessary for the wire bonding can be omitted. この場合、第2のダイ22は、図1と同様に、第1のダイ18に直接取り付けることができる。 In this case, the second die 22, similarly to FIG. 1, it can be attached directly to the first die 18. 第1および第2のダイの間の接続は、第2の基板のボンドフィンガから第1の基板のボンドフィンガまでの周辺ワイヤボンディングによって行うことができる。 The connection between the first and second die may be performed by the peripheral wire bonding from the second bond finger of the substrate to bond fingers of the first substrate. 第2の基板24と第2のダイ22との間、および第2の基板24と第1の基板との間のワイヤボンディングまたは他の電気的接続、ならびにモールドコンパウンド28は、上述したように、図1と同じように行う、または使用することができる。 Between the second substrate 24 and the second die 22, and a second substrate 24 a wire bonding or other electrical connections between the first substrate and the molding compound 28, as described above, performed in the same manner as in FIG. 1, or may be used. 図3に示されるパッケージ48は、追加の他のマイクロ電子パッケージ(パッケージ48と同じでも異なっていてもよい)の上に積み重ねられて、図2に示される概念と同様の積重ねアセンブリ36を形成することができる。 Package 48 shown in FIG. 3, stacked on top of additional other microelectronic packages (which may be the same as or different from the package 48) to form a concept similar stack assembly 36 shown in FIG. 2 be able to.

図4は、図3に示す設計とほぼ同様であるが、第1のダイ60がフリップチップパッケージ構造である、他の実施形態58を示す。 Figure 4 is substantially similar to the design shown in FIG. 3, the first die 60 is a flip-chip package structure, shows another embodiment 58. 第1のダイ60は、活性面を下にして第1の基板52に取り付けられる。 The first die 60 is attached to the active surface on the first substrate 52 facing down. 第1のダイ60と第1の基板52との間の電気的接続は、下向きの活性面上の導電性バンプまたは電気的結合部を介して行われる。 The first die 60 electrical connection between the first substrate 52 is performed through the conductive bumps or electrical coupling of the downward active surface. バンプは、第1の基板52上の目標パッドまたはコンタクトと一致しかつ接触する。 Bump is consistent with and in contact with the target pads or contacts on the first substrate 52. 第2のダイ22の裏面は、第1のダイ60の裏面に取り付けられる。 The back surface of the second die 22 is attached to the back surface of the first die 60. 第2の基板24は、第2のダイ22の活性面の上に取り付けられて、ボードオンチップ構造を形成する。 The second substrate 24 is mounted on the active surface of the second die 22, forming a board-on-chip structure. 第2のダイ22と第2の基板24との間、および第1の基板52と第2の基板24との間の電気的接続、ならびにモールドコンパウンド28は、図1または3を参照して上述したのと同じように行うことができる。 Electrical connection between the between the second die 22 and the second substrate 24, and the first substrate 52 and second substrate 24, and the molding compound 28, with reference to FIG. 1 or 3 above it can be carried out in the same way as was the. パッケージ58は、図1〜3に関連して上述したように、積み重ねられて、複数パッケージの積重ねアセンブリ36を形成することができる。 Package 58, as described above in connection with FIGS. 1-3, are stacked, it is possible to form a stacked assembly 36 of a plurality packages.

図5は、図4に示す設計とほぼ同様であるが、フリップチップを小さい方の基板74に取り付けられる第2のダイ60として用いた、他の実施形態68を示す。 Figure 5 is substantially similar to the design shown in FIG. 4, shown is used as the second die 60 attached to the substrate 74 smaller the flip chip, the other embodiments 68. 第1のダイ72が、ボードオンチップ構造の形で第1の基板70に取り付けられる。 The first die 72 is attached to the first substrate 70 in the form of a board on chip structure. 第2のダイ60は、接着剤20を用いて、第1のダイ72の上に背中合わせに取り付けることができる。 The second die 60 with an adhesive 20 may be attached back to back on the first die 72. 第2の基板74は、第2のダイ60に取り付けられる。 The second substrate 74 is attached to the second die 60. 第2のダイ60はフリップチップであるので、図4内の第1のダイ60を参照して上述したように、電気的接続が、第2のダイと第2の基板との間で第2のダイ上のバンプを介して行われる。 Since the second die 60 is a flip-chip, as described above with reference to the first die 60 in FIG. 4, the electrical connection, first between the second die and the second substrate 2 It takes place through the die bumps. 第2のダイ60に取り付けられる第2の基板74は、第1の基板70よりも小さい。 A second substrate 74 attached to the second die 60 is smaller than the first substrate 70. 第1および第2の基板の間、および第1のダイ72と第1の基板70との間の電気的接続は、ワイヤボンド26を介して行うことができる。 Between the first and second substrate, and the first die 72 electrical connection between the first substrate 70 can be performed through the wire bonds 26.

上述の設計は、同一平面性の問題を(ダイが背中合わせになっているため)回避すること、既存の設備を用いてアセンブリが可能であること、第1および第2の基板が、業界標準(JEDEC)に適合するボールピン配列のアサインを有することができること、構成要素を、最終アセンブリの前に個別に試験することができること、より薄いパッケージ高さを達成できること、などの利点を提供することができる。 Above design, the coplanarity problem (for the die is in back-to-back) avoid that, it is possible assembly using existing equipment, the first and second substrates, the industry standard ( it can have the assignment of matching ball pivot arranged in JEDEC), the components that can be tested separately before final assembly, to provide the advantage of, such as can achieve thinner packages height it can. もちろん、様々な実施形態を用いて様々な方法で本発明を実施して、これらの利点それぞれを実現する場合もあり、そうでない場合もある。 Of course, by implementing the present invention in a variety of ways using a variety of embodiments, it may also be realized each of these advantages, it may not. 本発明は、それぞれの利点をかならずしも達成することなく使用することもできる。 The present invention can also be used without necessarily achieving each advantage.

パッド、コンタクト、端子、バンプ、電気的結合部などの用語は、電気的な接続を行うために用いられる特徴を制限なしに表現するためのものであり、特定の排他的な意味を有するものではない。 Pads, contacts, terminals, bumps, terms such as electrical coupling unit is intended to represent, without limiting the features used to make electrical connections, the one having a specific exclusive meanings Absent. 本明細書で用いられているような、取り付けられる(attached)という用語は、直接間接を問わず、接合される、接着される、連接される、ボンディングされる、あるいはその他の方法で支持されることを意味する。 The term as used herein, is attached (an attached) is directly or indirectly, are bonded, are bonded, it is articulated and supported by bonded by, or otherwise it means that. 基板という用語は、ここではダイが取り付けられる要素または基部を意味し、基板は、典型的には回路板を含むが、それに限らない。 The term substrate is used herein to mean an element or base die is attached, the substrate is typically including circuit board is not limited thereto. 間(between)という用語は、周辺ワイヤボンディングと同様に、第1の要素と第2の要素との間の直接接続を意味するが、他のタイプの直接的または間接的電気的接続も含む。 Term between (Between), as well as the peripheral wire bonding, but refers to the direct connection between the first and second elements, including direct or indirect electrical connection other types.

したがって、いくつかの実施形態、およびそれらを製作する方法について示し、説明してきた。 Accordingly, some embodiments, and shows the method of making them has been described. 本発明の精神および範囲から逸脱することなく、様々な変更および置換を行うことができる。 Without departing from the spirit and scope of the present invention, it can make various changes and substitutions. したがって、本発明は、特許請求の範囲とその同等物による以外は限定されるべきでない。 Accordingly, the present invention, except by their equivalents and the appended claims should not be limited.

積み重ね可能なマイクロ電子マルチダイパッケージの概略断面図である。 It is a schematic cross-sectional view of a stackable microelectronic multi-die package. 図1に示される2つのパッケージが、積重ねアセンブリを形成するように互いに取り付けられるものの概略断面図である。 Two package shown in FIG. 1 is a schematic cross-sectional view of being attached together to form a stacked assembly. 他の積み重ね可能なマルチダイパッケージの概略断面図である。 It is a schematic cross-sectional view of another stackable multi-die package. 他の積み重ね可能なマルチダイパッケージの概略断面図である。 It is a schematic cross-sectional view of another stackable multi-die package. さらに他の積み重ね可能なマルチダイパッケージの概略断面図である。 Further is a schematic cross-sectional view of another stackable multi-die package.

Claims (62)

  1. 第1の基板と、 A first substrate,
    前記第1の基板と電気的に接続する第1のマイクロ電子ダイと、 Said first first microelectronic die to the substrate and electrically connected,
    前記第1の基板と電気的に接続する第2の基板と、 A second substrate electrically connected to said first substrate,
    前記第2の基板と電気的に接続する第2のマイクロ電子ダイとを含むマイクロ電子パッケージ。 Microelectronic package comprising a second second microelectronic die to the substrate and electrically connected.
  2. 前記第1の基板の第2の面を前記第2の基板の第2の面に接続する第1の組のワイヤと、前記第1の基板の第1の面を前記第1のマイクロ電子ダイの中心領域に接続する第2の組又はワイヤと、前記第2の基板の第2の面を前記第2のマイクロ電子ダイに接続する第3の組のワイヤとをさらに含む、請求項1に記載のマイクロ電子パッケージ。 The first of the first set of wires and, wherein the first of the first surface of the substrate and the first microelectronic die and the second surface of the substrate connected to the second surface of the second substrate further comprising a second set or wires connecting to the central region, and a third set of wires connecting the second side of the second substrate to the second microelectronic die, to claim 1 the microelectronic package according.
  3. 前記第1の基板が、前記第2の基板よりも大きい、請求項1に記載のマイクロ電子パッケージ。 The first substrate is larger than the second substrate, microelectronic package of claim 1.
  4. 前記第1の基板が、前記第2の基板にワイヤボンディングによって電気的に接続する、請求項3に記載のマイクロ電子パッケージ。 The first substrate is electrically connected by wire bonding to the second substrate, microelectronic package of claim 3.
  5. 前記第1のマイクロ電子ダイが、ボードオンチップパッケージ構造を含む、請求項1に記載のマイクロ電子パッケージ。 The first microelectronic die comprises a board on chip package structure, a microelectronic package according to claim 1.
  6. 前記第2のマイクロ電子ダイが、ボードオンチップパッケージ構造を含む、請求項1に記載のマイクロ電子パッケージ。 The second microelectronic die comprises a board on chip package structure, a microelectronic package according to claim 1.
  7. 前記第2の基板が、2つ以上のパッケージアセンブリからなる積重ねアセンブリを可能にするために、露出する電気コンタクトのグリッドアレイを有する、請求項1に記載のマイクロ電子パッケージ。 It said second substrate, in order to enable stacking assembly of two or more package assembly, has a grid array of electrical contacts exposed, microelectronic package of claim 1.
  8. 前記第1および第2のマイクロ電子ダイがそれぞれ、複数の活性端子を含む活性面と、裏面とを含み、前記第1のマイクロ電子ダイの前記裏面が、前記第2のマイクロ電子ダイの前記裏面に取り付けられる、請求項1に記載のマイクロ電子パッケージ。 Each of the first and second microelectronic die comprises an active surface including a plurality of active terminals, a back, the back surface of the first microelectronic die, the back surface of the second microelectronic die attached to, microelectronic package of claim 1.
  9. 前記第1の基板が第1の面および第2の面を有し、前記第2の面が前記第1のマイクロ電子ダイに隣接し、前記基板の前記第1の面が複数のコンタクトを有し、前記第1の基板が貫通開口部を有し、前記基板の前記第1の面上の前記複数のコンタクトから前記第1のマイクロ電子ダイまで延びるワイヤをさらに含む、請求項1に記載のマイクロ電子パッケージ。 Said first substrate having a first surface and a second surface, adjacent to the second surface of the first microelectronic die, have a first surface a plurality of contacts of said substrate and, wherein the first substrate has a through-opening, further comprising a wire extending from said plurality of contacts on said first surface of said substrate to said first microelectronic die, according to claim 1 microelectronic package.
  10. 前記第2の基板が第1の面および第2の面を有し、前記第1の面が前記第2のマイクロ電子ダイに隣接し、前記第2の基板が貫通開口部を有し、前記第2のダイ上の複数のコンタクトから前記第2の基板の前記第2の面まで延びるワイヤをさらに含む、請求項9に記載のマイクロ電子パッケージ。 Said second substrate having a first surface and a second surface, said first surface is adjacent to the second microelectronic die, the second substrate has a through-opening, the further comprising a wire extending from the plurality of contacts on the second die to the second surface of the second substrate, microelectronic package of claim 9.
  11. 前記第1、第2および第3の組のワイヤを封止するモールドコンパウンドをさらに含む、請求項2に記載のマイクロ電子パッケージ。 The first, further comprising a mold compound to seal the second and third set of wires, microelectronic package of claim 2.
  12. 前記第1のダイが前記第1の基板に隣接し、前記第2のダイが前記第2の基板に隣接し、前記第1のダイが前記第2のダイに隣接する、請求項1に記載のマイクロ電子パッケージ。 Said first die is adjacent to the first substrate, said second die adjacent to said second substrate, said first die is adjacent to the second die, according to claim 1 microelectronic package.
  13. 前記第1のダイが、前記第1の基板の第2の面と接触する、前記第1のダイの活性面上の複数の電気端子を介して、前記第1のダイに電気的に接続される、請求項1に記載のマイクロ電子パッケージ。 Said first die, said contact with the first of the second surface of the substrate, through a plurality of electrical terminals on the active surface of the first die is electrically connected to the first die that microelectronic package of claim 1.
  14. 第1の基板と、 A first substrate,
    前記第1の基板と電気的に接続する第1のマイクロ電子ダイと、 Said first first microelectronic die to the substrate and electrically connected,
    前記第1の基板と電気的に接続する第2の基板と、 A second substrate electrically connected to said first substrate,
    前記第2の基板と電気的に接続する第2のマイクロ電子ダイと を含む第1のマイクロ電子パッケージ、ならびに 第3の基板と、 A first microelectronic package and the third substrate, comprising a second second microelectronic die to the substrate and electrically connected,
    前記第3の基板と電気的に接続する第3のマイクロ電子ダイと、 A third microelectronic die connecting said third substrate and electrically,
    前記第2および第3の基板の間の複数の電気接続部と を含む第2のマイクロ電子パッケージを含む、積重ね型マイクロ電子パッケージアセンブリ。 Comprising a second microelectronic package including a plurality of electrical connection between said second and third substrate, stacked microelectronic package assembly.
  15. 前記第1のマイクロ電子パッケージアセンブリに付随する第1、第2および第3の組のワイヤであって、前記第1の組のワイヤが、前記第1の基板の第2の面を前記第2の基板の第2の面に接続し、前記第2の組又はワイヤが、前記第1の基板の第1の面を前記第1のマイクロ電子ダイの中心領域に接続し、前記第3の組のワイヤが、前記第2の基板の前記第2の面を前記第2のマイクロ電子ダイに接続する、第1、第2および第3の組のワイヤと、 First, a second and third set of wires, said first set of wires, the second surface of the first substrate and the second associated with the first microelectronic package assembly connect the the second surface of the substrate, the second set or wires connecting a first side of said first substrate in a central region of the first microelectronic die, the third set wire, connects the second surface of the second substrate to the second microelectronic die, the first, second and third set of wires,
    前記第3の基板と電気的に接続する第4の基板と、 A fourth substrate electrically connecting with the third substrate,
    前記第2のマイクロ電子パッケージアセンブリに付随する第4、第5および第6の組のワイヤであって、前記第4の組のワイヤが、前記第3の基板の第2の面を前記第4の基板の第2の面に接続し、前記第5の組又はワイヤが、前記第3の基板の第1の面を前記第3のマイクロ電子ダイの中心領域に接続し、前記第6の組のワイヤが、前記第4の基板の前記第2の面を前記第4のマイクロ電子ダイに接続する、第4、第5および第6の組のワイヤとをさらに含む、請求項14に記載の積重ね型マイクロ電子パッケージアセンブリ。 Fourth, a fifth and sixth set of wires, said fourth set of wires, said second surface of said third substrate 4 associated with the second microelectronic package assembly connect the the second surface of the substrate, the fifth set or wires connecting a first surface of the third substrate in a central region of the third microelectronic die, the sixth set of wires, connecting said second surface of said fourth substrate to the fourth microelectronic die, fourth, further comprising a fifth and sixth set of wires, according to claim 14 stacked microelectronic package assembly.
  16. 前記第1および第2のマイクロ電子パッケージアセンブリの間の前記複数の電気接続部が、前記第2および第3の基板の間にはんだボールを含む、請求項14に記載の積重ね型マイクロ電子パッケージアセンブリ。 Wherein said plurality of electrical connections between the first and second microelectronic package assembly, comprising a solder ball between the second and third substrate, stacked microelectronic package assembly according to claim 14 .
  17. 前記第1の基板が、前記第2の基板よりも大きい、請求項14に記載の積重ね型マイクロ電子パッケージアセンブリ。 Said first substrate, said larger than the second substrate, stacked microelectronic package assembly according to claim 14.
  18. 第1の基板上の第1のダイと、 A first die on a first substrate,
    第2のダイ上の第2の基板と、 A second substrate on the second die,
    前記第1および第2のダイの間のスペーサと、 A spacer between the first and second dies,
    前記第1のダイを前記第1の基板に接続する第1の組のワイヤと、 A first set of wires connecting the first die to the first substrate,
    前記第2の基板を前記第1の基板に接続する第2の組のワイヤとを含む、積み重ね可能なマルチ電子ダイパッケージ。 A second set of comprising a wire, stackable multi electronic die package for connecting the second substrate to the first substrate.
  19. 前記第2のダイを、前記第2の基板内の開口を通って前記第2の基板に接続する第3の組のワイヤをさらに含む、請求項18に記載の積み重ね可能なマルチ電子ダイパッケージ。 It said second die, the second through openings in the substrate further includes a third set of wires connecting the second substrate, stackable multi electron-die package of claim 18.
  20. 前記第1のダイおよび第1の基板が、チップオンボードパッケージ構造を含み、前記第2のダイおよび第2の基板が、ボードオンチップパッケージ構造を含む、請求項18に記載の積み重ね可能なマルチ電子ダイパッケージ。 The first die and the first substrate comprises a chip-on-board package structure, the second die and the second substrate comprises a board on chip package structure, stackable of claim 18 Multi electronic die package.
  21. 前記第1の基板が、前記第2の基板よりも大きい、請求項18に記載の積み重ね可能なマルチ電子ダイパッケージ。 The first substrate is larger than the second substrate, stackable multi electron-die package of claim 18.
  22. 第1の基板と、 A first substrate,
    前記第1の基板と電気的に接続する、前記第1の基板上の第1のダイと、 Connecting said first substrate and electrically, the first die on said first substrate,
    前記第1のダイの上に取り付けられる第2のダイと、 A second die mounted on the first die,
    前記第2のダイ上の第2の基板と、 A second substrate on the second die,
    前記第1の基板を前記第2の基板に接続する第1の組のワイヤと、 A first set of wires connecting the first substrate to the second substrate,
    前記第2の基板を前記第2のダイに接続する第2の組のワイヤとを含む、積み重ね可能なマルチ電子ダイパッケージ。 A second set of comprising a wire, stackable multi electronic die package for connecting the second substrate to the second die.
  23. 前記第1の基板および前記第1のダイが、フリップチップパッケージ構造を形成し、前記第2の基板および前記第2のダイが、ボードオンチップパッケージ構造を形成する、請求項22に記載の積み重ね可能なマルチ電子ダイパッケージ。 The first substrate and the first die, to form a flip-chip package structure, the second substrate and the second die, to form a board on chip package structure, a stack of claim 22 the multi-electron-die packages available.
  24. 前記第1の基板の上に積み重ねられるダイパッケージの基板と電気的に接続するように構成された、前記第1の基板の第1の面上の第1のコンタクト配列をさらに含む、請求項22に記載の積み重ね可能なマルチ電子ダイパッケージ。 The configured such that the first connecting die package substrate and electrically be stacked on the substrate, further comprising a first contact arrangement on the first face of the first substrate, according to claim 22 the stackable multi-electronic die package according to.
  25. 前記第1の組のワイヤが、前記第1の基板の第2の面を前記第2の基板の第2の面に接続する、請求項24に記載の積み重ね可能なマルチ電子ダイパッケージ。 It said first set of wires connects a second side of the first substrate to the second surface of the second substrate, stackable multi electron-die package of claim 24.
  26. 前記第1の基板が、前記第2の基板よりも大きい、請求項22に記載の積み重ね可能なマルチ電子ダイパッケージ。 The first substrate is larger than the second substrate, stackable multi electron-die package of claim 22.
  27. 前記第2の基板が、前記第1の基板よりも大きい、請求項22に記載の積み重ね可能なマルチ電子ダイパッケージ。 It said second substrate is larger than the first substrate, stackable multi electron-die package of claim 22.
  28. 前記第1および第2の基板の少なくとも一部を覆うケーシングをさらに含む、請求項22に記載の積み重ね可能なマルチ電子ダイパッケージ。 Wherein said further comprising first and second cover at least a portion of a casing of a substrate, stackable multi electron-die package of claim 22.
  29. 前記ケーシングが、他のパッケージの基板と接続するように構成された電気コンタクトを有する前記第2の基板の領域を露出させる開口を有する、請求項28に記載の積み重ね可能なマルチ電子ダイパッケージ。 The casing has an opening for exposing the region of the second substrate having electrical contacts adapted to connect with a substrate of another package, stackable multi electron-die package of claim 28.
  30. 前記第1および第2の組のワイヤが、ワイヤボンドを含む、請求項22に記載の積み重ね可能なマルチ電子ダイパッケージ。 It said first and second sets of wires comprise wire bonds, stackable multi electron-die package of claim 22.
  31. マイクロ電子パッケージを製造する方法であって、 A method of manufacturing a microelectronic package,
    第1のダイを第1の基板に取り付けるステップと、 Attaching a first die to a first substrate,
    第2のダイを前記第1のダイに取り付けるステップと、 Attaching a second die to the first die,
    第2の基板を前記第2のダイに取り付けるステップと、 And attaching a second substrate to the second die,
    前記第1の基板と前記第2の基板との間の第1の組の電気的接続を行うステップと、 A step for electrically connecting a first set of between the first substrate and the second substrate,
    前記第1のダイと前記第1の基板との間の第2の組の電気的接続を行うステップと、 A step for electrically connecting a second set of between the first substrate and the first die,
    前記第2のダイと前記第2の基板との間の第3の組の電気的接続を行うステップとを含む方法。 Method comprising the steps of electrically connecting the third set of between the second substrate and the second die.
  32. 前記第1、第2および第3の組の電気的接続が、ワイヤボンド接続である、請求項31に記載の方法。 It said first, second and third sets of electrical connections is wirebond connection method according to claim 31.
  33. 前記第2の組の電気的接続が、前記第1の基板内の開口を通って延びるワイヤによって行われる、請求項31に記載の方法。 The second set of electrical connections are made by wires extending through an opening in said first substrate, The method of claim 31.
  34. 前記第3の組の電気的接続が、前記第2の基板内の開口を通って延びるワイヤによって行われる、請求項33に記載の方法。 It said third set of electrical connections are made by wires extending through an opening in the second substrate, The method of claim 33.
  35. 前記第1、第2および第3の組の電気的接続をモールドコンパウンド内に密封するステップをさらに含む、請求項32に記載の方法。 The first, electrical connection of the second and third set further comprises the step of sealing in the molding compound, method of claim 32.
  36. 前記第1の組のワイヤボンドが、前記第1の基板の第2の面上のコンタクトを、前記第2の基板の第2の面上のコンタクトに接続する、請求項32に記載の方法。 It said first set of wire bonds, the contacts on the second surface of the first substrate, to connect to contacts on the second surface of the second substrate, The method of claim 32.
  37. 前記第2の組のワイヤボンドが、前記第1の基板の第1の面上のコンタクトを、前記第1のダイの第1の面上の端子に接続する、請求項32に記載の方法。 It said second set of wire bonds, the contacts on the first surface of the first substrate, connected to the terminals on the first surface of the first die, the method according to claim 32.
  38. 前記第3の組のワイヤボンドが、前記基板の第2の面上のコンタクトを、前記第2のダイの第2の面上のコンタクトに接続する、請求項32に記載の方法。 The third set of wire bonds, the contacts on the second surface of the substrate, connected to the contact on the second surface of the second die, the method according to claim 32.
  39. 前記第1の基板が、前記第2の基板よりも大きい、請求項31に記載の方法。 The first substrate is larger than the second substrate, The method of claim 31.
  40. 前記第1のダイが、ボードオンチップパッケージ構造を含む、請求項31に記載の方法。 It said first die comprises a board on chip package structure, The method of claim 31.
  41. 前記第2のマイクロ電子ダイが、ボードオンチップパッケージ構造を含む、請求項31に記載の方法。 The second microelectronic die comprises a board on chip package structure, The method of claim 31.
  42. 前記マイクロ電子パッケージを他のマイクロ電子パッケージ上に積み重ねることができるようにするために、前記モールドコンパウンドを前記第2の基板の各領域から除外して、電気コンタクトのグリッドアレイを露出したままにするステップをさらに含む、請求項35に記載の方法。 In order to be able to stack the microelectronic package on another microelectronic package, by excluding the mold compound from the region of the second substrate, to leave exposed the electrical contact grid array step further comprising the method of claim 35.
  43. 前記マイクロ電子パッケージを他のマイクロ電子パッケージ上に積み重ねることができるようにするために、前記モールドコンパウンドを前記第1の基板の各領域から除外して、電気コンタクトのグリッドアレイを露出したままにするステップをさらに含む、請求項35に記載の方法。 In order to be able to stack the microelectronic package on another microelectronic package, by excluding the mold compound from the region of the first substrate, to leave exposed the electrical contact grid array step further comprising the method of claim 35.
  44. 前記第1のダイの裏面を接着剤によって前記第2のダイの裏面に取り付けるステップをさらに含む、請求項31に記載の方法。 Further comprising the method of claim 31 the step of attaching the rear surface of said second die back surface of the first die by an adhesive.
  45. 積重ね型マイクロ電子パッケージアセンブリを製造する方法であって、 A method of manufacturing a stacked microelectronic package assembly,
    第1のダイを第1の基板に取り付けるステップと、 Attaching a first die to a first substrate,
    第2のダイを前記第1のダイに取り付けるステップと、 Attaching a second die to the first die,
    第2の基板を前記第2のダイに取り付けるステップと、 And attaching a second substrate to the second die,
    前記第1の基板と前記第2の基板との間の第1の組の電気的接続を行うステップと、 A step for electrically connecting a first set of between the first substrate and the second substrate,
    前記第1のダイと前記第1の基板との間の第2の組の電気的接続を行うステップと、 A step for electrically connecting a second set of between the first substrate and the first die,
    前記第2のダイと前記第2の基板との間の第3の組の電気的接続を行うステップと によって第1のマイクロ電子パッケージを製作するステップ、ならびに 第2のマイクロ電子パッケージを前記第1のマイクロ電子パッケージアセンブリに取り付けるステップを含む方法。 A third set of electrical steps for fabricating a first microelectronic package connected by a step of performing, and the second microelectronic package first between the second substrate and the second die comprising the step of attaching the microelectronic package assembly.
  46. 前記第2のマイクロ電子パッケージのコンタクトを前記第1の基板上のコンタクトに接続することによって、前記第1および第2のマイクロ電子パッケージの間の電気的接続を行うステップをさらに含む、請求項45に記載の方法。 By connecting the contacts of the second microelectronic package to the contact on the first substrate, further comprising an electrical connection between said first and second microelectronic package, according to claim 45 the method according to.
  47. 前記第1および第2のマイクロ電子パッケージの間の電気的接続をはんだ要素によって行うステップをさらに含む、請求項46に記載の方法。 Further comprising the method of claim 46 the steps performed by solder elements an electrical connection between said first and second microelectronic package.
  48. 前記第2のマイクロ電子パッケージを前記第1のマイクロ電子パッケージに取り付ける前に、前記第1および第2のマイクロ電子パッケージの少なくとも一方を試験するステップをさらに含む、請求項45に記載の方法。 Wherein the second microelectronic packages before attaching the first microelectronic package, further comprising the step of testing at least one of the first and second microelectronic packages The method of claim 45.
  49. 前記第2の組の電気的接続が、前記第1の基板内の開口を通って延びるワイヤボンドによって行われる、請求項45に記載の方法。 The second set of electrical connections are performed by the first wire bond extending through the opening in the substrate, The method of claim 45.
  50. 前記第3の組の電気的接続が、前記第2の基板内の開口を通って延びるワイヤボンドによって行われる、請求項45に記載の方法。 It said third set of electrical connections is made by the second wire bond extending through the opening in the substrate, The method of claim 45.
  51. 前記第2のマイクロ電子パッケージアセンブリを前記第1のマイクロ電子パッケージに取り付ける前に、前記第1、第2および第3の組の電気的接続をモールドコンパウンド内に密封するステップをさらに含む、請求項45に記載の方法。 Wherein the second microelectronic package assembly prior to attachment to the first microelectronic package, further comprising the step of sealing the first, second and third set of electrical connections of the molding compound, claim the method according to 45.
  52. 前記第1の基板が前記第2の基板よりも大きく、前記第1の組の電気的接続を、前記第1の基板の第2の面のコンタクトを前記第2の基板の第2の面上のコンタクトにワイヤボンディングすることによって行うステップをさらに含む、請求項45に記載の方法。 Greater than the first substrate is the second substrate, said first set of electrical connections, the second on the surface of said first of said second substrate contact on the second surface of the substrate further comprising the method of claim 45 the steps carried out by the contact wire bonding.
  53. 第3のマイクロ電子パッケージを前記第1のマイクロ電子パッケージに取り付けるステップと、前記第3のマイクロ電子パッケージのコンタクトを前記第2の基板上のコンタクトに接続することによって、前記第1および第3のマイクロ電子パッケージの間の電気的接続を行うステップとをさらに含む、請求項46に記載の方法。 Attaching a third microelectronic package to the first microelectronic package, by connecting the contacts of the third microelectronic package contacts on the second substrate, the first and third further comprising the step of performing the electrical connection between the microelectronic package, the method according to claim 46.
  54. 前記第1の基板上の前記コンタクトが、前記第1の基板の縁部から離れて配置される、請求項46に記載の方法。 The first of said contacts on the substrate is disposed away from the edge of the first substrate, The method of claim 46.
  55. 前記第2のマイクロ電子パッケージが、前記第1のマイクロ電子パッケージアセンブリと同じである、請求項45に記載の方法。 The second microelectronic package is the same as the first microelectronic package assembly method according to claim 45.
  56. マイクロ電子パッケージを製造する方法であって、 A method of manufacturing a microelectronic package,
    第1のダイを第1の基板に取り付けるステップと、 Attaching a first die to a first substrate,
    スペーサを前記第1のダイに取り付けるステップと、 And attaching the spacer to the first die,
    第2のダイを前記スペーサに取り付けるステップと、 Attaching a second die to the spacer,
    第2の基板を前記第2のダイに取り付けるステップと、 And attaching a second substrate to the second die,
    前記第1の基板と前記第2の基板との間の第1の組の電気的接続を行うステップと、 A step for electrically connecting a first set of between the first substrate and the second substrate,
    前記第1のダイと前記第1の基板との間の第2の組の電気的接続を行うステップと、 A step for electrically connecting a second set of between the first substrate and the first die,
    前記第2のダイと前記第2の基板との間の第3の組の電気的接続を行うステップとを含む方法。 Method comprising the steps of electrically connecting the third set of between the second substrate and the second die.
  57. 前記第1のダイの裏面を前記第1の基板の第2の面に取り付けるステップと、前記第1のダイの活性面上の端子と前記第1の基板の前記第2の面上のコンタクトとの間の前記第2の組の電気的接続を行うステップとをさらに含む、請求項56に記載の方法。 And attaching the rear surface of the first die to the second surface of the first substrate, and contacts on the second surface of the terminals on the active surface of the first die and the first substrate further comprising the method of claim 56 and a second set of steps for performing the electrical connection between the.
  58. 前記第2のダイの活性面上のほぼ中心に配置される端子と前記第2の基板の第2の面上のコンタクトとの間の前記第3の組の電気的接続を、前記第2の基板内の開口を通って延びるワイヤによって行うステップをさらに含む、請求項56に記載の方法。 The electrical connection of the third set between the contact on the second surface of the second substrate and the terminals arranged substantially in the center of the active surface of the second die, the second further comprising the method of claim 56 the steps performed by a wire extending through the opening in the substrate.
  59. 第2のマイクロ電子パッケージを前記第1の基板または前記第2の基板に取り付けるステップをさらに含む、請求項56に記載の方法。 Further comprising the step of attaching the second microelectronic package to the first substrate or the second substrate, The method of claim 56.
  60. 積み重ね可能なマルチ電子パッケージを製作する方法であって、 A method of fabricating a stackable multi-electronic package,
    第1のダイを第1の基板の上に取り付けるステップであって、前記第1のダイが、前記第1の基板上のパッドに物理的に接触する電気的結合部を有するステップと、 The method comprising: attaching a first die on a first substrate, the first die comprises the steps of having an electrical coupling unit in physical contact with the first pads on the substrate,
    前記第1のダイ上に第2のダイを取り付けるステップと、 Attaching a second die on the first die,
    前記第2のダイ上に第2の基板を取り付けるステップと、 And attaching a second substrate on the second die,
    前記第1の基板上の第1のコンタクトを前記第2の基板上の第1のコンタクトにワイヤボンディングするステップと、 A step of wire bonding the first contacts on the first substrate to the first contacts on the second substrate,
    前記第2のダイ上の接続端子を前記第2の基板上の第2のコンタクトにワイヤボンディングするステップとを含む方法。 Method comprising the steps of wire bonding to the second contacts on the second substrate on the connection terminals of the second die.
  61. 前記第1の基板上の前記第1のコンタクトが、前記第1の基板の縁部に隣接し、前記第2の基板上の前記第1のコンタクトが、前記第2の基板の縁部に隣接する、請求項60に記載の方法。 The first of said first contact on the substrate, adjacent to the edge of the first substrate, the first contacts on the second substrate, adjacent to the edge of the second substrate to method of claim 60.
  62. 前記第2の基板上の前記第2のコンタクトが、前記第2の基板内の開口に隣接する、請求項60に記載の方法。 Said second of said second contact on the substrate, adjacent to the opening in the second substrate, The method of claim 60.
JP2008528182A 2005-08-26 2006-08-25 Microelectronic device packages, stacked microelectronic device packages, and methods of manufacturing a microelectronic device Active JP5522561B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US11218028 US7504284B2 (en) 2005-08-26 2005-08-31 Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US11/218,028 2005-08-31
PCT/US2006/033219 WO2007025127A3 (en) 2005-08-26 2006-08-25 Microelectronic device packages, stacked microlecetronic device packages, and methods for manufacturing microelectronic devices

Publications (2)

Publication Number Publication Date
JP2009506553A true true JP2009506553A (en) 2009-02-12
JP5522561B2 JP5522561B2 (en) 2014-06-18

Family

ID=37802914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008528182A Active JP5522561B2 (en) 2005-08-26 2006-08-25 Microelectronic device packages, stacked microelectronic device packages, and methods of manufacturing a microelectronic device

Country Status (1)

Country Link
JP (1) JP5522561B2 (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013535825A (en) * 2010-07-19 2013-09-12 テッセラ,インコーポレイテッド Stackable mold microelectronic package comprising an area array unit connector
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10115678B2 (en) 2017-11-06 2018-10-30 Invensas Corporation Wire bond wires for interference shielding

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025553A (en) * 1988-06-24 1990-01-10 Fujitsu Ltd Semiconductor device
JPH0289852U (en) 1988-12-27 1990-07-17
JPH03159146A (en) 1989-11-16 1991-07-09 Tokyo Electron Ltd Probing card
JP2000228468A (en) 1999-02-05 2000-08-15 Mitsubishi Electric Corp Semiconductor chip and semiconductor device
US6472736B1 (en) * 2002-03-13 2002-10-29 Kingpak Technology Inc. Stacked structure for memory chips
WO2004027823A2 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having wire bond interconnection between stacked packages
US20040159954A1 (en) * 2002-12-17 2004-08-19 Infineon Technologies Ag Electronic device having a stack of semiconductor chips and method for the production thereof
JP2005026680A (en) 2003-06-30 2005-01-27 Samsung Electronics Co Ltd Stacked ball grid array package and its manufacturing method
US20050023657A1 (en) 2003-04-18 2005-02-03 Yu-Fang Tsai Stacked chip-packaging structure
US20050046006A1 (en) 2003-08-28 2005-03-03 Kun-Dae Yeom Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same
JP2005150719A (en) * 2003-11-13 2005-06-09 Samsung Electronics Co Ltd Double-stacked bga package and multi-stacked bga package
WO2005059967A2 (en) * 2003-12-17 2005-06-30 Chippac, Inc. Multiple chip package module having inverted package stacked over die

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH025553A (en) * 1988-06-24 1990-01-10 Fujitsu Ltd Semiconductor device
JPH0289852U (en) 1988-12-27 1990-07-17
JPH03159146A (en) 1989-11-16 1991-07-09 Tokyo Electron Ltd Probing card
JP2000228468A (en) 1999-02-05 2000-08-15 Mitsubishi Electric Corp Semiconductor chip and semiconductor device
US6472736B1 (en) * 2002-03-13 2002-10-29 Kingpak Technology Inc. Stacked structure for memory chips
WO2004027823A2 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having wire bond interconnection between stacked packages
US20040159954A1 (en) * 2002-12-17 2004-08-19 Infineon Technologies Ag Electronic device having a stack of semiconductor chips and method for the production thereof
US20050023657A1 (en) 2003-04-18 2005-02-03 Yu-Fang Tsai Stacked chip-packaging structure
JP2005026680A (en) 2003-06-30 2005-01-27 Samsung Electronics Co Ltd Stacked ball grid array package and its manufacturing method
US20050046006A1 (en) 2003-08-28 2005-03-03 Kun-Dae Yeom Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same
JP2005150719A (en) * 2003-11-13 2005-06-09 Samsung Electronics Co Ltd Double-stacked bga package and multi-stacked bga package
WO2005059967A2 (en) * 2003-12-17 2005-06-30 Chippac, Inc. Multiple chip package module having inverted package stacked over die

Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9153562B2 (en) 2004-11-03 2015-10-06 Tessera, Inc. Stacked packaging improvements
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US9218988B2 (en) 2005-12-23 2015-12-22 Tessera, Inc. Microelectronic packages and methods therefor
KR101734882B1 (en) 2010-07-19 2017-05-12 테세라, 인코포레이티드 Stackable molded microelectronic packages with area array unit connectors
JP2013535825A (en) * 2010-07-19 2013-09-12 テッセラ,インコーポレイテッド Stackable mold microelectronic package comprising an area array unit connector
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
JP2017038075A (en) * 2010-07-19 2017-02-16 テッセラ,インコーポレイテッド Stackable molded ultra small electronic package including area array unit connector
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
CN106129041A (en) * 2010-07-19 2016-11-16 德塞拉股份有限公司 Stackable molded microelectronic packages with area array unit connectors
US9324681B2 (en) 2010-12-13 2016-04-26 Tessera, Inc. Pin attachment
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9224717B2 (en) 2011-05-03 2015-12-29 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9252122B2 (en) 2011-10-17 2016-02-02 Invensas Corporation Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10115678B2 (en) 2017-11-06 2018-10-30 Invensas Corporation Wire bond wires for interference shielding

Also Published As

Publication number Publication date Type
JP5522561B2 (en) 2014-06-18 grant

Similar Documents

Publication Publication Date Title
US6936913B2 (en) High performance vias for vertical IC packaging
US7205178B2 (en) Land grid array packaged device and method of forming same
US6051878A (en) Method of constructing stacked packages
US5684330A (en) Chip-sized package having metal circuit substrate
US6313522B1 (en) Semiconductor structure having stacked semiconductor devices
US7535110B2 (en) Stack die packages
US7429787B2 (en) Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides
US5817530A (en) Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
US6870249B2 (en) Semiconductor device and manufacturing method thereof
US6765228B2 (en) Bonding pad with separate bonding and probing areas
US20060220209A1 (en) Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
US20060240595A1 (en) Method and apparatus for flip-chip packaging providing testing capability
US6861761B2 (en) Multi-chip stack flip-chip package
US6706557B2 (en) Method of fabricating stacked die configurations utilizing redistribution bond pads
US20060108676A1 (en) Multi-chip package using an interposer
US7298033B2 (en) Stack type ball grid array package and method for manufacturing the same
US6731009B1 (en) Multi-die assembly
US5763947A (en) Integrated circuit chip package having configurable contacts and a removable connector
US7345361B2 (en) Stackable integrated circuit packaging
US6558978B1 (en) Chip-over-chip integrated circuit package
US20080032448A1 (en) Semiconductor device with stacked chips and method for manufacturing thereof
US20050173807A1 (en) High density vertically stacked semiconductor device
US6765299B2 (en) Semiconductor device and the method for manufacturing the same
US7326592B2 (en) Stacked die package
US20070190690A1 (en) Integrated circuit package system with exposed interconnects

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110208

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110509

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20110509

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120403

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120802

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20120802

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120813

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20120907

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20121219

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20121219

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20121226

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130124

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130124

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130130

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130221

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20130702

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130702

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130711

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131008

Free format text: JAPANESE INTERMEDIATE CODE: A821

Effective date: 20131008

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20140328

R150 Certificate of patent or registration of utility model

Ref document number: 5522561

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250