JP2009503822A - System and method for assembling packaged integrated circuits using insulated wire bonds - Google Patents

Abstract

  The apparatus and method provide a reduced impact of replacing bare bond wires with insulated bond wires in an IC packaging process. In particular, methods and apparatus are presented to limit the changes required in the assembly process, thereby enabling a faster and cheaper transformation of the current assembly process.

Description

  The present invention relates generally to systems and methods for assembling integrated circuits, and more particularly to systems for assembling integrated circuits where the wire bonds used in the assembly are protected by an insulating coating.

  Miniaturization is a feature of modern electronic devices. Integrated circuits (ICs) have become very small in size, and integrated circuits are created on silicon wafers by various known techniques, for example. ICs typically contain densely packed electronic circuits, located at the heart of any intelligent electronic device, and must be connected to the outside world to gain access to their functions.

  On the other hand, ICs typically need to be connected to other devices to make one complete electronic device. For example, the IC may need to be connected to other ICs or other electronic components, either directly or via a circuit board. For example, in a device bonded with a wire, an IC is provided with an input port and an output port including bonding pads. Bonding pads make it easy to connect or bond wires to ports to make functional devices.

  However, since ICs are very small and fragile, it is often too difficult to directly manipulate the IC during the manufacturing process. Thus, the IC is processed into a packaged IC, thereby reducing problems associated with using unpackaged ICs in the manufacturing process.

  The standard packaging process for an organic plastic encapsulation module is described below. Several ICs are typically made on a single silicon wafer. The ICs are then cut from the wafer or diced into individual ICs, which are also called “dies”. Each die is attached to a bonding substrate. In general, multiple dies are attached to a single bonding substrate to improve the efficiency of the manufacturing process. The IC / substrate combination is cleaned with plasma to remove foreign contaminants or oxides that could interfere with the next step, wire bonding.

  In wire bonding, a thin conductive bare wire is taken, and the bare wire is bonded from the connection pad of the IC to the connection pad of the substrate by welding. The substrate to which the IC is attached includes several bond pads. Bond pads are sometimes referred to as bond fingers or lead fingers. Bond fingers are typically placed around the outer edge of the substrate and are electrically isolated from one another to prevent short circuits. The wire bonding process electrically connects the bond fingers of the substrate to corresponding IC bond pads via bare gold bonding wires. Bond fingers are typically routed along the substrate to leads or pads (typically metal or solder ball connections). The leads or pads may then be electrically connected to other components as needed to complete the electrical device.

  The wire bonded IC and substrate combination is often cleaned again with plasma prior to the molding step or encapsulation. The main purpose of this cleaning is to remove foreign contamination before the next stage begins.

  In the molding stage, in order to physically shield the combination of the IC and the substrate bonded with the wire from the environment, a polymer material containing a filler is injected at a high pressure to protect the wire and the IC with an epoxy dielectric. Wrap it in. The previous plasma cleaning step strengthens the adhesion of the molding epoxy to the substrate, and the molding epoxy covers the entire IC, all bonding wires, and corresponding portions of the substrate. The entire assembly is then cured.

  When the wrapping is performed, for example, a lead or a conductive wire such as a solder ball is attached to the substrate. If the substrate has a shape in which many devices are arranged in strips, the substrate is then cut into individual parts. These are the desired package ICs.

  The process outlined above is described in detail in “From Dicking to Packing: Exposing the Packing Process” by Patrick McKinney in the March 2001 issue of Advanced Packaging. This process is typical for a class of ICs that value price / performance, such as application specific integrated circuits (ASICs), microprocessor units (MPUs), digital signal processors (DSPs), and the like. As package configurations, ball grid array (BGA), quad flat pack (QFP), chip scale package (CSP), etc. are provided, which are the basic physical shape, size and style of the package IC. Is specified.

  The wires used for this type of wire bonding are typically bare. Thus, IC packaging and bonding pads separate the IC input and output by a gap sufficient to allow the wires to be placed without causing a short circuit. However, the use of bare wire limits the bond wire pattern because a relatively large spacing between the wires is required. When such large gaps are required, miniaturization is hampered, circuit paths become unnecessarily long, and the speed and efficiency of the assembled device is reduced.

  Therefore, it is desirable to introduce an insulating bonding wire into a standard packaging process. In microelectronics, the use of insulated bonding wires has long been sought. If bond wires can be placed in direct physical contact with each other without risking an electrical short circuit, starting with an increase in input / output connections, improved performance, size, and time to market. Until now, new flexibility is provided in IC package design.

  Therefore, recently, it has been proposed to use an insulated wire instead of a bare wire. For example, US Pat. No. 6,177,726, entitled “SiO2 Wire Bond Insulation in Semiconductor Assemblies” granted to Mantegie on January 23, 2001, describes a process that includes insulation after bare wire wire bonding. Is described. However, since the wires are bare during wire bonding, the wires must be separated to prevent electrical shorts. This solution thus limits the possibility of using insulated wires.

  Therefore, it is even more desirable to be able to use “pre-insulated” bonding wires to achieve maximum flexibility. US Patent No. 5,396,104 entitled “Resin Coated Bonding Wire, Method of Manufacturing the Same, and Semiconductor Device” granted to Kimura, and “Ball Bon ing” U.S. Pat. No. 4,860,941 entitled "Wire" describes an insulating bonding wire.

  Insulated bonding wires as illustrated above maximize the flexibility of point-to-point connections, allowing configurations ranging from high-density “on-chip” interconnections to complex chip-to-chip assembly. become. However, when the insulating bonding wire is introduced into the package IC assembly process, a trouble occurs. Since the package IC assembly process is well established, it is desirable to limit the changes required in the assembly process when using insulated wires or wires.

  Accordingly, it is an object of the present invention to obviate or mitigate at least some of the above disadvantages.

  The present invention attempts to reduce the impact of replacing bare bond wires with insulated bond wires in the IC package process. As such, several methods are presented to limit the changes required in the assembly process, thereby making the current assembly process faster and cheaper to convert.

  According to one aspect of the present invention, there is provided a process step for assembling an integrated circuit / substrate combination into an integrated circuit package using a bonding wire having an insulating coating. Uses a plasma to clean a combination of an IC and a substrate, and uses an insulating bonding wire to control each aspect of a pattern of wires to be bonded in a three-dimensional manner. Wire-attached using a reduced-power plasma cleaning device configured to remove contamination while minimally affecting the coating of the insulated bonding wire Cleaning the combination of the IC and the substrate, and the bonding of the IC and the substrate bonded with the wire at an optimized speed. Forming a wire-bonded IC and substrate combination using a molding tool configured to wrap with xy, thereby limiting damage to the insulating bonding wire; Curing the epoxy to provide a packaged IC that protects the integrated IC and substrate from direct exposure to the environment.

  According to a further aspect of the present invention, a method is provided for bonding an integrated circuit (IC) to a substrate by stitch bonding using a bonding wire. The bonding wire is bonded to the IC at one end, and this method includes a step of setting a tool change point (Tool Inflection Point) having a height of 5 mils (about 127 μm) or less, and bonding on the substrate. Using a set tool change point to effectively create a bond at the site.

  According to a further aspect of the present invention, there is provided a method of bonding an IC to a substrate by ball stitch bonding using a bonding wire having an insulating coating in a ball stitch bonding machine, the method comprising: arcing a free end of the insulating bonding wire. Creating a loop shape by bending the wire, forming a ball bond at a bond pad on the IC, and breaking the insulation coating so that the bonding wire produces a free air ball. Use a capillary to create a stitched bond in a bond finger on the substrate using a low tool change point (TIP) to create the bond, thereby creating an electrical connection between the IC and the substrate A step of performing.

  According to a further aspect of the present invention, a method is provided for effectively bonding a wire to a bonding site, the method comprising applying a first strike to the bonding site to produce a bond, and to a predetermined height. A step of retracting, and a step of applying a second hit to the joint site.

  According to a further aspect of the present invention, a package integrated circuit (IC) is provided, the package IC comprising an IC attached to a substrate, the IC being electrically connected to the substrate via a bonding wire, the bonding wire being one end And the other end is bonded to the substrate, and at least one of the bonds includes a stitch bond that performs two strikes.

  In accordance with a further aspect of the present invention, there is provided a cleaning apparatus that removes contamination from a combination of an integrated circuit and a substrate bonded with a wire using an insulating bonding wire while minimally affecting the covering of the insulating bonding wire. A method of configuring is provided, the method using a predetermined setting to test the test substrate and the insulating bonding wire sample, and sufficient for the cleaning apparatus to effectively clean the substrate contamination. Analyze the test substrate to determine that it is set to such a high power configuration, and the cleaning device is set to a low power configuration sufficient to remove a minimum amount of coating from the insulating bond wires. To analyze the insulated bonding wire sample and to satisfy both of the above steps. To determine the Kutomo one setting, and a step of iteratively repeating the test using the changed settings.

  According to a further aspect of the present invention, there is provided a method for configuring an insulated wire to be compatible with a forming tool, wherein the insulated wire is bonded with a wire between the IC and the substrate and later covered with a polymeric material. The method includes the steps of limiting the loop height of the wire, thereby minimizing the pulling of the wire due to the flow of the polymeric material, and the areas and geometries that are susceptible to physical damage by the molding process. And avoiding the occurrence of crossing points in the geometric configuration.

  In accordance with a further aspect of the present invention, an integrated circuit (IC) and substrate combination is provided, wherein the IC and the substrate are electrically connected via an insulating bonding wire bonded therebetween and insulated. The bonding wire has a limited loop height of the wire and a geometric configuration that avoids crossing points in areas that are susceptible to physical damage during the subsequent forming process, thereby allowing the insulating bonding wire to form a tool. It is configured to be compatible (compatible) with.

  According to a further aspect of the present invention, there is provided a method of constructing a molding tool that wraps a combination of an IC and a substrate bonded by a wire using an insulating bonding wire with a molding material while limiting damage to the coating of the insulating bonding wire. The method comprises initially inserting a molding material at a minimum flow rate until a flow wall is established, and once the flow wall is established, increasing an epoxy insertion rate to an increased flow rate. However, the duration of the molding process is sufficient to completely cover the combined body of the IC and the substrate without gaps, but is shorter than the gelation time of the molding material.

  According to a further aspect of the present invention, there is provided a test kit including parts for making a tester for testing the breakdown point of an insulating bonding wire, the test kit comprising a base for supporting the tester, a pair A conductive rod of which one of the rods is electrically connected to the anode of the power source and the other of the rods is electrically connected to the cathode of the power source and is spaced apart by a predetermined distance A pair of conductive bars to be tested, a slide for supporting the insulated bonding wire to be tested so that the insulating bonding wire contacts each of the conductive bars, and a pair of conductive bars to the base First connecting means for connecting the insulating bonding wire to the slide, and second connecting means for connecting the insulating bonding wire to the slide.

The embodiments of the present invention will now be described by way of example only with reference to the following drawings.
FIG. 1 is a flowchart for explaining the operation of the wire bonding process.
FIG. 2 is a diagram of a wire bonder for producing a ball joint.
FIG. 3a illustrates a standard TIP for stitch joining (prior art).
FIG. 3b illustrates a stitch bonded capillary according to the present invention.
FIG. 4 is a diagram illustrating the LF2 position that can be assumed in the second bonding.
FIG. 5 is a schematic diagram illustrating an improvement in wire density of an IC employing a single row configuration.
FIG. 6 is a schematic diagram for explaining the improvement of the wire density of an IC adopting a multi-row configuration.
FIG. 7 is a diagram of a free air ball of insulated wires.
FIG. 8a is a perspective view of an assembled test kit for testing breakdown voltage.
FIG. 8b is a schematic diagram of the electrical connections of the assembled kit described in FIG. 8a.
FIG. 8c is a perspective view of a test substrate for supporting an insulated wire during testing.
FIG. 9 is a block diagram illustrating a forming tool.
FIG. 10 is a diagram illustrating wire regions that become sensitive during the molding process.
FIG. 11a is a top view of the bonded IC and substrate combination illustrating the wire crossing region that becomes sensitive during the molding process.
FIG. 11b is a side view of the bonded IC and substrate combination illustrating the wire crossing region that becomes sensitive during the molding process.
FIG. 12 is a block diagram of a sample tester that is an alternative to the sample tester shown in FIG. 8a.
FIG. 13a illustrates a magazine configured to reduce the power of the plasma cleaning process.
FIG. 13b illustrates an alternative embodiment of FIG. 13a.
FIG. 14a illustrates an alternative embodiment to FIGS. 13a and 13b.
FIG. 14b illustrates an alternative embodiment to FIGS. 13a and 13b.

  For convenience, the same numbers in the description refer to the same configurations in the drawings. Referring to FIG. 1, a flow chart illustrating the process for providing a package IC using insulated bonding wires is indicated generally by the numeral 100.

  In step 102, the IC is cut from the wafer or diced into individual ICs. In step 104, the IC is attached to the bonding substrate. In step 106, the IC and substrate combination is cleaned in preparation for wire bonding. Cleaning is typically accomplished using a plasma, but those skilled in the art will recognize that other methods may be used to clean the IC / substrate combination. Examples of alternative cleaning techniques include chemical cleaning and ultraviolet (UV) ozone. In step 108, the IC bonding pads are connected to the substrate bonding pads using insulated gold bonding wires. In step 110, the bonded IC / substrate combination is again plasma cleaned. In step 112, during the molding process, epoxy is injected to encapsulate and encapsulate the wires and IC to encapsulate and protect them from the environment. The entire assembly is then cured. In step 114, leads or conductors are attached to the substrate, typically in the form of solder balls. In step 116, the substrate is cut into individual package ICs. The following detailed description of the process 100 will reveal changes made to facilitate the use of insulated wires.

  Steps 102 through 106 occur prior to the introduction of the insulated wire into the IC assembly process and can therefore be performed according to the state of the art. In step 108, an insulated wire is bonded between the IC and the substrate. Two types of wire bonders are usually used for wire bonding. One is called a ball bonder and the other is called a wedge bonder. Hereinafter, application of an insulating bonding wire using a ball bonder will be described. Wire bonding using a ball bonder has a ball bonding process, also referred to as first bonding, and a stitch bonding process, also referred to as second bonding or wedge bonding. Ball bonding is typically performed at bond pads on a semiconductor die, and stitch bonding is performed at lead fingers on the substrate. In the present embodiment, wire bonding to the bonding pad of the IC is realized by using an automatic ball stitch wire bonding method, which is provided by, for example, a curric & sofa, ASM, Shinkawa, Kaijo, or ESEC. Available on industry standard equipment.

  The overall operation of the ball stitch wire bonding machine will be described below. The combined device and substrate is heated to a defined temperature with a heating body below the substrate. The free end of the insulated wire is sparked to generate a free air ball (FAB). The wire bonding machine uses pressure and ultrasonic vibration at a high temperature to bond the FAB to the input / output pad of the IC, which is called first bonding or ball bonding. The wire bonding machine is then located on the corresponding bonding pad or finger of the substrate. Wire bonding machines use pressure and ultrasonic vibration to bond an insulated wire to a substrate, which is called a second bond, or stitch bond, and then cuts the insulated wire, thus creating an IC Creates an electrical connection, i.e. a loop, between the circuit board and the substrate. A free air ball is again generated from the free end of the wire and positioned on the IC to generate the next loop. This process is repeated until all desired wire bond connections are completed.

  Referring to FIG. 2, an example of a ball stitch bonding machine for generating a first bond is indicated generally by the numeral 200. Insulated bond wire 201 is shown extending from spool 202 away from free end 204. In the present embodiment, the insulating bond wire 201 is X-Wire (registered trademark) manufactured by Micro Bonds, and has an insulating material having a thickness of about 0.1 μm to 0.5 μm. The spool 202 serves as a supply source for the insulated wire 201. Also shown is a conductive or metal capillary 206 having a central hole or tube 207 through which the insulated wire 201 is drawn. Capillary 206 serves as a wire holder while forming a ball for ball bonding. Many types of materials may be used for the capillaries so that strength, conductivity and manufacturability can be advantageously combined, but tungsten carbide capillaries are preferred.

  A wire clamp 208 is placed on the capillary 206 at a distance from the surface 210 to which the wire 201 is joined. An electronic frame-off (EFO) wand 212 is shown near the free end 204 of the wire 201, approximately below the capillary or wire holder. An ultrasonic transducer arm 214 is also shown, which generates sufficient ultrasonic and pressurizing energy to bond a ball formed at the free end of the wire to the substrate.

  The operation of the above ball stitch bonding apparatus will be briefly described below. The insulated wire is passed through the central hole of the capillary 206 and extended until the free end of the wire exceeds the end of the capillary. The wand 212 emits a charge or arc of electrical energy to the wire 201. Then, this energy jumps to the wire 201, and even if the wire is insulated, the energy exceeds the electrical breakdown potential of the insulation, breaking the insulation and grounding. In the present embodiment, the electrically conductive capillary 228 is grounded. In this step, the free end of the wire 201 is melted and the insulation is broken to form a suitable ball. Details of a ball stitch bonder for use with an insulating bonding wire are described in detail in US Pat. No. 6,896,170, entitled “Wire Bonder for Ball Bonding Insulated Wire and Method of Using Same” by Lin et al.

Furthermore, it should be noted that under the same parameters, the FAB size of the insulated wire will be different from the size of the bare wire FAB. Typically, the size of the insulated wire FAB is expected to be larger than the size of the bare wire FAB. Referring to Table 1 below, a comparison between bare wire and insulated wire X-Wire®, provided by Microbonds, is shown for various parameters of FAB size. Thus, those skilled in the art will recognize that if insulated wires are used, the bonding machine parameters may need to be set differently in order to obtain the desired size of the FAB.

  The second joint includes Tool Inflection Point (TIP), Constant Velocity Motion (CV), ultrasonic power, time, force, temperature, Loop Factor 2 (LF2), There are several parameters to consider, including loop-shaped trajectories and contact angles, contact options, stitching options, and related secondary joint parameters. Referring to FIG. 3a, a diagram illustrating the location for generating the second junction according to the prior art is indicated generally by the number 300. FIG. IC 302 is attached to substrate 304 and the free end of bare wire 306 is already bonded to IC 302 as described above. The clamp of capillary 206 is closed and is positioned to make a second bond. TIP 308 represents the distance between the capillary 206 and the substrate 304 at which point the downward movement to create the second bond decelerates to the CV setting. Standard CV is relatively low compared to high speed descent from the point where wire loop formation is complete, which is the highest point in the wire forming cycle.

  Referring to FIG. 3b, an example of generating a second junction in accordance with this embodiment is indicated generally by the number 350. The free end of the insulated wire 322 is joined to the IC 302. It has been determined that a lower TIP and higher CV should be used than standard in the art to effectively generate the second junction. Therefore, in this embodiment, TIP is approximately half of the standard implementation TIP and CV is approximately twice the standard CV. A rapid increase in velocity at low TIP has been determined to cause a higher impact, which is preferable considering that the wire 322 is provided with an insulating coating. Specifically, depending on the size of the wire, a TIP of less than 5 mils, more preferably 2-3 mils (about 50.8 to about 76.2 μm), and 1.0-2.5 mils. Per millisecond (about 25.4 to about 63.5 μm / msec) has been found to provide the necessary impact.

  Thus, the strength of the second bond is improved compared to standard methods for insulated wires. The above process always produced a strong second bond. Specifically, MIL-STD-883 test method 2011 was used using 4N gold insulated wire modified with beryllium according to ASTM F72-95, having a wire length of 200 mils (about 5.08 mm). When the center tension is adopted according to .7, an average bonding strength of 5 gf (about 49 mN) to 8 gf (about 78 mN) can be obtained by using the insulated wire and the above-described TIP and CV.

  Referring to FIG. 4, an example of a possible LF2 position is indicated generally by the number 400. LF2 defines the horizontal position of the capillary at the TIP with respect to the programmed bond location on the substrate, and is the goal of the last step of CV drop to the substrate bonding finger to form the second bond Determine. If there is a capillary just above the programmed joint location, LF2 is said to be zero. If the capillary is between the IC and the finger, LF2 is said to be positive. If the capillary exceeds the bonding finger as seen from the IC, LF2 is said to be negative. Typical values for LF2 in wire bonding are positive to reduce sagging between wires, thus preventing short circuits. However, since an insulated wire is mounted in this embodiment, a short circuit between adjacent wires is not a concern. Further, as will be described in connection with the forming step 112, some degree of sagging between adjacent wires may prevent the occurrence of short circuits during forming. Therefore, this embodiment can use negative LF2 when generating the second junction.

  As described above, the energy given from the EFO exceeds the electrical breakdown potential of the insulation. Thus, the wire bonding process described above has the ability to “burn out” the wire coating during ball formation (for IC side connections) while maintaining as much of the remaining wire coating as possible. I understand. In this embodiment, the insulation coating is maintained up to the neck of the second joint and up to the upper side of the ball of the first joint.

  The bonding process described above facilitates bonding of insulated wires in various forms that can be envisaged. Since the insulated wire can be bonded between the IC and the substrate with only minimal degradation of insulation, the wire configuration can be more dense and complex than the prior art.

  As an example, referring to FIG. 5, a schematic diagram illustrating how the density of bonding wires per unit length of the outer periphery of the IC is improved is shown. According to recent experiments, it was found that the distance between the wires can be reduced to 0.4 μm. Since the wires are insulated, there is little concern if they come into contact with each other. Such improvements in density can help increase the number of input / output ports that an IC can provide to other components, further miniaturizing electronic components.

  Referring to FIG. 6, the number of input / output ports that can be used can be further increased by increasing the number of input / output port rows without being limited to placing the input / output port rows along the outer periphery of the IC. Because the wires are insulated, the risk of short circuiting is greatly reduced using such a layout.

  Furthermore, the layout described in both FIG. 5 and FIG. 6 allows for more complex connections since the wires can be brought into physical contact with each other with little risk of a short circuit. This greatly expands the circuit layout that can be assumed for the chip designer.

  In the wire bonding described above, it is preferable that the wire is composed of a gold-based metal or a copper-based metal bond wire. In this embodiment, a gold-based metal bond wire is used. Furthermore, the bond wire is preferably 0.005 inches (about 127 μm) or less in diameter. Furthermore, the diameter of the wire is more preferably less than 0.002 inch (about 50.8 μm), and most preferably less than 0.001 inch (about 25.4 μm). However, those skilled in the art will recognize that the diameter of the bond wire may vary depending on the needs of the particular implementation.

  Referring to FIG. 7, a diagram of a free air ball in the case of an insulated wire as described above is shown. In the present embodiment, the insulating coating and the metal surface exhibit a sufficient adhesive force in forming a free air ball by EFO. As can be seen from the figure, the insulation coating is present on the balls and is represented by “watermelon stripes”. From this it can be seen that the insulation breaks when the arc is blown during ball bonding.

  Although this embodiment describes the use of ball stitch bonding to electrically connect an IC to a substrate, those skilled in the art will recognize other bonding methods including wedge wedge bonding using a wedge bonder. It will be appreciated that the invention encompasses.

  In an alternative embodiment, a double hit stitch technique is performed to improve the stitch joint. As explained above, in a normal stitch bonding process, ultrasonic power and force are applied at high temperatures through a bonding tool or bonding capillary to create a bond between the bonding wire and the substrate bonding pad. Added. The bonding capillary must land and remain in contact with the substrate lead fingers before applying ultrasonic power and force. The bond strength of the wire must be high enough to meet the industry specifications required to survive the assembly process and reliability testing.

  For insulated wires, the wire bonder needs to break the insulation coating during bonding. It is beneficial to perform two strikes in the stitch bonding process to help break the coating, expose the metal for bonding, and improve the tendency of fishtail cracks or flaking. Using the double strike stitch technique, the stitch bonding process, excluding the loop forming process, is repeated twice at the same joint site, as described below. After the first strike of the stitch joint is made, the bonding capillary is raised to the programmed height and another strike, the second strike, is made at the same joint site. At each landing, ultrasonic power and force are applied. In the present embodiment, the programmed height is sufficient to cut the insulated wire before the second strike. However, it is not expected to be so.

  The stitch bonding process is repeated at the same joint site, but a joint offset from the first strike of the stitch joint can be applied. A positive bond offset setting shifts the second hit of the stitch joint toward the ball bond, and a negative bond offset setting shifts the second hit of the stitch bond away from the ball bond.

  When wire bonding 108 is complete, the process continues to plasma cleaning in step 110. As described above, the purpose of the plasma cleaning 110 is to remove possible contamination from the IC / substrate combination, which may affect the adhesion of the molding material. , Absorbed contaminants, and airborne contaminants. Therefore, this step 110 may not be necessary if the molding process 112 is performed immediately after the wire bonding 108. However, since the molding process 112 is typically performed separately from the bonding 108 at another facility or in another area of the same facility, a considerable amount of time may elapse between these steps. High nature. Therefore, plasma cleaning 110 after wire bonding is a typical step of the assembly process.

  However, plasma cleaning 110 may reduce the effectiveness of the insulated wire by unintentionally removing a portion of the insulation from the insulated wire, thereby exposing the bare wire to the possibility of a short circuit. This is especially true because insulated wires are often placed in a very close configuration, including intersecting configurations.

  Accordingly, the plasma cleaning step 110 is modified to limit damage to the insulation to prevent conduction between the wires. Specifically, the plasma power is reduced so as to minimize the effect on the insulation wire coating while the plasma cleaning properties are still effective. Further, typical choices of plasma for the cleaning step 110 include argon (Ar) and a mixed gas of argon and oxygen. While the latter is suitable for bare wire, it is preferable to use the former for this embodiment, but this may limit the effect of oxygen reacting with the insulating wire coating material. Because. For example, oxygen can affect coating characteristics such as moisture resistance, ductility, dielectric breakdown, and the like. Since both are generally used, there is almost no influence on the mounting of the plasma cleaning step 110 by selecting argon.

  However, those skilled in the art will recognize that there are several different types of plasma cleaners used in the plasma cleaning step 110. Furthermore, the operation of the same plasma cleaning apparatus in different facilities may differ due to different environmental conditions and the physical state of the plasma cleaning apparatus. Therefore, the power of each plasma cleaning apparatus is set separately using the evaluation kit.

  The evaluation kit provides the materials and recommended instructions required for the evaluation of low power plasma process parameters before molding or reworking. The following description is intended to provide guidance for the evaluation process. Those skilled in the art will recognize that guidelines may need to be changed to meet specific user requirements.

  Referring to FIG. 8a, a sample tester created using the evaluation kit is indicated generally by the number 800. The sample tester 800 is used for conducting a dielectric breakdown test. The tester 800 comprises a plastic or glass base plate 802 and a pair of stainless steel bars 804 separated by a width W. The bar 804 is held in place using a spring loaded conductive clip (not shown). In the present embodiment, W = 25 mm. A glass slide 806 with one or more sample insulated wires 808 to be tested is placed over the bar 804. The glass slide is placed on the rod 804 with the sample wire 808 facing down so that the sample wire 808 is in direct contact with the rod 804.

  Referring to FIG. 8b, a schematic diagram illustrating the electrical connections of the tester described in FIG. 8a is indicated generally by the numeral 820. One of the bars 804 is electrically connected to the positive output of the power supply 822, while the other of the bars 804 is electrically connected to the negative output of the power supply 822. In this embodiment, the power source 822 can supply 0 V to 200 V at 1 A. However, the necessary circuitry is provided to limit the current just above the wire fusing current. A voltmeter 824 is connected to the bar 804 in parallel with the power source 822. The voltmeter can measure up to the maximum value of the power supply. In the present embodiment, the maximum value of the power supply is 200V.

  Referring to FIG. 8c, the configuration of the test substrate 860 used to prepare the sample wire 808 to be tested is shown. In the present embodiment, the test substrate 860 is longer than 15 cm in length. In order to confirm the best results, the test substrate is preferably the same thickness as the actually used substrate. The wire post 862 is placed so as to pass between both ends in the width direction of the test substrate 860. Wire post 862 is attached using a suitable die adhesive. Each wire post 862 includes a pair of upwardly facing grooves (not shown) for receiving the sample wire 808. Sample wire 808 is hung approximately 1 mm above the surface of test substrate 860 by wire post 862. The sample wire 808 is fixed to the wire post 862 using an adhesive tape 864 such as Kapton tape. The sample wire 808 is placed between the wire posts 862 so that it is slightly tensioned.

  The operation when using the above-described evaluation kit to determine the desired parameters of the plasma cleaning 110 before molding will be described in detail below.

  A wire 808 to be tested is attached to the test substrate 860 as described in FIG. 8c. The test substrate 860 is placed in the plasma chamber in the same manner as the target process conditions. It should be noted that when using a low power plasma in a multilayer plasma chamber, a single layer should be used. Experimental results show that the plasma cleaning effect is significantly different between different layers. Therefore, a single layer should be used for consistency. Furthermore, the optimal placement of the substrate in the plasma chamber is a checkerboard pattern. However, it will be appreciated that other placement patterns may be used with only minor differences in results.

In accordance with the recommended conditions given in Table 2, low power plasma cleaning is initiated. As mentioned above, the preferred plasma is argon.

  The duration of plasma cleaning is initially set near the lower time limit. When the plasma cleaning is complete, the sample wire 808 is removed from the test substrate 860. Contact angle measurements are taken at several different locations on the test substrate 860. The contact angle is preferably measured within 60 minutes after the plasma cleaning.

  In this embodiment, at least three locations are analyzed. The contact angle measurement is used to determine the “cleanliness” of the test substrate 860. The smaller the contact angle, the “cleaner” the test substrate 860 is. If the contact angle is less than 30 degrees using deionized (DI) water with a specific resistance greater than 12 MΩ, the test substrate is considered sufficiently clean. Otherwise, the duration of the plasma cleaning is increased and the test process is repeated until the minimum allowable plasma cleaning duration is determined based on the contact angle measurement.

  In the present embodiment, an upper limit of 200 seconds is provided for the duration of the test. When this duration is reached without obtaining a satisfactory contact angle measurement result, the power is increased and the process is started again from the lower limit of the duration.

  Once a suitable time limit has been set, the sample wire 808 is tested to confirm that the plasma clean did not break the insulation coating. Thus, the sample wire 808 is removed from the wire post 862 and a portion of the wire that was under the Kapton tape 864 is cut off. Since the piece of wire that was under the Kapton tape 864 was not exposed to the plasma, the result of the dielectric breakdown test may be distorted.

  Six wire samples 808 are positioned by bonding to glass slide 806 for testing. In this embodiment, two sample wires 808 are tested per glass slide 806. Care must be taken to ensure that the sample wire is not mechanically damaged during handling. For example, nicks, bending, or coating damage due to handling can affect test results. Similarly, six wire samples that have not been plasma cleaned are tested for reference.

  Each glass slide 806 is tested as follows. A glass slide 806 is placed on the rod 804 with the wire sample 808 facing down. The sample wire 808 of the glass slide 806 is in contact with the rod 804 at four points. The glass slide 806 is preferably centered based on the center line between the bars 804. If the glass slide 806 is off-center, each wire contact may have a different weight, which can affect the accuracy of the test.

  A DC voltage is applied from the power source 822 and gradually raised while the wire is monitored under sufficient illumination. As soon as the wire breaks down, a current flow is detected in the power supply and the wire is typically broken into two. The voltage rise is stopped and the voltage reading of the voltmeter 824 is recorded. Note that the typical breakdown voltage range for X-Wire® is 30 VDC to 80 VDC.

  Since there are two wires per slide, the voltage is slowly increased again until a second wire break occurs. The voltmeter reading is recorded and the power source 822 is lowered to zero to prepare for testing the next wire sample 808.

  The following data is collected on the breakdown of both the reference and plasma treated samples. That is, the average of the six breakdown voltages, the standard deviation of the data set (reference and test samples), and the minimum breakdown voltage in the set.

  The degree to which the allowable breakdown voltage is considered should be determined for each design. The following is a guideline for general tolerances for X-Wire®. To be considered acceptable, the difference in average breakdown voltage between the plasma treated wire and the non-plasma treated wire shall be less than 10 percent. Similarly, the minimum breakdown voltage reading is greater than 25 VDC.

  In this way it can be seen that the range of duration of the plasma cleaning can be determined using the test kit. The shortest time that can provide a suitable contact angle measurement is the lower end of the duration range, and the longest time that can provide a suitable dielectric breakdown result is the upper limit of the range. In this way, the plasma cleaning before molding performs a low power cleaning that cleans the combined body of the IC and the substrate but does not substantially affect the insulating coating of the bonding wire.

  Referring to FIG. 12, an alternative sample tester embodiment is indicated generally at 1200. In this embodiment, the sample tester is a substrate 1202, and includes a plurality of bonding pads 1204 on one side of the substrate 1202 and a plurality of test points (not shown) on the other side of the substrate 1202. . The test points are electrically connected to corresponding ones of the bonding pads 1204.

  Two or more insulating bonding wires 1206 are joined in a crossing manner. An example of the form of crossing will be described with reference to FIG. The insulating bonding wires 1206 are in contact with each other due to the intersecting form.

  In order to test the dielectric breakdown voltage of a wire in this embodiment, a voltage is applied between two contacting wires via a test point. A voltage increase method is used to increase the voltage until dielectric breakdown occurs in the insulating material. By detecting the current flowing through any of the wires in contact, the breakdown is identified. This is achieved by monitoring the corresponding test points on the wire. As described above, the voltage is written down and can be used to determine whether the process is satisfactory.

  An advantage of using the sample tester 1200 of this embodiment is that the tester can continue throughout the process and can be used to measure the breakdown voltage after, for example, encapsulation. This is achieved because the user can access the test points. Further, although not shown in FIG. 12, the substrate may include dummy ICs to more closely resemble the actual IC-substrate combination.

  As described above, plasma is used as the cleaning agent, but other cleaning agents may be used. Accordingly, those skilled in the art will recognize that the concept of constructing a cleaning device as described above may be applied to such cleaning agents and cleaning mechanisms.

  In an alternative embodiment, a standard plasma cleaning unit may be used at a standard power level. In the following embodiments, effective plasma cleaning with low power is realized by electrically isolating the carrier of the IC / substrate combination. Isolating the carriers reduces the direct plasma effect by keeping the carriers at a floating potential with respect to the plasma field boundary, resulting in less damage to the plasma insulation. Therefore, large volume plasma cleaning of chip carriers bonded with insulated wires can be performed using magazine loading or an in-line plasma cleaning machine. These embodiments will be described below.

  In one embodiment, a vertical magazine is implemented. Referring to FIG. 13a, the vertical magazine is indicated generally by the number 1300. In the present embodiment, vertical magazine 1300 includes a plurality of horizontal racks 1302 for placing a plurality of joined IC / substrate assemblies on a shelf. Further, the vertical magazine 1300 includes four legs 1304 for supporting the vertical magazine 1300 and maintaining a distance between the vertical magazine 1300 and a surface on which the vertical magazine 1300 is placed. Leg 1304 is constructed of a material selected for stability during the plasma process. Such materials include, for example, glass, ceramics, and semiconductor wafers. Other materials exhibiting desirable characteristics may also be used.

  Then, when the vertical magazine 1300 is placed on a plasma cleaner (not shown), it is placed on one of the electrodes. Thus, the legs 1304 electrically isolate the vertical magazine 1300 from the electrodes, thereby reducing the strength of the plasma cleaning and preventing significant damage to the insulated wires.

  In another embodiment, a horizontal magazine is implemented. Referring to FIG. 13b, a horizontal magazine is indicated generally by the number 1350. The horizontal magazine 1350 is similar to the vertical magazine 1300 except for its orientation. The horizontal magazine 1350 includes a vertical rack 1352 instead of the horizontal rack 1302.

  In yet another embodiment, an insulating sheet (plate) is provided to maintain electrical isolation. Referring to FIG. 14a, a further example 1400 of a vertical magazine is shown. In this example, an insulating sheet 1402 is placed under the vertical magazine 1400 to isolate the vertical magazine 1400 from the electrodes. Similarly, with reference to FIG. 14b, a further example 1450 of a horizontal magazine is shown. In this example, an insulating sheet 1452 is placed under the horizontal magazine 1450 to isolate the horizontal magazine 1450 from the electrodes.

  As illustrated in both FIG. 14a and FIG. 14b, the size and shape of the insulating sheet matches or substantially matches the mounting surface shape of the magazine on the electrode.

  Further, the insulating sheet effectively shields the electrode on which the insulating sheet is placed. This reduces the surface area of the electrode and reduces the path through which plasma can flow from the upper electrode (eg, power supply) to the lower electrode (eg, ground). If a large number of magazines are placed on the electrodes and packed side by side with little or no spacing, the electrodes can be covered until the plasma cannot flow from the upper electrode to the lower electrode. Thus, in order to maintain a sufficient ground-to-power ratio of the plasma electrodes, an interval is provided between the magazines.

  According to a further embodiment, the gap between the two adjacent IC and substrate combinations in the magazine is kept short enough to prevent the creation of local plasma regions, ie hot spots. It is. For example, a double-gap magazine loading in which the gap between the two adjacent IC-substrate combinations in the magazine is 12 mm presents irregular hot spots during cleaning. However, single-gap magazine loading, in which the gap between the two adjacent IC-substrate combinations in the magazine is 6 mm, exhibits little or no hot spots. One skilled in the art will recognize that other distances may be allowed for 6 mm and that it can be verified by experiment. Furthermore, it will be appreciated that the distance may vary depending on factors such as plasma flow rate, pressure, time, and the like.

  Therefore, in this embodiment, all slots of the magazine are filled. Dummy strips are used when there are not enough IC-substrate combinations to fill the magazine. A dummy substrate, such as an empty or discarded substrate, can be the most convenient material to be used as a dummy strip. However, other insulating materials such as glass, ceramic, etc. may be used instead.

  According to a further embodiment, shields are provided at the top and bottom of the magazine slot to further prevent damage to the insulating bond wires of the IC-substrate combination. Both the upper and lower portions of the magazine slot are exposed to a high energy plasma compared to the rest of the magazine. The slot at the bottom of the magazine is usually close to the plasma sheath region that is exposed to hot electrons, high concentrations of ionized gas, and the like. The upper slot of the magazine is usually exposed to self-bias with respect to the magazine surface, which is generally caused by metal or anodized metal material. For this reason, dummy strips are placed on both the top and bottom of the magazine to shield the IC / substrate combination.

The above embodiments utilize the isolation of the magazine from the electrode to effectively reduce the plasma energy in the integrated circuit and substrate combination during the plasma cleaning step. Table 3 below illustrates examples of effective parameters used for plasma cleaning. March Plasma PX-1000 was used for the plasma cleaning process, but other plasma cleaners may be used. A perforated ground shelf configuration (with the ground shelf parallel to the vertical and the power electrode on the bottom of the chamber) was employed. The magazine was isolated using a glass slide.

  The following performance characteristics were confirmed from the test. A perforated ground shelf configuration enhances gas flow during plasma cleaning, but other configurations such as a perforated power shelf configuration may be sufficient. Furthermore, applying a plasma process longer than 5 minutes can cause excessive damage to the insulation coating. Furthermore, in the case of using magazine loading, there is a limit to how the gas reaches at the center of the magazine loading, which inevitably results in non-uniform plasma cleaning.

  According to a further embodiment, high capacity plasma cleaning of the combined integrated circuit and substrate is achieved using an improved in-line plasma cleaning apparatus. Similar to the previous embodiment, the combined integrated circuit and substrate is isolated from the electrodes.

  Therefore, the in-line type plasma cleaning machine is configured such that the combination of the IC and the substrate that is placed on the chip carrier and enters the plasma cleaning machine is isolated. This in-line plasma isolation can be achieved using two methods. In the first method, the chip carrier is isolated by providing an isolating material between the carrier and the rail of the plasma cleaning machine used to support and transport the chip carrier during the plasma cleaning process. In the second method, the plasma cleaner rail is configured to be isolated from the electrodes of the plasma cleaner.

  Examples of high-capacity in-line plasma cleaning devices suitable for such improvements include March Plasma's TRAK (registered trademark) series plasma processing systems and Panasonic PSX303.

The above embodiments utilize rail isolation from the electrode or carrier isolation from the rail to effectively reduce the plasma energy at the chip carrier location during the plasma cleaning phase. Table 4 below illustrates examples of effective parameters used for plasma cleaning. The plasma cleaning process used a March Plasma ITRAK in-line plasma cleaning machine with an electrode distance of 2 inches (about 50.8 mm), but other in-line plasma equipment may be used.

  The following performance characteristics were confirmed from the test. A plasma time of 10 seconds is sufficient to achieve a contact angle of less than 10 degrees. The sample was cleaned uniformly under in-line plasma conditions.

  Once the plasma cleaning 110 is complete, a molding step 112 is performed by injecting a polymeric material with or without filler to encapsulate the wires and IC and protect them from the environment. Although the use of a polymeric material is described in this embodiment, other molding materials may be used as will be understood by those skilled in the art. An example of the polymer material is an epoxy-based molding material containing a silica filler. The entire assembly is then cured. However, the high pressure and temperature of the polymer material and the movement of the polymer material as the polymer material fills the mold during the molding process, both mechanically (physically It may be possible to damage the wire coating (via simple contact).

  Thus, some of the issues to be considered in the molding process include loop height, sensitive cross-shape and position between wires, transfer parameters and material selection criteria such as filler size and distribution, shrinkage when the molding material cures and There is a coefficient of thermal expansion.

  It has been determined to reduce the tensile effect of the forming process on bonded wires with a lower loop height. Specifically, the lower loop height limits the force acting on the wire bond during the molding process, thereby reducing the “lift” of the wire contact.

  Further, the lower loop height maximizes the structural strength of the wire and minimizes wire flow. Whereas wire slack is in the vertical plane, wire flow occurs when the bonded wire is moved from its original position on a horizontal plane during molding. Although wire flow is less of a concern with insulated wires, reducing the wire flow limits the force acting on the insulation coating at the wire intersection. This limits the fact that two intersecting wires “cut” each other due to pressure from the epoxy during molding, thereby exposing the bare wire and creating a potential short circuit. For example, in a PBGA having a BT substrate and a silicon IC having a thickness of 250 to 400 μm and using X-Wire (registered trademark) as an insulating wire, a selective loop height is 266 μm for a wire having a length exceeding 4 mm. It is set to be lower.

  The polymeric material is applied using a transfer molding machine and associated molding equipment. Transfer molding includes devices such as pistons and cylinders that are incorporated into a mold so that epoxy can be injected into a cavity through a small orifice and runway system. Referring to FIG. 9, a block diagram illustrating the forming tool is shown. The IC and substrate combination is placed in a housing 902 having a gate 904 through which the epoxy is injected by a transfer press. The transfer press may comprise an electromechanical press or a hydraulic press. The location of the gate 904 is on the side or corner of the housing 902, as is standard in the art.

  To minimize the “jetting”, which is a turbulent flow in the epoxy, caused when the narrow part (inflow to the gate) suddenly thickens (outflow from the gate), the epoxy exits the gate and flows into the wall. Until a low is established. Once the flow wall is established, the transfer rate can be increased. While it may be preferable to use a lower than recommended maximum transfer rate, the overall transfer rate will necessarily depend on the size of the cavity and the gel time of the selected epoxy. That is, the transfer rate must be sufficient for the housing to be filled with epoxy in a time shorter than the gel time, otherwise the epoxy will begin to set during the transfer process. As the epoxy begins to set during the transfer process, the possibility of damage to the insulated wire increases. Furthermore, it will be apparent that larger cavities will require higher transfer rates than smaller cavities since the gel time of the epoxy is the same.

  Therefore, it is desirable to select an epoxy having the following characteristics as the epoxy used in the molding process. A relatively large spiral flow at the molding temperature is desirable. Spiral flow is a measure of the viscosity and flow properties of a thermoset plastic molding material at molding temperatures for semiconductor devices and is measured in units of length. Spiral flow is measured in specially designed test molds, but the shorter the spiral flow, the greater the tensile force acting on the wire during insertion of the epoxy into the cavity. This is because the material does not flow very naturally without the transfer pressure. Viscosity and spiral flow are closely related. In the above example, the spiral flow at the molding temperature is desirably larger than 140 cm. Those skilled in the art will appreciate that this particular spiral flow is specific to a given example and may be different in other examples.

  As previously mentioned, a relatively long gel time is desirable to reduce the possibility of epoxy gelation, which results in a substantial increase in viscosity during transport. Because. Continuing with this example, a gel time longer than 30 seconds is desirable.

  Further, the molding material such as epoxy preferably has a low viscosity in order to limit mutual interference with the wire. Similarly, the epoxy filler preferably has a relatively small filler size. In this example, a viscosity lower than 60 poise (6 Pa · s) and an average filler size smaller than 19 μm are desirable. Similarly, the epoxy preferably has a relatively low proportion of filler content.

  Furthermore, it is preferred that the ratio of spherical filler particles to the total filler be relatively high, since the flow properties and wire damage are increased by the uneven particles. In this example, the proportion of spherical filler particles is greater than 80 percent.

  However, even though all of the above precautions are noted during transfer molding, there are still some regions and geometric configurations that are susceptible to physical damage from the molding process. Therefore, for these areas, it is preferable to manage the position where the wires intersect to reduce the possibility of wire contact.

  As an example, referring to FIG. 10, a block diagram illustrating a sensitive region near the gate is indicated generally by the number 1000. As shown, the area closest to the gate, as indicated by the vertical line pattern, and the area along the edge of the housing are most sensitive during the molding process. Although the area represented by the diagonal line pattern is less sensitive, attention should still be paid. Therefore, it is preferable to limit the number of wire crossings in these regions. In a housing where the second bonding fingers are placed close to the gate, these areas are more sensitive than in a housing where the second bonding fingers are placed away from the gate. It will be clear.

  Still referring to FIG. 11, a block diagram illustrating a sensitive wire configuration is indicated generally at 1100. As shown, the wire crossing closest to the substrate, indicated by the vertical line pattern, is most sensitive in the molding process. Although the area represented by the diagonal line pattern is less sensitive, attention should still be paid. Typically, insulated wires are less flexible in this regard, and therefore have little “deflection” when placed under pressure during the molding process. As previously mentioned, although insulated wires can be designed to assume a crossed configuration without much concern for short circuits, pressure from the molding process can cause the crossed wires to tear the insulation coating and cause a short circuit. . This risk is increased when the crossed wires are at the point where the loop descends, near the second junction, and near the gate. Thus, these parameters should be taken into account when designing the layout of the IC-substrate combination, designing the bond diagram, or programming the wire bonder for manufacturing.

  Steps 114 and 116, i.e., ball attachment and singulation, are performed after the insulated wire and IC are packaged, so there is no need to change. However, as is standard in the art, packaged ICs should be handled with care to minimize mechanical damage and electrostatic discharge concerns.

  From the above, the above steps provide an IC assembly process that facilitates the use of a bonding wire coated with an insulating material when assembling an IC package while minimizing the changes required for the entire assembly process. It will be understood that.

  The assembled IC package includes a semiconductor device, a substrate to which the semiconductor device is attached, a semiconductor device attached to the substrate with an adhesive or a soldering material, and at least one bond on the semiconductor device called a “die bond pad” A terminal, at least one bonding terminal on a substrate called a “bond finger”, at least one bonded wire connecting the bond pad of the chip to the bond finger in the form of a loop, and a bonding wire; The wire is an insulating bonding wire.

  While preferred embodiments of the invention have been described herein, those skilled in the art will recognize that modifications can be made without departing from the spirit of the invention or the scope of the appended claims.

FIG. 1 is a flowchart for explaining the operation of the wire bonding process. FIG. 2 is a diagram of a wire bonder for producing a ball joint. FIG. 3a illustrates a standard TIP (prior art) for stitch joining. FIG. 3b illustrates a stitch bonded capillary according to the present invention. FIG. 4 is a diagram illustrating the LF2 position that can be assumed in the second bonding. FIG. 5 is a schematic diagram illustrating an improvement in wire density of an IC employing a single row configuration. FIG. 6 is a schematic diagram for explaining the improvement of the wire density of an IC adopting a multi-row configuration. FIG. 7 is a diagram of a free air ball of insulated wires. FIG. 8a is a perspective view of an assembled test kit for testing breakdown voltage. FIG. 8b is a schematic diagram of the electrical connections of the assembled kit described in FIG. 8a. FIG. 8c is a perspective view of a test substrate for supporting an insulated wire during testing. FIG. 9 is a block diagram illustrating a forming tool. FIG. 10 is a diagram illustrating wire regions that become sensitive during the molding process. FIG. 11a is a top view of the bonded IC and substrate combination illustrating the wire crossing region that becomes sensitive during the molding process. FIG. 11b is a side view of the bonded IC and substrate combination illustrating the wire crossing region that is sensitive during the molding process. FIG. 12 is a block diagram of a sample tester that is an alternative to the sample tester shown in FIG. 8a. FIG. 13a is a diagram illustrating a magazine configured to reduce the power of the plasma cleaning process. FIG. 13b illustrates an alternative embodiment of FIG. 13a. FIG. 14a illustrates an alternative embodiment to FIGS. 13a and 13b. FIG. 14b illustrates an alternative embodiment to FIGS. 13a and 13b.

Claims (52)

A method of bonding an integrated circuit (IC) to a substrate using a bonding wire by stitch bonding, wherein the bonding wire is bonded to the IC at one end, and the method includes:
(A) setting a tool change point with a height of 5 mils (about 127 μm) or less;
(B) using the set tool change point to effectively generate a bond at a bonding site on the substrate. The step of effectively generating the joint comprises:
(A) applying a first blow to the joint site to produce the joint;
(B) Retreat to a predetermined height,
(C) applying a second blow to the joint site to strengthen the joint;
The method of claim 1, comprising:   The method according to claim 2, wherein the first and second hits on the joining portion are performed in a shifted manner. A method of effectively bonding a wire to a bonding site,
(A) applying a first blow to the joint site to produce the joint;
(B) retreating to a predetermined height;
(C) applying a second blow to the joint site;
A method characterized by comprising:   5. The method of claim 4, wherein the predetermined height is set such that the bonding wire is cut while retracting to the predetermined height.   The method of claim 4, wherein the bonding wire is an insulated wire.   The method according to claim 4, wherein the second hit is performed deviating from the first hit.   A package integrated circuit (IC) comprising an IC attached to a substrate, wherein the IC is electrically connected to the substrate via a bonding wire, and the bonding wire is bonded to the IC at one end. The package IC is bonded to the substrate at the other end, and at least one of the bonds includes a stitch bond that performs two hits.   9. The package IC according to claim 8, wherein the two hits of the bonding are performed with a shift from each other. A method of constructing a cleaning apparatus for removing contamination from a combined body of an integrated circuit and a substrate bonded using an insulating bonding wire,
(A) setting the cleaning device to a predetermined value for at least one parameter of duration and power;
(B) cleaning the test substrate and the insulating bonding wire sample using the set parameters;
(C) analyzing the cleaned test substrate to determine whether the parameter is high enough to clean contamination of the substrate to provide a contact angle of less than 30 degrees;
(D) analyzing the cleaned insulating bonding wire sample to determine whether the parameter is low enough to not reduce the breakdown voltage of the insulating bonding wire sample by more than 10 percent;
(E) Iteratively repeat the test with a modified value for at least one of the parameters to determine at least one setting that satisfies both steps (c) and (d) Steps,
A method characterized by comprising:   The method of claim 10, wherein the duration that the cleaning device is in operation does not exceed 200 seconds.   The method according to claim 10, wherein the cleaning device is a plasma cleaning device. A method of using a cleaning device to remove contamination from a combination of an integrated circuit and a substrate bonded using an insulating bonding wire,
(A) placing a combined body of the integrated circuit and substrate on a chip carrier;
(B) electrically isolating the chip carrier from the cleaning device;
(C) cleaning the integrated circuit and substrate combination using standard parameters;
A method characterized by comprising:   The method according to claim 13, wherein the cleaning device is a plasma cleaning device.   15. The method of claim 14, wherein the chip carrier is a magazine and a plurality of integrated circuit and substrate combinations are placed in the magazine for simultaneous cleaning.   The method of claim 15, wherein the magazine includes a leg with a separator for electrically isolating the magazine.   The method according to claim 15, wherein the magazine is electrically isolated from the cleaning device by providing an isolation sheet between the magazine and the cleaning device.   The method of claim 17, wherein the isolation sheet is configured to match an installation surface shape of the magazine.   The method of claim 14, wherein the separator comprises a substrate, glass, or ceramic.   16. The method of claim 15, wherein a sufficient spacing is provided between the magazines to maintain a power ratio to sufficient grounding of the plasma electrodes.   16. The method of claim 15, wherein dummy strips are provided at the top and bottom of the magazine.   16. The method of claim 15, wherein adjacent integrated circuit and substrate combinations are evenly spaced.   The method of claim 22, wherein the spacing is provided to reduce hot spots.   The method of claim 23, wherein the spacing is approximately 6 mm.   16. The method of claim 15, wherein the plasma cleaning time is limited to less than 5 minutes to reduce undue damage to the insulating bonding wire.   15. The plasma cleaning apparatus according to claim 14, wherein the plasma cleaning apparatus is an in-line type plasma cleaning apparatus, and the chip carrier transports a combination of the IC and the substrate along a rail of the in-line type plasma cleaning apparatus. The method described.   27. The method of claim 26, wherein the rail comprises an electrode of the in-line plasma cleaning apparatus and the chip carrier is isolated from the rail by a separator.   27. The method of claim 26, wherein the chip carrier is isolated by isolating the rail from an electrode of the in-line plasma cleaner using an isolator.   27. The method of claim 26, wherein the plasma cleaning time is limited to less than 30 seconds to reduce undue damage to the insulating bonding wire.   15. The method according to claim 14, wherein the plasma cleaning step uses an inert gas to suppress a change in surface characteristics of the insulating material.   A chip carrier for supporting at least one combined body of an IC and a substrate bonded using an insulating bonding wire in a cleaning device, wherein the chip is used to reduce the influence of the cleaning process on the insulating bonding wire A chip carrier comprising an isolator configured to electrically isolate the carrier from the cleaning device.   32. The chip carrier of claim 31, wherein the chip carrier is a magazine, and a plurality of IC and substrate combinations are placed in the magazine for simultaneous cleaning.   33. The chip carrier according to claim 32, wherein the magazine includes a leg having the isolator for electrically isolating the magazine from the cleaning device.   The chip carrier according to claim 32, wherein the magazine is electrically isolated from the cleaning device by providing an isolation sheet between the magazine and the cleaning device.   35. The chip carrier according to claim 34, wherein the isolation sheet is configured to match an installation surface shape of the magazine.   32. The chip carrier according to claim 31, wherein the separator includes a substrate, glass, or ceramic.   33. The chip carrier of claim 32, wherein the slots for adjacent integrated circuit and substrate combinations are evenly spaced.   38. The chip carrier according to claim 37, wherein the interval is provided so as to reduce hot spots.   The chip carrier according to claim 38, wherein the distance is approximately 6 mm.   32. The chip carrier according to claim 31, wherein the chip carrier is configured to support a combined body of the IC and the substrate along a rail of an in-line cleaning apparatus.   41. The chip carrier according to claim 40, wherein the rail includes an electrode of the in-line cleaning device, and the chip carrier is isolated from the rail by a separator. An in-line type cleaning apparatus configured to electrically isolate a chip carrier supporting at least one combination of an IC and a substrate bonded using an insulating bonding wire from the cleaning apparatus;
A rail for guiding the chip carrier passing through the in-line cleaning device during a cleaning process, the rail being electrically isolated from an electrode of the cleaning device using a separator; An in-line type cleaning apparatus that reduces the influence of the cleaning step on an insulating bonding wire. A test kit including parts for making a tester for testing a breakdown point of an insulating bonding wire,
(A) a base for supporting the tester;
(B) a pair of conductive rods, one of the rods being electrically connected to the anode of the power source and the other of the rods being electrically connected to the cathode of the power source, a predetermined distance A pair of conductive rods spaced only apart;
(C) a slide for supporting the insulated bonding wire to be tested so that the insulated bonding wire contacts each of the conductive rods;
(D) first connection means for connecting the pair of conductive rods to the base;
(E) second connection means for connecting the insulating bonding wire to the slide;
A test kit comprising: A test apparatus for testing the influence of a wire bonding process on an insulating bonding wire, comprising a substrate having first and second surfaces facing each other, the substrate comprising:
(A) a pair of bonding pads on the first surface for bonding both ends of an insulating bonding wire;
(B) a pair of test points on the second surface that are electrically connected to a corresponding pair of bonding pads to facilitate electrical testing of the insulating bonding wire;
A test apparatus further comprising:   45. The test apparatus according to claim 44, wherein the substrate further includes an IC disposed on the substrate. A combined body of an integrated circuit (IC) and a substrate, wherein the IC and the substrate are electrically connected via an insulating bonding wire bonded therebetween, and the insulating bonding wire is
(A) limited wire loop height;
(B) a geometric configuration that avoids the occurrence of intersections in areas that are susceptible to physical damage during subsequent molding steps;
A combination of an integrated circuit (IC) and a substrate, wherein the insulating bonding wire is configured to be compatible with a forming tool. A method of wrapping a combination of an IC and a substrate including an insulating bonding wire with a molding material using a transfer molding machine when the combination of the IC and the substrate is placed inside a mold,
(A) transferring the molding material into the cavity at an initial flow rate within the mold;
(B) establishing a flow wall within the cavity; then (c) increasing the insertion speed of the molding material to a final flow rate;
A method characterized by comprising:   48. The method of claim 47, wherein the molding material is selected to have a gel time that is at least equal to the time required to encapsulate the IC / substrate combination.   48. The method of claim 47, wherein the molding material is selected to have a relatively small filler size.   48. The method of claim 47, wherein the molding material is selected to have a relatively high proportion of spherical filler particles.   51. The method of claim 50, wherein the percentage is at least 80 percent.   48. The method of claim 47, wherein the insulated bonding wires are configured not to intersect in a region near the gate of the transfer molding machine.