JP2009502041A - Drain extended MOSFETS with diode clamp - Google Patents

Abstract

An upper extended drain MOS driver transistor (T2) is provided. Within this transistor, the extended drains (108, 156) are separated from the first buried layer (120) by a second buried layer (130). Note that an internal or external diode (148) is coupled between the first buried layer (120) and the extended drains (108, 156) to increase the breakdown voltage.
[Selection] Figure 3A

Description

  The present invention relates generally to semiconductor devices, and more particularly to extended drain MOS transistor devices and methods of manufacturing the same.

  Power semiconductor products are often N or P, such as lateral diffused MOS (LDMOS) devices or reduced surface field (RESURF) transistors, for high power switching applications. Channel drain extended metal oxide semiconductor (DEMOS) transistor device. DEMOS devices advantageously have short channel operation, high current handling capability, relatively low drain-to-source on-state resistance (Rdson), and high blocking voltage without suffering voltage breakdown failure. Combine the ability to endure. The breakdown voltage is generally measured as the breakdown voltage from the drain to the source with the gate and source shorted together (BVdss) (where DEMOS device designs are often referred to as breakdown voltage BVdss). And a trade-off between Rdson). In addition to operational advantages, DEMOS device manufacturing is relatively easy to assemble into a CMOS process flow and can be a single integrated circuit (IC), whether in logic, low power analog, or other circuits. Facilitates use in devices that are to be manufactured in-house.

  N-channel drain extended transistors (DENMOS) are asymmetric devices often formed of n-wells with p-wells (sometimes called p-bodies) formed in n-wells. An n-type source is formed in the p-well. Here, the p-well provides a p-type channel region between the source and the extended n-type drain. The extended drain generally includes an n-type drain implanted into the n-well and a drift region in the n-well extending between the channel region and the drain. Low n-type doping on the drain side provides a large depletion layer with high blocking voltage capability. Here, the p-well is generally connected to the source by a p-type back gate connection to prevent the p-well from floating, thereby stabilizing the element threshold voltage (Vt). The device drain region is spaced (eg, extended) from the channel and provides a drift region or drain extension in the n-type semiconductor material therebetween. In operation, drain-channel spacing spreads out the electric field, thereby increasing the breakdown voltage rating of the device (high BVdss). However, because drain extension increases the resistance (Rdson) of the current path from drain to source, DEMOS device designs often involve a trade-off between high breakdown voltage BVdss and low Rdson.

  DEMOS devices have been widely used for power switching applications that require high blocking voltages and high current carrying capabilities, especially when solenoids or other inductive loads are to be driven. . In one common configuration, two or four n-channel DEMOS elements are arranged as half or full “H-bridge” circuits to drive the load. In a half H bridge arrangement, two DEMOS transistors are coupled in series between supply voltage VCC and ground, with the load coupled to ground from an intermediate node between the two transistors. In this configuration, the transistors between the intermediate node and ground are referred to as “low-side” transistors, and the other transistors are referred to as “high-side” transistors. Here, these transistors are activated alternately to provide current to the load. In a full H-bridge driver circuit, two upper drivers and two lower drivers are provided with the load coupled between two intermediate nodes.

  In operation, the upper DEMOS has a drain coupled to the supply voltage and a source coupled to the load. In the “on” state, the upper driver conducts current from the power supply to the load. Here, the source is essentially pulled up to the supply voltage. In general, DEMOS devices are manufactured with a wafer having a p-doped silicon substrate and an epitaxial silicon layer formed over the substrate. Here, the substrate is grounded and the source, drain and channel of the transistor (eg, including n-well and p-well) are formed in the epitaxial silicon. Therefore, in order to prevent punch-through current between the p-well and the substrate, the p-well surrounding the source is isolated from the grounded and underlying p-type substrate in the on state for the upper DEMOS device. Is desirable. The n-well can extend below the p-well, but the n-well is generally only lightly doped and is therefore suitable for on-state punch-through current from the source to the substrate. Does not provide a barrier. Therefore, prior to forming the epitaxial silicon layer to isolate the n-well from the substrate, and therefore to inhibit the on-state punch-through current from the p-well to the substrate in the upper DEMOS driver, A heavily doped n-buried layer (eg, NBL) is often formed in the substrate.

  The n-buried layer operates to prevent on-state punch through current, but NBL limits the off-state breakdown voltage rating of the upper DEMOS driver. In the “off” state, the upper driver is essentially pulled to ground while the lower driver conducts. Here, the drain-to-source voltage across the upper DEMOS is essentially the supply voltage VCC. In high voltage switching applications, the presence of the n buried layer under the p well limits the breakdown of the device from drain to source. This is because the n buried layer is tied to the drain at VCC. In this state, the source is low in the off state so that the p-well is at ground, and the supply voltage VCC is between the bottom of the p-well and the n-buried layer and on the channel side of the p-well. Between the drain and the drain, essentially dropped over the extended n-well portion. Further, as the upper driver is shut off when driving an inductive load, the transient drain-to-source voltage can increase above the supply voltage level VCC.

  In these situations, the lateral spacing of the drain from the p-well can be adjusted to avoid breakdown from the p-well to the drain. However, the vertical spacing between the bottom of the p-well and the n-buried layer is more difficult to increase. One approach is to increase the thickness of the epitaxial silicon layer. However, this is costly in terms of process complexity, especially in terms of forming a deep diffusion to connect the n-buried layer to the drain. Accordingly, an improved DEMOS driver and method of manufacture, which provides increased voltage breakdown capability without increasing epitaxial silicon thickness and sacrificing device performance. There is a need for a manufacturing method that can be realized.

  The present invention is an n- or p-channel drain extended MOS (DEMOS) transistor and method of manufacture, wherein the extended drain is separated from the first buried layer and is internal or external. Related to the manufacturing method coupled there by the diode. The present invention facilitates increased breakdown voltage operation of upper drivers and other DEMOS devices without requiring a thicker epitaxial silicon layer and without adversely affecting Rdson. With minimal changes to existing manufacturing process flows, increased driver operating voltages can be realized. The first buried layer can be separated from the extended drain by a second buried layer of opposite conductivity type formed prior to epitaxial growth. The diodes are separated in the epitaxial layer with a connection from the anode to the first buried layer and a connection from the cathode to the extended drain (formed in the interconnect or metallization layer) ( separately). Alternatively, an external connection can be formed to couple an external diode between the first buried layer and the extended drain.

  The present invention provides an improved DEMOS transistor and a manufacturing method therefor. These allow high breakdown voltage ratings to be achieved without increasing the epitaxial silicon thickness. Here, the buried layer is a diode coupled to the extended drain. The transistors and methods for the present invention are not limited to the following applications, but the present invention finds particular utility in applications with upper driver transistors in full or half bridge circuits. Since p-doped regions can be replaced with n-doped regions, and vice versa, PMOS implementations are also possible, but various features of the invention will be described in the context of NMOS driver transistors hereinafter. Explained and described in In addition, the following exemplary devices are formed using a semiconductor body having a silicon substrate and an epitaxial silicon layer thereon, including but not limited to standard semiconductor wafers, SOI wafers, etc. Other semiconductor bodies can be used. Here, all such modified implementations are considered to be within the scope of the present invention and its claims.

  FIG. 1 shows a full H-bridge driver semiconductor device 102 powered by a DC power supply VCC. In this, various features of the present invention can be implemented. Referring to FIG. 6E, as shown and described below, the semiconductor device 102 includes four driver transistors TT4 and connections for the power supply, gate signal, and load terminal, and the upper side. It can be constructed as a single IC 102a with external connections that can optionally provide connections for external diodes for drivers T2 and / or T3. FIG. 6F shows another possible device 102b having a single upper driver provided in an IC having drain, source, gate, back gate, and external connections for optional anode connections. . Alternatively, the present invention can be employed in other integrated circuits having any number of components therein. Here, an extended drain MOS transistor with a high breakdown voltage is desirable.

  As shown in FIG. 1, exemplary element 102 includes corresponding sources S1-S4, drains D1-D4 coupled in an H-bridge to drive a load coupled between intermediate nodes N1 and N2. , And four n-channel / drain extended MOS (DEMOS) elements T1-T4 each having gates G1-G4. Transistors T1-T4 are as two sets of lower and upper drivers (T1 & T2 and T4 & T3), where the load is coupled between the two sets of intermediate nodes to form an “H-shaped” circuit. Arranged. The half-bridge driver circuit can be implemented using transistors T1 and T2 such that the right hand node n2 of the load is coupled to ground (where T3 and T4 can be eliminated). In one example, for applications in automobiles, portable electronic devices, etc., the supply voltage VCC can be the positive terminal of the battery source and ground can be the negative terminal of the battery.

  On the left side of the H-bridge in FIG. 1, the lower driver T1 and the upper driver T2 are coupled in series between the power supply VCC and ground, and the other sets T4 and T3 are similarly connected. Upper driver transistor T2 has a drain D2 coupled to VCC and a source S2 coupled to an intermediate node N1 and a load. Lower transistor T1 has a drain D1 coupled to node N1 and a source S1 coupled to ground. The node N1 between the transistors T1 and T2 is coupled to the first terminal of the load, and the other load terminal N2 is coupled to the other transistor sets T3 and T4. Here, the load is generally not a set of elements 102. The upper and lower transistor gates G1-G4 are controlled to drive the load in an aletrnating manner. When transistors T2 and T4 are on, current flows in the first direction (to the right in FIG. 1) through the upper transistor T2 and the load. And when both transistors T3 and T1 are on, current flows in the second opposite direction through the load and lower transistor T1.

  In order to understand one or more of the problems of conventional DEMOS transistors in applications such as the H-bridge of FIG. 1, FIGS. 2A and 2B show a semiconductor device having a conventional upper DEMOS transistor 3. 2 is shown. Here, FIG. 2B shows an equipotential voltage line in the drift region of the upper driver 3 in the off state (for explaining its breakdown voltage limitation). To facilitate an understanding of the possible advantages of the present invention, a conventional upper driver transistor 3 is briefly described below in the context of an H-bridge driver circuit. Here, the DEMOS transistor 3 can be coupled to drive a load in a full or half bridge driver circuit configuration, such as T2 in the H bridge circuit of FIG.

  As shown in FIG. 2A, device 2 includes a p-doped silicon substrate 4 (on which an epitaxial silicon layer 6 is formed). An n buried layer (NBL) 20 is located in the substrate 4 below the upper device 3 and partially extending into the epitaxial silicon 6. The n-well 8 is implanted with n-type dopant into the epitaxial silicon 6 above the n-buried layer 20 and a p-well or p-body 18 is formed in the n-well 8. A field oxide (FOX) isolated structure 34 is formed in the upper portion of the epitaxial silicon 6 between the transistor element terminals of the lower and upper transistors 1 and 3. A p-type back gate 52 and an n-type source 54 are formed in the p-well 18 and an n-type drain 56 is formed in the n-well 8. The gate structure is formed on the channel portion of the p-well 18 including the gate oxide 40 and the gate electrode 42. Here, the gate G2, source S2, and drain D2 of the conventional upper DENMOS transistor 3 are labeled to form a half or full H-bridge as in FIG. (labeled).

  In such driver applications, the upper element 56 is connected to the supply voltage VCC and the source 54 is connected to the load at the intermediate node N1. When the upper transistor 3 is on, both the source 54 and the drain 56 are at or near the supply voltage VCC. Here, the n-buried layer 20 helps prevent punch-through current from flowing between the p-well 18 and the grounded p-type substrate 4 (where the n-buried layer 20 is the drain Tied to 56 (eg to VCC). However, when the upper transistor 3 is off, the source 54 is pulled from the drain across the upper DENMOS 3 by “pulsating” essentially through the lower transistor to the ground. Is essentially the supply voltage VCC. Furthermore, when switching from the on state to the off state, if the load is inductive, the upper driver 3 can experience a transient drain-to-source voltage greater than VCC. FIG. 2B shows equipotential voltage lines in the drift region of the n-well 8 of the upper transistor 3 in the off state. At such a high drain-to-source voltage level, a high electric field is generated in regions 21 and 22 (where equipotential lines are closely spaced). Here, the upper driver 3 is shown in FIG. 2B with Vds just below the breakdown level.

  The inventor has found that these regions 21 and 22 are at a higher supply in the off state of the upper driver, due at least in part to the n buried layer 20 located beneath the n well 8. I understand that it is susceptable to voltage. Here, the breakdown voltage BVdss of the conventional DENMOS 3 described is relatively low. Thus, the n-buried layer 20 inhibits the on-state punch through current from the p-well 18 to the substrate 4, while the off-state breakdown voltage BVdss of the upper driver 3 is limited by the presence of NBL 20. In this regard, the inventor has shown that the presence of the n-buried layer 20 at the drain potential (VCC) indicates that the high drain-to-source voltage level, particularly the equipotential of FIG. 2C in regions 21 and 22 of FIG. 2C. We understand that it contributes to the crowding of lines. Without design changes, the supply voltage VCC cannot be increased without the risk of off-state or transient voltage breakdown. One approach is to reduce the n-well 8 dopant density for improved breakdown voltage performance. However, this approach adversely affects on-state drive current by increasing Rdson. Another approach is to increase the thickness of the epitaxial silicon layer 6. However, as described above, manufacturing a thicker epitaxial layer 6 causes process complexity and may not be feasible beyond a certain amount.

  The present invention provides a DEMOS transistor that facilitates an improved breakdown voltage rating without increasing the thickness of the Rdson or epitaxial silicon layer. In this way, the present invention facilitates the use of such devices in new applications that require higher supply voltages, including but not limited to full or half H-bridge configurations as in FIG. While avoiding or mitigating the normal trade-off between Rdson and BVdss in drain-extended MOS devices without significant changes in existing manufacturing process flow. 3A-3C illustrate an exemplary DENMOS upper driver transistor T2 in the H-bridge driver element 102 of FIG. Here, the n-buried layer 120 is separated from the extended drain of the device by a p-buried layer 130. A diode 148 is then coupled between the n-buried layer 120 and the drain ions to increase the breakdown voltage without the need to increase the epitaxial thickness. Described in the context of a DENMOS upper driver formed in a semiconductor body having a silicon substrate and an epitaxial silicon layer disposed thereon, for example, a PMOS implementation, manufactured using other semiconductor body structures. Other implementations are possible within the scope of the present invention, such as transistors, other drain extended MOS transistors (eg, RESURF devices, etc.) and / or transistors not employed in upper driver applications. is there. Further, as described below, a diode 148 can be incorporated within the element 102 or can be external.

  As illustrated in FIG. 3A, the device 102 is formed in a semiconductor body comprising a p-doped silicon substrate 104 and an epitaxial silicon layer 106 formed on the substrate 104. Prior to the formation of epitaxial silicon 106, an n-buried layer (NBL) 120 is formed (eg, implanted or diffused) in the substrate 104 under the prospective upper driver region. Then, a p-buried layer (PBL) 130 is formed over the n-buried layer in the upper driver region (eg, implantation), so that the p-buried layer 130 becomes an n-buried layer. Located between 120 and the upper DENMOS transistor T2 above it. Here, some of the implanted p-type dopant of the p-buried layer 130 may be directed upward during its epitaxial growth and / or during subsequent manufacturing process steps in which thermal energy is applied to the device 102. Can diffuse into the epitaxial silicon 106. Further, the p-buried layer 130 may prevent or inhibit upward diffusion of the n-buried layer 120 n-type dopant during such heat treatment.

  Transistor T2 also includes an n-well 108 implanted with an n-type dopant (eg, arsenic, phosphorous, etc.) in epitaxial silicon 106, and a p-well or p-body 118 formed in n-well 108. A field oxide (FOX) structure 134 is formed in the upper portion of the epitaxial silicon 106 between the transistor source, drain, and back gate terminal. Other implementations are possible, for example, where the back gate can be connected directly to the source. Here, the isolation structure is formed using a shallow trench isolation (STI) technique, a deposited oxide, or the like. Here, a diode (eg, diode 148) coupled between, having a first buried layer (eg, NBL 120) separated from DEMOS by a second buried layer (eg, PBL 130) of the opposite conductivity type. All such alternative implementations, including) are to be construed as falling within the scope of the invention and the appended claims.

  Transistor T2 includes a p-type back gate 152 and an n-type source 154 formed in p-well 118, and an n-type drain 156 formed in the n-well. Here, a portion of the n-well 108 between the drain 150 and the p-well 118 provides a drain extension or (or) drift region. Thus, transistor T3 includes an extended drain with the drift region of n-well 108 and drain 56. In operation, the back gate 152 can be coupled to the source 154 in an overlying metallization layer (not shown), but this is not necessary. In a possible alternative implementation, the field oxide (FOX) structure 134 between the back gate 152 and the source 154 may be eliminated due to the direct connection of the back gate 152 to the source 154. A gate structure including gate oxide 140 and gate electrode 142 is formed over the channel portion of p well 118 and over the drift region portion of n well 108. There, the portion of the gate electrode 142 further extends over the field oxide structure 134 above the drain extension or drift region of the n-well 108 in the exemplary transistor T2.

  In a half or full H-bridge load driver configuration, drain 156 is connected to supply voltage VCC along with the cathode of internal or external diode 148. Source 154 is then coupled to the load at intermediate node N1 in FIG. In the on state of the upper DENMOS transistor T2, the source 154 is pulled to the vicinity of the supply voltage VCC. Here, the n-buried layer 120 helps prevent punch through current from flowing between the p-well 118 and the grounded p-type substrate 104. In the off state, most of the supply voltage VCC appears between the drain 156 and the source 154. However, unlike a conventional upper driver (wherein the n-buried layer (eg, NBL 20 in FIG. 2A) is coupled to the drain), the p-buried layer 130 causes the exemplary device 102 to Inner n buried layer 20 is isolated from the extended drain (eg, from the drain region of drain 156 and n well 108). Here, diode 148 is coupled between the n-buried layer 120 and the extended drain. Thus, the off-state voltage potential of the n-buried layer 120 is lower than VCC.

  The presence of the lower n buried layer potential and the intervening p buried layer resulted in a significantly different field profile in the device in the off state compared to the field profile of a conventional upper driver. FIG. 3B shows the upper element T2 at a high drain-to-source voltage that is about 60% higher than the voltage of FIG. 2B above without voltage breakdown. Here, the n-buried layer 120 is at a lower voltage than the drain 156. Here, a portion of the supply voltage appears across the diode 148. In this example, the design parameters (eg, dimensions, dopant concentration, etc.) of the exemplary upper DENMOS transistor T2 are essentially the same as the conventional device 3 of FIG. 2A, except that the p-buried layer 130 and the diode. 148 has been added. Thus, the addition of diode coupling in the p-buried layer 130 and the n-buried layer 120 and the extended drain operate at higher supply voltage VCC without suffering off-state voltage breakdown. To make it easier. Here, BVdss is sufficiently increased without increasing the epitaxial silicon thickness and without changing Rdson.

  3C shows the drain current (Id)... For the conventional upper DENMOS 3 of FIG. 2A and the exemplary upper DENMOS transistor T2 of FIG. 3A, respectively. vs. A graph 160 illustrating the drain-to-source voltage (Vds) curves 162 and 164 is provided. As can be seen in graph 160, transistor T3 of FIG. 3A can be safely operated at higher voltages without breakdown. Here, the corresponding BVdss 164 is 60% or more larger than the BVdss 162 of the conventional upper DENMOS 3 of FIG. 2A. Thus, the separation of the n-buried layer 120 from the extended drains 156, 108, and the coupling of the diode 148 therebetween provides a sufficiently higher breakdown voltage, and the epitaxial silicon layer 106 Allows use at higher supply voltage VCC without increasing the thickness and without a significant adverse impact on Rdson.

In a preferred implementation, the n-well 108 is depleted between the p-well 118 and the p-buried layer 130 because the dopant concentration of the n-buried layer 120 is higher than the concentration of the p-buried layer 130. When depleted, on-state punch through current is prevented from flowing between the p-well 118 and the p-type substrate 104. In one example, p-buried layer 130 is about 5E15 cm ^-3 or greater, and, with about 5E17 cm ^-3 or less of peak dopant concentration. Here, n-buried layer 120 is about 1E17 cm ^-3 or greater, and has about 1E20 cm ^-3 or smaller peak concentration than that, n peak concentration of buried layer is, p-buried layer Higher than 130 peak concentration.

  Another feature of the present invention is a method for semiconductor device fabrication that can be used to fabricate devices having NMOS and / or PMOS extended drain transistors with improved breakdown voltage performance. I will provide a. In this aspect of the invention, a first conductivity type first buried layer is implanted into the substrate and a second conductivity type second buried layer is then implanted. An epitaxial silicon layer is formed on the implanted substrate. A drain extended MOS transistor is then formed on the second buried layer in the epitaxial silicon layer. Here, the extended drain of the transistor is isolated from the first buried layer. The method may include forming a diode in the epitaxial layer and coupling the first buried layer to the extended drain, or alternatively, the first buried layer and the extended drain. Forming an external connection to (to couple an external diode therebetween).

  FIG. 4 illustrates an exemplary method 202 for fabricating semiconductor devices and DEMOS transistors in accordance with this aspect of the invention, and FIGS. 5A-5H generally illustrate the case where an internal diode 148 is provided, FIG. 5 illustrates an exemplary semiconductor device 102 at various stages of manufacture, according to the method 202 of FIG. 6A-6D show the fabrication of another implementation of element 102 and method 202. FIG. Here, a connection is provided for the external diode 148. Other methods of the present invention can be employed to form PMOS devices where p-type dopants are substituted for n-type dopants and vice versa. Further, the method 202 may form a device with an internal diode for coupling the first buried layer to the extended drain of the DEMOS transistor and / or the first buried layer and It can be employed to fabricate devices that have externally accessible connections to couple external diodes between the extended drains. Here, all such implementations are construed as falling within the scope of the invention and the appended claims.

  In the following, the exemplary method 202 is described and described as a series of operations or events, while it should be construed that the present invention is not limited by the described order of such operations or events. For example, some operations may occur in a different order and / or simultaneously with other operations or events, apart from those described herein and / or described herein, in accordance with the present invention. Can do. Furthermore, not all of the steps described for carrying out the method according to the invention are necessary. Furthermore, the method according to the invention can be carried out in connection with the manufacture of the elements described and described herein and in connection with other elements and structures not described.

  The method 202 begins at 204 in FIG. An n-buried layer (eg, NBL) is then implanted into the substrate at 206, which can optionally be diffused at 208. In the exemplary semiconductor device 102, for the upper device T2, an n-buried layer 120 in the driver region 112 is provided, and the n-buried layer 120 is a separate n-buried in the diode region 111. Other portions within device 102, including layer 120a, can also be implanted. In FIG. 5A, the element 102 exposes a portion of the upper surface of the substrate 104 where it will be the upper driver region 112, while covering a portion of the location where it will be the internal diode region 111. Illustrated with an NBL implant mask 302 formed over a portion of the silicon substrate 104. An implantation process 304 is performed with the mask 302 in place to implant an n-type dopant (eg, phosphorous, arsenic, etc.) into the exposed portion of the substrate 104, thereby providing a driver region 112 (eg, A first buried layer 120 of the first conductivity type is formed, and a separate n buried layer 120 a is formed in the diode region 111. A diffusion anneal (not shown) may optionally be performed at 208 to drive n-type dopant further into the substrate 104, thereby causing the n-buried layers 120, 120a to initially and downwardly and laterally. Expands outward from the injected region.

  In 210 of FIG. 4, a second buried layer of a second conductivity type is implanted (eg, p-buried layer 130 in device 102), which can optionally be diffused at 212. In FIG. 5B, a mask 312 is formed that exposes a portion of the n-buried layer 120 where it will be the upper region 112. An implantation process 314 is then performed to provide a p-type dopant (eg, boron) in the exposed portion of the substrate 104. As shown in FIG. 5B, the exemplary p-buried layer 130 in the upper region 112 is disposed within the n-buried layer 120 in the device 102. Note that at 212, another diffusion anneal may optionally be performed to drive the implanted p-type dopant laterally and downwardly to expand the p-buried layer 130.

  As 214 in FIG. 4, an epitaxial growth process is performed to grow the epitaxial silicon layer 106 on the substrate 104. At 214, any suitable epitaxial growth processing may be employed (in this step, the epitaxial silicon layer 106 is formed on the upper surface of the substrate 104). In FIG. 5C, an epitaxial silicon layer 106 is formed on the substrate 104 “via” process 322. It should be noted that the thermal energy associated with the epitaxial growth process 322 causes the p-buried layer 130 portion to diffuse into the epitaxial silicon 106 by causing diffusion above the p-type dopant portion of the p-buried layer 130. Expand. Similarly, the end portion of the n-buried layer 120 may diffuse into the epitaxial silicon 106 outside and above the upper driver region 112. The n-buried layer 120a in the diode region also extends into the epitaxial silicon 106 on the upper side. However, both during and after the epitaxial process 322 at 214, the p-buried layer 130 generally limits the upward diffusion of at least a portion of the n-buried layer 120 in the upper driver region 112. Alternatively, blocking and providing a physical barrier between the n-buried layer 120 and the later formed extended drain of DEMOS (eg, drain 156 and n-well 108 in FIG. 3A).

  At 216, in the upper region 112, an n-well is implanted into the epitaxial silicon 106, which can then be thermally diffused at 218. Either before or after the n-well formation at 216, a deep n-type diffusion (eg, a sinker) is formed in the epitaxial silicon 106 to provide a connection to the n-buried layer 120. . In FIGS. 5D and 6A, a mask 324 is formed over the epitaxial layer 106 and an n-type implant 326 is performed with thermal diffusion annealing (not shown) to n n regions n within the region 111. Form a sinker 107 connection. 5E and 6B, a mask 332 is formed that exposes all or a portion of the portion that will become the upper driver region 112, and an implant 334 is performed to form an n-well 108 therein (eg, in FIG. 5E). n wells 108a-108c and n well 108 in FIG. 6B). If the internal diode 148 is to be formed in the device 102, the mask 332 exposes two portions of the diode region 111, as shown in FIG. 5E, so that the implant 218 underlies the diode region. Form cathode n-wells 108a and 108c that extend to n-buried layer 120a in 111 and also form DEMOS n-well 108b in upper driver region 112, after which thermal diffusion annealing is employed at 218. obtain.

  At 220, a p-well or p-base region 118 is implanted into a portion of transistor n-well 108. This step may be followed by another thermal diffusion anneal (not shown). FIG. 5F shows the case for the internal diode 148. Note that a mask 342 is formed to expose the locations in the DEMOS n well 108b and in the diode region 112 between the n wells 108a and 108c that are to become the p well region of the epitaxial layer 106. An implantation process 344 is then performed to form an internal diode 148 and a transistor p well 118b in the epitaxial layer 106 by forming an anode p well 118a. The n well 108b extends below the p well 118b between the p well 118b and the p buried layer 130. In this configuration, n wells 180a and 108c and diode region n buried layer 120a serve to isolate diode p well 118a from the remainder of epitaxial layer 106 and from p substrate 104. FIG. 6C shows the case where an external diode 148 is used. Note that a single p well 118 is formed in the transistor n well 108 (mask 342 covers region 111). An implantation process may be employed to form any buried layers 120, 130 and wells 108, 118 within the scope of the present invention. In this case, a dedicated diffusion anneal may optionally be performed following any or all of the implants or without any implants. It is noted that all such corrective injections are considered to fall within the scope of the present invention.

  In 222 of FIG. 4, the isolation structure 134 is formed using any suitable technique such as local oxidation of silicon (LOCOS), shallow trench isolation technique (STI), deposited oxide, and the like. . As shown in FIG. 5G, in the exemplary device 102, field oxide (FOX) structures 134 are formed for both the diode and the upper regions 111 and 112, respectively. As shown in FIGS. 5H and 6D, a thin gate oxide 140 is formed on the top surface of the device, for example, by thermal oxidation processing (eg, at 224 in method 202). Then, at 226, a gate polysilicon layer 142 is deposited over the thin gate oxide 140. Gate oxide 140 and polysilicon 142 are patterned at 228 to form a gate structure that extends over the channel region of p-well 118b in FIG. 5H (p-well 118 in FIG. 6D).

  With the patterned gate structure formed, LDD and / or MDD implants may be performed, and at 230, sidewall spacers are formed along the lateral sidewalls of the patterned gate structure. . At 232, source and drain regions 154 and 156 are implanted with n-type dopants. Then, at 234, the back gate 152 is implanted with a p-type dopant. It should be noted that any suitable mask and implantation process may be used in forming the n-type source 154 and drain 156, and the p-type back gate 152. Silicide, metalization, and other back-end processing are then performed at 236 and 238, respectively, of the gate 142, source 154, drain 156, and DEMOS transistor T2. In the first pre-metal dielectric (PMD) layer 174 (on the p-type anode 118a and n-type cathode 118a in the case of the internal diode 148 (FIG. 5H)) above the back gate 152, A conductive metal silicide material 172 and a conductive plug 178 (for example, tungsten) are formed.

  At 240, an additional metallization layer (not shown) is then formed to create a multi-level interconnect routing structure. Thereafter, the method 202 ends at 240 in FIG. In the case of an internal diode, an n-buried layer 120 is coupled with an anode p-well 118a through an n-type sinker 107 and a conductive contact plug 178 (on the sinker 107 and anode 118a) to form a conductive contact plug. The 178 may then be connected with an overlying metallization layer, as shown schematically in FIG. 5H. If an external diode 148 is used, an external anode connection is provided from the metallization routing to connect the diode 148 to the n-buried layer 120. Then, as shown in FIG. 6D, an external drain connection is provided from D2 to connect to the cathode of diode 148.

  FIGS. 6E and 6F show possible completed semiconductor elements 102a and 102b (providing external connections to the anode and cathode of external diode 148), respectively. FIG. 6E shows an external for coupling diodes 148a and 148b between the n buried layer 120 (anode) and the extended drains (cathodes) of upper driver DEMOS transistors T2 and T3, respectively, according to the present invention. 2 shows an exemplary single chip implementation 102a of the full H-bridge circuit element of FIG. 1 with diode connections. FIG. 6F illustrates another exemplary comprising a single upper driver transistor (eg, T2) having an external anode connection for coupling between the n-buried layer 120 and the drain 156 of the external diode 148. Element 102b is shown.

  Although the invention has been described and described in connection with one or more implementations, alternatives and / or modifications to the described examples may be made without departing from the scope of the invention. Can be made.

Full H-bridge circuit element for driving a load using two sets of lower and upper drain extended NMOS elements, in which one or more features of the present invention may be implemented FIG. It is a partial side elevation view of a portion showing a conventional upper DENMOS transistor. 2B is a side elevation view of the conventional upper transistor of FIG. 2A showing equipotential voltage lines in the drift region and in a region that tends to break down at high voltages from drain to source in the off state. An exemplary upper DENMOS transistor with a p-buried layer that separates the extended drain from the underlying n-buried layer, and n with an extended drain, according to one or more features of the present invention. FIG. 6 is a partial side elevational view of a portion showing a diode clamp coupling a buried layer. FIG. 3B is a front view of the exemplary high-side DENMOS transistor of FIG. 3A showing equipotential voltage lines in the drift region in the off state. To show the relative breakdown voltage performance for the upper DENMOS driver transistor of FIGS. 2A and 3A, the drain current (Id). versus. It is a graph which shows the voltage (Vds) curve from a drain to a source. FIG. 6 illustrates an exemplary method of manufacturing a semiconductor device and its upper DENMOS driver transistor according to the present invention. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. In the part illustrating the exemplary implementation of the upper DENMOS driver transistor of FIG. 3A with an internal diode coupling the n-buried layer with an extended drain, shown generally at various stages of manufacture by the method of FIG. It is a partial side elevation view. Overall, the upper DENMOS driver of FIG. 3A with an external connection for coupling an external diode between the n-buried layer and the extended drain, shown at various stages of manufacture, according to the method of FIG. -A partial side view in part showing another possible implementation of the transistor. Overall, the upper DENMOS driver of FIG. 3A with an external connection for coupling an external diode between the n-buried layer and the extended drain, shown at various stages of manufacture, according to the method of FIG. -A partial side view in part showing another possible implementation of the transistor. Overall, the upper DENMOS driver of FIG. 3A with an external connection for coupling an external diode between the n-buried layer and the extended drain, shown at various stages of manufacture, according to the method of FIG. -A partial side view in part showing another possible implementation of the transistor. Overall, the upper DENMOS driver of FIG. 3A with an external connection for coupling an external diode between the n-buried layer and the extended drain, shown at various stages of manufacture, according to the method of FIG. -A partial side view in part showing another possible implementation of the transistor. 2 is a top view showing a single chip implementation of the full H-bridge circuit element of FIG. 1 with external diode connections according to the present invention. FIG. FIG. 6 is a top view showing an implementation of a single upper driver transistor with external connections for an external diode according to the present invention.

Explanation of symbols

T1, T2, T3, T4 n-channel drain extended MOS (DEMOS) element 102 full H-bridge driver semiconductor element

Claims (14)

A source of a first conductivity type formed in a semiconductor body;
A drain of a first conductivity type laterally spaced from the source in the semiconductor body;
A drift region of a first conductivity type disposed between the drain and the source in the semiconductor body;
A channel region of a second conductivity type that extends between the drift region and the source in the semiconductor body, wherein the drift region extends between the channel region and the drain. Yes,
A gate disposed on the channel region;
A first buried layer of the first conductivity type disposed below the source, channel region, and drift region, the first buried layer extending from the drift region; And are separated from the drain, and
A diode having an anode coupled to the first buried layer and a cathode coupled to at least one of the drift region and the drain;
A drain extended MOS transistor comprising: A second buried layer of a second conductivity type disposed under the source, the channel region, and the drift region, wherein the second buried layer is the first buried layer; Separating a buried layer from the drain and the drift region, and separating the diode from the second buried layer;
The transistor of claim 1, further comprising: The semiconductor body includes a silicon substrate and an epitaxial silicon layer formed on the silicon substrate, and the source, the drain, the channel region, and the drift region are in the epitaxial silicon layer. Disposed and at least a portion of the second buried layer is disposed within the silicon substrate;
The transistor according to claim 2.   The transistor of claim 3, wherein the diode is formed in the epitaxial silicon layer.   The transistor of claim 2, wherein the first buried layer is disposed under at least a portion of the second buried layer. A first well of the first conductivity type extending into the semiconductor body under the source, the drain, and the channel;
The second buried layer is disposed under the first well;
The transistor according to claim 2. A second well of the second conductivity type disposed within the first well, the second well extending under the source and the gate, the first well A portion extends between the second well and the second buried layer;
A transistor according to claim 6.   The transistor of claim 1, wherein the diode is formed in the semiconductor body.   The transistor of claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.   The transistor according to claim 1 or 2, wherein the transistor comprises a drain-extended MOS transistor. A method for manufacturing a semiconductor device, comprising:
Prepare a silicon substrate,
Implanting a first buried layer of a first conductivity type into the silicon substrate;
Implanting a second buried layer of a second conductivity type into the silicon substrate;
After implanting the second buried layer, forming an epitaxial silicon layer on the silicon substrate; and
A drain extended MOS transistor is formed on the second buried layer in the epitaxial silicon layer, and the drain extended MOS transistor is separated from the first buried layer. And including an extended drain of the first conductivity type,
Including methods. Forming an external connection to the first buried layer and the extended drain to couple an external diode between the first buried layer and the extended drain; In addition,
The method of claim 11. Forming a diode in the epitaxial silicon layer, the diode comprising an anode and a cathode;
Coupling the anode to the first buried layer; and
Coupling the cathode to the extended drain;
The method of claim 11, further comprising a step.   The method of claim 11, wherein the first conductivity type is n-type and the second conductivity type is p-type.

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