JP2009302644A - Receiver for spread spectrum communication - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a receiver for spread spectrum communication which are simultaneously receivable from a plurality of transmissions, without having to use a multi-bit A/D. <P>SOLUTION: The receiver for spread spectrum communication is provided with: a quadrature detection part 200, which comprises a first multiplier 52 for multiplying a 1 bit quantization signal 49 and a first reference phase signal generated by an oscillator 50; a first accumulator 54 for accumulating outputs of the multiplier 52; a first ternary converter 56 for performing ternary conversion to output of the first accumulator 54; a phase shifter 51 for performing π/2 phase shifting to a first reference phase signal, to generate a second reference phase signal orthogonal to the first reference phase signal; a second multiplier 53 for multiplying the quantization signal 49 and the second reference phase signal; a second accumulator 55 for accumulating the outputs of the second multiplier 53 for accumulating outputs of the second multiplier; and a second ternary converter 57 for performing ternary conversion on the outputs of the second accumulator 55; and a despreading part 300 for performing despreading to signals ternary converted that are outputted by the first and second ternary converters 56 and 57. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a receiver for direct spread spectrum communication, and more particularly to a digital demodulator circuit for applications with a small number of simultaneous accesses.

Currently, spread spectrum communication technology is actively applied to mobile communications, and among them, CDMA (code division multiple access), which is a multiple access method using a direct spreading method, is used. Yes.
In this multiple access method, an A / D converter having the number of A / D bits corresponding to the equal power control and the number of simultaneous accesses is required.
Under such circumstances, for example, a low-cost and small-sized “for a vehicle electronic key system with a small number of simultaneous accesses” shown in the in-vehicle device remote control system disclosed in Japanese Patent Application Laid-Open No. 2008-92267. Development of a "spread spectrum receiver" is also desired.

Japanese Patent Laid-Open No. 7-183831 (Patent Document 1) shows one of the conventional examples that realize the low cost without using the multi-bit A / D converter while retaining the characteristics of the spread spectrum communication. There are digital communication devices.
In Japanese Patent Application Laid-Open No. 7-183831, a multi-bit A / D converter used for digital demodulation of phase shift keying (PSK) is quantized by 1 bit with a directly spectrum spread signal. A digital communication device that can perform sampling and communication equivalent to multi-bit quantization using a 1-bit A / D converter (comparator) is described.
Japanese Patent Laid-Open No. 7-183831

  In Japanese Patent Laid-Open No. 7-183831, there is no description about multiple access, which is one of the characteristics of spread spectrum communication. However, as disclosed in Japanese Patent Laid-Open No. 7-183831, “a signal after quadrature detection is converted into one bit. In the “quantization method”, when two or more signals are received at the same time, they cannot be demodulated correctly.

  The present invention has been made to solve such problems, and is small and inexpensive that can be correctly demodulated even when a plurality of signals are received at the same time even if it is constituted by a 1-bit A / D converter. An object is to provide a receiver for spread spectrum communication.

  A spread spectrum communication receiver according to the present invention is a spread spectrum communication receiver that performs communication by performing phase shift keying on an information signal spread by spread spectrum, and receives a phase shift key modulation signal to be received at an intermediate frequency. Frequency downshift means for downshifting to a signal, A / D conversion means for converting an intermediate frequency signal output from the frequency downshift means into a 1-bit quantized signal, and conversion by the A / D conversion means A first multiplier for multiplying the quantized signal by a first reference phase signal generated by an oscillator; a first accumulator for accumulating an output of the first multiplier for a predetermined time; First ternary conversion means for ternary conversion of the output of the accumulated hand, and generating a second reference phase signal orthogonal to the first reference phase signal by shifting the first reference phase signal by π / 2. Transferee , Second multiplying means for multiplying the quantized signal and the second reference phase signal, second accumulating means for accumulating the output of the second multiplying means for a predetermined time, and output of the second accumulating means. Quadrature detection means composed of second ternary conversion means for ternary conversion of the signal, and ternary conversion output from the first ternary conversion means and the second ternary conversion means of the quadrature detection means And despreading means for despreading the received signal to obtain binary-encoded binary-coded data.

  According to the present invention, an intermediate frequency signal obtained by down-shifting a received phase shift keying signal is converted into a 1-bit quantized signal by a 1-bit A / D converter (A / D converter). However, even when a plurality of signals are received at the same time, it can be demodulated correctly, and a small and inexpensive spread spectrum communication receiver can be realized.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a block diagram illustrating a configuration example of a transmitter in spread spectrum communication.
In the figure, a primary modulator 15 is a spreading code (PN0) generated by a PN code generator 11 in a section where binary transmission data (information signal) 10 from an ECU (electronic control unit) (not shown) is “0”. 12 is selected, the spread signal (PN1) 14 generated by the PN code generator 13 is selected in a section where the binary transmission data 10 is “1”, and the primary modulation signal 16 which is a direct spread spectrum signal is generated. .
Based on the primary modulation signal 16 from the primary modulator 15, a secondary modulation signal 19 is generated by phase shift keying (PSK) the carrier wave of the carrier generator 17 by the modulation unit 18, and the generated secondary modulation signal 19 is Amplified by the amplifier 20 and transmitted as a radio wave from the transmitting antenna 2.

FIG. 2 is a block diagram showing a configuration example of a spread spectrum communication receiver according to the first embodiment.
As shown in FIG. 2, in the receiver 4, the signal received by the receiving antenna 3 (that is, the phase shift keying signal 19 transmitted from the transmitter 1) is allowed to pass through only the band used in this communication. The signal is filtered by the band pass filter (BPF) 40, the signal filtered by the band pass filter (BPF) 40 is amplified by the amplifier 41, and the signal amplified by the amplifier 41 and the signal from the local oscillator 42 are multiplied by the multiplier 43. Multiplication is performed, and the output of the multiplier 43 is passed through a low-pass filter (LPF) 44 to obtain a low intermediate frequency.
That is, the local oscillator 42, the multiplier 43, and the low-pass filter 44 constitute frequency downshift means for downshifting the phase shift keying signal received by the receiver 4 to an intermediate frequency signal.
The intermediate frequency signal downshifted by the frequency downshift means is quantized 1 bit by a 1-bit A / D converter (A / D conversion means) 45 and output to the digital processing unit 5 as an intermediate frequency digital signal 49. To do.

FIG. 3 is a block diagram showing a configuration of the digital processing unit 5 shown in FIG.
As shown in the figure, the digital processing unit 5 includes an orthogonal detection unit (orthogonal detection unit) 200 and a despreading unit (despreading unit) 300.
The quadrature detection unit (orthogonal detection means) 200 has two signal processing routes, an “I sequence processing route” and a “Q sequence processing route”.
The “I-sequence processing route” is generated by the “intermediate frequency digital signal (ie, 1-bit quantized signal) 49” input from the A / D converter (A / D conversion means) 45 and the oscillator 50. A first multiplying unit 52 for multiplying one reference phase signal 50a; a first accumulator (first accumulating unit) 54 for accumulating the output of the first multiplier 52 for one chip of the spreading code; The first ternary converter (first ternary conversion means) 56 for converting the output of the accumulator 54 into three values (1, 0, −1).

The “Q sequence processing route” is a phase shifter (a phase shifter that generates a second reference phase signal that is orthogonal to the first reference phase signal by phase-shifting the first reference phase signal 50a generated by the oscillator 50 by π / 2. Phase shift means) 51, second multiplier (second multiplier means) 53 that multiplies the 1-bit quantized signal 49 and the second reference phase signal generated by the phase shifter (phase shift means) 51. A second accumulator (second accumulating means) 55 that accumulates the output of the second multiplier (second multiplying means) 53 for a predetermined time, and a second accumulator (second accumulating means) 55. The output is a second ternary converter (second ternary conversion means) 57 for ternary conversion.
The intermediate frequency digital signal (1-bit quantized signal) 49 input from the A / D converter (A / D conversion means) 45 to the quadrature detection unit (orthogonal detection means) 200 is the “I-sequence processing route” described above. ”And“ Q sequence processing route ”.

Next, the output of the I-sequence processing route (that is, the output of the first ternary converter (first ternary conversion means) 56) and the output of the Q-sequence processing route (that is, the second The Q output 59, which is the output of the ternary conversion unit 57, is sent to the despreading unit (despreading unit) 300.
In the despreading unit (despreading means) 300, the digital matched filters (DMF60 to DMF63) perform despreading processing, and are exclusive OR of the reference PN code (PN0 or PN1) and the chip unit (Tc). Is a circuit unit that performs correlation evaluation for calculating the sum of information for one bit length (Tb = Tc × Nc) and outputs a correlation value (sum).
The computing unit 64 and the computing unit 65 select the higher correlation between the I component and the Q component that are higher than the predetermined correlation height (correlation threshold).

A binary coding computation unit (binary coding computing means) 68 compares the PN0 correlation value and the PN1 correlation value, selects the one with the higher correlation, and outputs a binary corresponding to each (when the PN0 correlation is high) The output is “0”, and when the PN1 correlation is high, the output is “1”).
That is, the despreading unit (despreading unit) 300 despreads the ternary converted signal output from the first ternary conversion unit 56 and the second ternary conversion unit 57 of the orthogonal detection unit 200, Binary-encoded binary reception data is obtained.

  Since the chip phase is not synchronized between the transmission side and the reception side, the despreading processing of the digital matched filters DMF60 to DMF63 may not be able to detect a correlation peak in the correlation value calculation at the chip unit (Tc) interval. It is preferable that the correlation value calculation is performed at two series of Tc intervals shifted by about / 2, and the one with higher correlation is employed.

FIG. 4 is a diagram for explaining the operation (effect) of the receiver according to the present embodiment, and the correlation value when two signals (signal A and signal B) spread by the same spreading code are received. The comparison of peak detection methods (multi-bit A / D method, conventional method of 1-bit A / D, method of the present invention) is tabulated.
In FIG. 4, the spreading code is a 15-chip Barker code (111101011001000), which is PN0 in FIG. 1. For simplicity, in the example of FIG. 4, all binary transmission data 10 is illustrated as “0”.
The “primary modulated signal A” 102 transmitted from the transmitter A corresponds to 1 bit at times 3 to 17 at time 101 in units of chips.
On the other hand, the “primary modulated signal B” 103 transmitted from the transmitter B corresponds to the chip time 10 to 24 corresponding to 1 bit.

FIG. 4 shows an example of a state where the signals of “primary modulation signal A” 102 and “primary modulation signal B” 103 are out of phase by 7 chips.
Numerical values “1” and “−1” of “secondary modulation signal A” 104 and “secondary modulation signal B” 105 corresponding to “primary modulation signal A” 102 and “primary modulation signal B” 103 are respectively Corresponding to the numerical values “0” and “1” in the row of the primary modulation signal, it indicates whether the carrier wave is generated in phase or in phase with respect to the carrier wave generated by the carrier wave generator 17, and the carrier wave amplitudes are “1” and “1”. -1 ".
When this signal is transmitted as a radio wave from the transmitter 1 and received by the receiver 2 as a radio wave of equal power, the amplitude of the received signal is the received signal 106 shown in FIG. 4 and the “secondary modulation signal A” 104 and “ This is the sum of the secondary modulation signal B ”105.

FIG. 5 is a block diagram showing a configuration of a digital processing unit in a conventional receiver.
In the multi-bit method, 3 bits (-2 to 2) are required to completely correspond to the received waveform amplitude, and the A / D converter 45 of FIG. 2 is changed to 3 bits A / D. The correlation value obtained by inputting to the digital processing unit shown in FIG. 5 is “correlation value at 3 bit A / D” 107, and the received signal 106 and the reference PN code 112 (“0” of the Barker signal is “1”). In addition, “1” is converted to “−1”), and is a numerical value obtained by performing the above-described correlation calculation for each chip.
"Correlation value at 3bit A / D" 107, 1 bit = 2 chips corresponding to the correlation values A and B written in bold "14" at the end chip (chip time 17 and 24) "Peak" indicates that the received signals from the two transmitters can be accurately demodulated into binary signals (information signals).
In the block diagram of FIG. 5, although the number of bits of the signal is different, the signal processing flow differs from the block of FIG. 3 in terms of a ternary converter (ternary converter) 56 and a ternary converter (ternary converter). ), Except for 57, the description of FIG. 5 is omitted.
The “correlation value at 3 bit A / D” 107 is m = 3 of “m bit” in FIG.

In Japanese Patent Application Laid-Open No. 7-183831 showing an example of a conventional method, orthogonal detection is performed, and after accumulation, 1-bit quantization is performed by a comparator to calculate correlation. Therefore, m = 1 of “m bit” in FIG. 5 is set. It corresponds to a thing.
Performing quadrature detection and setting the accumulated data to 1 bit (1, −1) cannot express a state of “reception amplitude 0” that does not exist when there is one reception signal.
In the “reception signal 1 bit A / D” 108 of the conventional system example shown in FIG. 4, “−2” and “−1” of the reception signal 106 are “−1”, “2” and “1” are Since “1” is converted but “0” cannot be converted, “1” and “−1” are alternately assigned in the order of appearance of “0”, assuming that the conversion probability is 50%.

Correlation calculation of “reception signal 1-bit A / D” 108 in the same manner is “correlation value at 1-bit A / D” 109, and a correlation value peak is seen at the chip at the end of each 1-bit. There is also a high correlation value (correlation value 7 at chip time 22 and correlation value −9 at chip time 23), and the peak of the correct correlation value cannot be detected, indicating that it cannot be demodulated into binary data. ing.
In the value conversion method according to the present embodiment, the “three values after accumulation” 110 used for calculating the correlation value is “−2” and “−1” of the received signal 106, “−1”, and “2”. “1” is converted to “1”, and “0” is converted to “0”.
Similarly, “correlation value with three values after accumulation” 111 obtained by performing correlation calculation with “three values after accumulation” 110 is a correlation peak value compared with “correlation value with 3 bits A / D” 107. Although it is low, it can be correctly demodulated into binary data because the peak can be detected correctly.
That is, according to the present embodiment, the 1-bit A / D converter is used as the A / D conversion means 45 for converting the intermediate frequency signal output from the frequency downshift means into the 1-bit quantized signal 49. However, it is possible to correctly demodulate even when a plurality of signals are received simultaneously.

As described above, the spread spectrum communication receiver according to the present embodiment is a spread spectrum communication receiver that performs communication by performing phase shift keying on an information signal spread by spread spectrum. 1-bit frequency downshift means (comprising a local oscillator 42, a multiplier 43 and a low-pass filter 44) for downshifting the modulation signal to an intermediate frequency signal, and an intermediate frequency signal output from the frequency downshift means A / D conversion means 45 for converting to a first quantized signal 49, and a first reference phase signal generated by the oscillator 50 multiplied by the quantized signal 49 converted by the A / D conversion means 45 Multiplication means 52, first accumulation means 54 for accumulating the output of the first multiplication means 52 for a predetermined time, and first ternary conversion means for ternary conversion of the output of the first accumulation hand 54. 6. Phase shift means 51 for generating a second reference phase signal orthogonal to the first reference phase signal by π / 2 phase shifting of the first reference phase signal, quantized signal 49 and second reference phase signal The second multiplication means 53 for multiplying the outputs, the second accumulation means 55 for accumulating the outputs of the second multiplication means 53 for a predetermined time, and the second ternary conversion for ternary conversion of the output of the second accumulation means 55 A quadrature detection means 200 composed of the means 57, and a ternary converted signal output from the first ternary conversion means 56 and the second ternary conversion means 57 of the quadrature detection means 200 to despread 2 And despreading means 300 for obtaining binary encoded reception data.
Therefore, according to the present embodiment, an intermediate frequency signal obtained by down-shifting the received phase shift keying signal is converted into a 1-bit quantized signal by a 1-bit A / D converter (A / D converter). Even though multiple signals are received at the same time, it can be demodulated correctly, and a small and inexpensive spread spectrum communication receiver can be realized. Is preferred.

In the spread spectrum communication receiver according to the present embodiment, the first accumulating unit 54 and the second accumulating unit 55 are low-pass filters, so that there is an advantage that the digital circuit configuration is simplified.
In addition, in the spread spectrum communication receiver according to the present embodiment, the first reference phase signal and the second reference phase signal are rectangular wave signals, so that the digital circuit configuration is similarly simplified. .

  INDUSTRIAL APPLICABILITY The present invention is useful for realizing a small and inexpensive spread spectrum communication receiver that can correctly demodulate even when a plurality of signals are received simultaneously while using a 1-bit A / D converter.

It is a block diagram which shows the structural example of the transmitter in spread spectrum communication. 2 is a block diagram showing a configuration of a receiver of spread spectrum communication according to Embodiment 1. FIG. FIG. 3 is a block diagram illustrating a configuration of a digital processing unit illustrated in FIG. 2. 6 is a diagram for explaining an operation of the receiver according to Embodiment 1. FIG. It is a block diagram which shows the structure of the digital processing part in the conventional receiver.

Explanation of symbols

DESCRIPTION OF SYMBOLS 3 Reception antenna 4 Receiver 5 Digital processing part 6 Binary reception data 40 BPF (band pass filter) 41 Amplifier 42 Local oscillator 43 Multiplier 44 LPF (low-pass filter) 45 A / D conversion means 49 1 bit quantization Signal 50 Oscillator 50a First reference phase signal 51 Phase shift means 52 First multiplication means 53 Second multiplication means 54 First accumulation means 55 Second accumulation means 56 First ternary conversion means 57 Second Ternary conversion means 60-63 DMF (digital matched filter)
64, 65 arithmetic unit 68 binary encoding arithmetic unit 200 orthogonal detection means 300 despreading unit

Claims (3)

A spread spectrum communication receiver that performs communication by performing phase shift keying on an information signal spread by spread spectrum,
A frequency downshift means for downshifting the received phase shift keying signal to an intermediate frequency signal;
A / D conversion means for converting an intermediate frequency signal output from the frequency downshift means into a 1-bit quantized signal;
First multiplication means for multiplying the quantized signal converted by the A / D conversion means by a first reference phase signal generated by an oscillator, and a first multiplication means for accumulating outputs of the first multiplication means for a predetermined time. 1 accumulating means, a first ternary converting means for ternary conversion of the output of the first accumulating hand, and a phase shift of the first reference phase signal by π / 2 to be orthogonal to the first reference phase signal. Phase shifting means for generating a second reference phase signal, second multiplication means for multiplying the quantized signal and the second reference phase signal, and a second time for accumulating outputs of the second multiplication means for a predetermined time. Quadrature detection means comprising two accumulation means, and second ternary conversion means for ternary conversion of the output of the second accumulation means;
Despreading to obtain binary-encoded binary reception data by despreading the ternary converted signals output from the first ternary conversion unit and the second ternary conversion unit of the orthogonal detection unit A spread spectrum communication receiver comprising: means.   2. The spread spectrum communication receiver according to claim 1, wherein the first accumulating means and the second accumulating means are low-pass filters.   3. The spread spectrum communication receiver according to claim 1, wherein the first reference phase signal and the second reference phase signal are rectangular wave signals.

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