JP2009302448A - Manufacturing method of solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a solid-state imaging element that has an overflow barrier formed at a position deep from a surface of a semiconductor substrate without using thick-film resist and is suitable for microfabrication. <P>SOLUTION: The manufacturing method includes an implantation process S103 of forming at least parts of photoelectric conversion areas 13c and 13d included in a photodetection portion 13 by ion implantation from the side of a reverse surface 16b of the semiconductor substrate 11, a second implantation process S104 of forming element isolation areas 15c and 15d included in a vertical transfer register portion 15 by ion implantation from the side of the reverse surface 16b of the semiconductor substrate 11, and a process S105 of forming a p-type semiconductor well layer 12 functioning as the overflow barrier after the first implantation process S103 and second implantation process S104. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a solid-state imaging device having a light receiving portion with high photoelectric conversion efficiency and operating with high sensitivity to light from the outside.

  In recent years, digital cameras have become widespread and are also standardly installed in mobile phones, and further improvements in high-definition image quality are desired. For the purpose of improving the image quality, the number of pixels of a solid-state image sensor mounted as a heart of a digital camera is being increased.

  This increase in the number of pixels can be realized, for example, by reducing the unit pixel of the solid-state imaging device. However, when the unit pixel is reduced, the amount of input light received from the outside is relatively reduced. There is a problem of reduced sensitivity.

  In order to prevent a decrease in sensitivity in the unit pixel, a technique has been proposed in which an overflow barrier is formed at a deep position from the surface of the semiconductor substrate using a high energy ion implantation apparatus. By efficiently confining the carriers generated by forming the overflow barrier in this way, it is possible to improve the light receiving sensitivity from the visible light region to the near infrared light region constituting the input light from the outside. It is said that it is possible to prevent a decrease in sensitivity at the unit pixel.

As an example of a manufacturing method for improving the sensitivity of a light receiving unit using such a high-energy ion implantation apparatus, for example, a manufacturing method for forming a photoelectric conversion region using a phenomenon of channeling of implanted ions in ion implantation (for example, , See Patent Document 1). The ion implantation energy is set to a high energy of several hundred to 4 MeV, and the ion implantation is performed under the condition that the implanted ions intentionally channel in the semiconductor substrate, for example, the semiconductor substrate is tilted by a predetermined angle in the ion implantation direction. Yes. By adopting such a method, an overflow barrier is formed at a position deeper than the conventional photoelectric conversion region, for example, a position of 4 μm to 6 μm from the surface, and the photoelectric conversion region can be expanded to improve the sensitivity of the unit pixel. It is said.
JP 2005-191311 A

  However, in the conventional technology described above, when a high-sensitivity solid-state imaging device is manufactured even in a near-infrared light region having a depth of 6 μm or more using a high-energy ion implantation device from the surface side of the semiconductor substrate, A thick film resist having high energy resistance is required, but if the resist is thickened, miniaturization becomes difficult due to the limit of the aspect ratio.

  SUMMARY OF THE INVENTION The present invention solves the above-described problems, and a method for manufacturing a solid-state imaging device suitable for miniaturization that can form an overflow barrier at a deep position from the surface of a semiconductor substrate without using such a thick film resist. Is to provide.

  In addition, since the element isolation region for electrically separating adjacent photoelectric conversion regions can be formed to a depth near the overflow barrier by the method for manufacturing a solid-state imaging device of the present invention, the photoelectric conversion region can be enlarged. Sensitivity can be improved in unit pixels, and even if the number of pixels is increased, a good solid-state image sensor can be manufactured without a decrease in sensitivity.

  In order to achieve the above object, a method of manufacturing a solid-state imaging device according to the present invention includes a first conductivity type semiconductor substrate, a vertical transfer register portion, a read gate portion, and a p-type semiconductor well layer adjacent to the semiconductor substrate. A solid-state imaging device manufacturing method including a light receiving unit, wherein at least a part of a photoelectric conversion region included in the light receiving unit is formed by ion implantation from the back side of the semiconductor substrate. A second implantation step in which an element isolation region included in the vertical transfer register portion is formed by ion implantation from the back side of the semiconductor substrate, and the first implantation step and the second implantation step. And a step of forming the p-type semiconductor well layer that functions as an overflow barrier later.

  By adopting such a method, it is possible to form a photoelectric conversion region and an overflow barrier at a deep position from the surface (front surface) of the semiconductor substrate without using a thick film resist. Can do. As a result, it is possible to efficiently absorb the input light from the outside visible light region to the near infrared light region, so that the light receiving sensitivity of the solid-state imaging device can be improved, and the sensitivity in the unit pixel is lowered. The number of pixels of the solid-state imaging device can be increased without any problem.

  Alternatively, the semiconductor substrate may be thinned from the back side before the first implantation step and the second implantation step.

  By adopting such a method, it is possible to form a photoelectric conversion region and an overflow barrier at a deep position from the surface (front surface) of the semiconductor substrate without using a thick film resist. Can do.

  The light receiving portion is formed to include a positive charge accumulation region, a charge accumulation region, and a photoelectric conversion region. The photoelectric conversion region includes a first n-type photoelectric conversion region adjacent to the charge storage region and a second adjacent to the first n-type photoelectric conversion region. In which the n-type impurity concentration of the first n-type photoelectric conversion region is higher than the n-type impurity concentration of the second n-type photoelectric conversion region. .

  By adopting such a method, the n-type impurity concentration of the first n-type photoelectric conversion region is formed higher than the n-type impurity concentration of the second n-type photoelectric conversion region, so that it is accumulated in the photoelectric conversion region. It is possible to reduce the shutter voltage when sucking out the carriers to the semiconductor substrate side.

  The light receiving portion is formed to include a positive charge accumulation region, a charge accumulation region, and a photoelectric conversion region. The photoelectric conversion region includes a first n-type photoelectric conversion region adjacent to the charge storage region and a second adjacent to the first n-type photoelectric conversion region. In which the n-type impurity concentration of the first n-type photoelectric conversion region is lower than the n-type impurity concentration of the second n-type photoelectric conversion region. .

  By adopting such a method, the n-type impurity concentration of the first n-type photoelectric conversion region is formed lower than the n-type impurity concentration of the second n-type photoelectric conversion region. It is possible to prevent the position of the overflow barrier in the depth direction from being determined due to the variation, and the position can be determined at a predetermined position. As a result, it is possible to improve sensitivity by suppressing variations in sensitivity.

  The photoelectric conversion region is formed including a first n-type photoelectric conversion region, a second n-type photoelectric conversion region, and a third n-type photoelectric conversion region in order from the side closer to the surface of the semiconductor substrate. Alternatively, the n-type impurity concentration in the n-type photoelectric conversion region may be lower than the n-type impurity concentration in the first n-type photoelectric conversion region and the third n-type photoelectric conversion region.

  By adopting such a method, it is possible to reduce the shutter voltage when sucking out the carriers accumulated in the photoelectric conversion region to the semiconductor substrate side, and set the position of the overflow barrier in the depth direction to a predetermined value. By determining the position, it is possible to improve sensitivity by suppressing variation in sensitivity.

  Alternatively, the second n-type photoelectric conversion region may be formed wider than the first n-type photoelectric conversion region. By adopting such a method, the width of the second n-type photoelectric conversion region can be expanded, so that the shutter voltage can be lowered and the sensitivity can be improved.

  Alternatively, the third n-type photoelectric conversion region may be formed wider than the second n-type photoelectric conversion region. By adopting such a method, the width of the third n-type photoelectric conversion region can be increased, so that the shutter voltage can be lowered and the sensitivity can be improved.

  Alternatively, the n-type impurity implantation layer may be formed on the semiconductor substrate side adjacent to the p-type semiconductor well layer by ion implantation from the back side of the semiconductor substrate.

  By adopting such a method, a high-concentration n-type impurity implantation layer is formed adjacent to the p-type semiconductor well layer functioning as an overflow barrier, so that the overflow barrier position can be accurately placed at a predetermined position. Can do. As a result, the shutter voltage of the semiconductor substrate can be further reduced.

  According to another aspect of the present invention, there is provided a method for manufacturing a solid-state imaging device, comprising: a first conductivity type semiconductor substrate; a CMOS image comprising a CMOS transistor and a light receiving portion formed on a p-type semiconductor well layer adjacent to the semiconductor substrate. A method for manufacturing a solid-state imaging device including a sensor, wherein a first implantation step in which at least a part of a photoelectric conversion region included in a light receiving portion is formed by ion implantation from the back side of a semiconductor substrate, and a depth in the light receiving portion As an overflow barrier after the second implantation step in which the element isolation region adjacent to the vertical direction is formed by ion implantation from the back surface side of the semiconductor substrate, the first implantation step, and the second implantation step And a step of forming a functioning p-type semiconductor well layer.

  By adopting such a method, the photoelectric conversion region and the overflow barrier can be formed at a deep position from the surface of the semiconductor substrate without using a thick film resist, and it is possible to cope with further miniaturization. As a result, it is possible to efficiently absorb the input light from the outside visible light region to the near infrared light region, so that the light receiving sensitivity of the solid-state imaging device can be improved, and the sensitivity in the unit pixel is lowered. The number of pixels of the solid-state imaging device can be increased without any problem.

  Alternatively, the semiconductor substrate may be thinned from the back side before the first implantation step and the second implantation step.

  By adopting such a method, the photoelectric conversion region and the overflow barrier can be formed at a deep position from the surface of the semiconductor substrate without using a thick film resist, and it is possible to cope with further miniaturization.

  According to the method for manufacturing a solid-state imaging device of the present invention, a photoelectric conversion region and an overflow barrier can be formed at a deep position from the surface (front surface) of a semiconductor substrate without using a thick film resist. Can respond. As a result, it is possible to efficiently absorb the input light from the outside visible light region to the near infrared light region, so that the light receiving sensitivity of the solid-state imaging device can be improved, and the sensitivity in the unit pixel is lowered. The number of pixels of the solid-state imaging device can be increased without any problem.

  Hereinafter, a method for manufacturing a solid-state imaging device according to an embodiment of the present invention will be described with reference to the drawings. In addition, what attached | subjected the same code | symbol in drawing may abbreviate | omit description.

(Embodiment 1)
FIG. 1A is a cross-sectional view of a solid-state imaging device 10 manufactured by the method for manufacturing a solid-state imaging device according to the first embodiment of the present invention, and FIG. 1B is a flowchart of the main part of the manufacturing method. Here, the solid-state imaging device 10 is an overflow drain type solid-state imaging device.

  As shown in FIG. 1A, in the solid-state imaging device 10, a light receiving unit 13, a read gate unit 14, and a vertical transfer register unit 15 are disposed on a p-type semiconductor well layer 12 adjacent on a semiconductor substrate 11.

  The light receiving unit 13, the read gate unit 14, and the vertical transfer register unit 15 are covered with a gate insulating film 16, and a transfer electrode 17 is formed on the gate insulating film 16 in the read gate unit 14 and the vertical transfer register unit 15. Has been.

  Then, the input light from the outside to the light receiving unit 13 through the opening of the transparent interlayer insulating film 18 that protects the front surface (hereinafter referred to as “surface”) 16a and the transfer electrode 17 and the light shielding film 19 formed thereon. The electric signal generated based on the input light 20 is transferred by the transfer electrode 17.

Here, the light receiving unit 13 includes a p ⁺ -type positive charge storage region 13a, an n-type charge storage region 13b, an n ⁻ -type first n-type photoelectric conversion region 13c, and an n ⁻ -type from the side close to the surface 16a. It is formed including the second n-type photoelectric conversion region 13d.

  The vertical transfer register unit 15 includes an n-type transfer channel region 15a, a p-type semiconductor well region 15b, a first p-type element isolation region 15c, and a second p-type element isolation region 15d from the side close to the surface 16a. It is formed including. The light receiving unit 13 and the vertical transfer register unit 15 are separated by an epitaxial layer 11a formed first on the semiconductor substrate 11.

Further, a p ⁺ -type channel stop region 11 b is formed on the adjacent pixel side of the light receiving unit 13 and under the gate insulating film 16 in order to prevent electric charge from flowing out to the adjacent pixel.

  The solid-state imaging device 10 configured as described above is manufactured using the flowchart shown in FIG.

  That is, in the manufacturing method shown in the first embodiment, the vertical transfer register unit 15, the read gate unit 14, and the first conductivity type semiconductor substrate 11 and the p-type semiconductor well layer 12 adjacent to the semiconductor substrate 11 are provided. This is a method of manufacturing a solid-state imaging device including the light receiving unit 13.

  This manufacturing method includes a first implantation step S103 in which at least a part of the photoelectric conversion regions 13c and 13d included in the light receiving unit 13 is formed by ion implantation from the back surface 16b side of the semiconductor substrate 11, and the vertical transfer register unit. 15 includes a second implantation step S104 formed by ion implantation from the back surface 16b side of the semiconductor substrate 11.

  The method further includes a step S105 in which the p-type semiconductor well layer 12 functioning as an overflow barrier is formed after the first implantation step S103 and the second implantation step S104.

  By adopting such a method, it is possible to form the photoelectric conversion regions 13c and 13d and the overflow barrier at a deep position from the surface 16a of the semiconductor substrate 11 without using a thick film resist, and to cope with further miniaturization. can do.

  As a result, the input light 20 from the outside visible light region to the near infrared light region can be efficiently absorbed, so that the light receiving sensitivity of the solid-state imaging device 10 can be improved, and the sensitivity at the unit pixel is increased. The number of pixels of the solid-state image sensor 10 can be increased without being lowered.

  Before performing these steps, this manufacturing method includes a step S101 for forming a diffusion region on the front surface 16a side as shown in FIG. 1 (b) and disposing the optical member, and a step S102 for reducing the thickness from the back surface 16b side. I have.

  That is, the semiconductor substrate 11 may be thinned from the back surface 16b side before performing the first implantation step S103 and the second implantation step S104.

  By adopting such a method, ion implantation is performed from the back surface 16b side by an ion implantation apparatus having a normal energy, and the photoelectric conversion regions 13c and 13d and the overflow barrier are formed at a deep position from the surface 16a of the semiconductor substrate 11. it can.

  Therefore, the photoelectric conversion regions 13c and 13d and the overflow barrier can be formed at a deep position from the surface 16a of the semiconductor substrate 11 without using a thick film resist.

  Next, the manufacturing method of the solid-state imaging device according to the first embodiment will be described in detail with reference to FIGS. 2 (a) to 2 (c), FIG. 3 (a) and FIG. 3 (b), and FIG. 4 (a) and FIG. 4 (b) show a flowchart of this manufacturing method.

  As shown in FIG. 2A, a structure is prepared in which an epitaxial layer 11 a having a second conductivity type semiconductor region is stacked on a first conductivity type semiconductor substrate 11. Here, the semiconductor substrate 11 is, for example, an Si substrate having a thickness of 800 μm and an 8-inch diameter, and the epitaxial layer 11a is formed by epitaxially laminating Si single crystals to a thickness of 4 μm to 6 μm.

  Next, as shown in FIG. 2B, the transfer channel region 15a and the p-type semiconductor well region 15b constituting the vertical transfer register unit 15 are formed by normal ion implantation from the surface 16a side.

  Further, the positive charge accumulation region 13a, the charge accumulation region 13b and the channel stop region 11b constituting the light receiving unit 13 are formed by normal ion implantation, respectively. A gate insulating film 16 is formed so as to cover them.

  Then, as shown in FIG. 2C, the first n-type photoelectric conversion region 13c constituting the light receiving unit 13 is formed by injecting an ion beam 11c of normal energy from the surface 16a side. At this time, the area other than the light receiving portion 13 is covered and protected by the resist 16c.

  Subsequently, as shown in FIG. 3A, the first p-type element isolation region 15c constituting the vertical transfer register portion 15 is formed from the surface 16a side by implanting an ion beam 11c of normal energy. . At this time, the area other than the vertical transfer register unit 15 is covered and protected by the resist 16d.

  Next, as shown in FIG. 3B, a transfer electrode 17 made of, for example, a polysilicon film is formed on the gate insulating film 16 on the surface 16a side.

  A light shielding film 19 such as tungsten, an on-chip color filter 21 and an on-chip lens 22 are formed on the interlayer insulating film 18 formed so as to cover the gate insulating film 16 and the transfer electrode 17, and then a resin or the like is formed. After flattening with the flattening film 23, the glass substrate 24 is disposed. The lower part of the on-chip color filter 21 is flattened by, for example, a BPSG film 21a.

  2 and 3, the diffusion region such as the positive charge accumulation region 13a is formed on the surface 16a side, and the optical members such as the light shielding film 19, the on-chip color filter 21, and the on-chip lens 22 are disposed. Step S101 is performed.

  Next, as shown in FIG. 4A, in the step S102 of thinning from the back surface 16b, the back surface 16b side of the semiconductor substrate 11 is deleted by, for example, a CMP technique so that the film thickness of the semiconductor substrate 11 is about 1 μm to 3 μm. Until it becomes thin.

  After that, in the first implantation step S103, ion implantation is performed from the back surface 16b of the semiconductor substrate 11 at an acceleration energy of about 2 MeV to 5 MeV to form the next region.

  That is, as shown in FIG. 4A, the ion beam 11d is ion-implanted to form the second n-type photoelectric conversion region 13d. At this time, the region other than the light receiving portion 13 is covered and protected by the resist 16d.

  Then, in the second implantation step S104, after forming the second p-type element isolation region 15d constituting the vertical transfer register section 15 as shown in FIG. 4B, the p-type semiconductor is formed from the back surface 16b side. Step S105 in which the well layer 12 is formed is performed. In this way, the solid-state imaging device 30 including the optical region 25 can be manufactured.

  Even if the thickness of the semiconductor substrate 11 is reduced to 1 μm or less, the optical region 25 including the optical member such as the on-chip lens 22 formed on the surface 16 a side has a thickness of about 600 μm to 1000 μm, and is integrated with the semiconductor substrate 11. Therefore, in the series of flowcharts, handling of an 8-inch substrate including these in the manufacturing process can be handled without any difference from the manufacturing process of an ordinary 8-inch substrate of a semiconductor element.

  Further, as described above, the photoelectric conversion regions 13c and 13d and the overflow barrier can be formed at a deep position from the surface 16a of the semiconductor substrate 11 without using a thick film resist, which can cope with further miniaturization. it can.

  The solid-state imaging device manufactured basically using the manufacturing method of the solid-state imaging device of the first embodiment described above will be described in the following second to sixth embodiments.

(Embodiment 2)
FIG. 5 is a diagram showing a schematic configuration of a solid-state imaging device 35 according to the second embodiment of the present invention. FIG. 5A is a cross-sectional view, and FIG. 5B is an impurity profile in the depth direction from the surface 16a. It is a figure which shows the change of the potential corresponding to this.

  As shown in FIG. 5A, the light receiving unit 13 includes a positive charge accumulation region 13a, a charge accumulation region 13b, and photoelectric conversion regions 13c and 13d.

  Then, a first n-type photoelectric conversion region 13c adjacent to the charge storage region 13b and a second n-type photoelectric conversion region 13d adjacent to the first n-type photoelectric conversion region 13c are formed, and the n-type impurity of the first n-type photoelectric conversion region 13c is formed. It is formed by a method in which the concentration is higher than the n-type impurity concentration of the second n-type photoelectric conversion region 13d. The difference between the n-type impurity concentration and the solid-state imaging device 10 shown in the first embodiment is that the n-type impurity concentration is added.

  As shown in FIGS. 5A and 5B, the second embodiment is different from the conventional n-type photoelectric conversion region 13c in the photoelectric conversion region in the device structure of the conventional example. Separated from the second n-type photoelectric conversion region 13d, the respective n-type impurity concentrations are different. A p-type semiconductor well layer 12 is provided adjacent to the second n-type photoelectric conversion region 13d on the semiconductor substrate 11 side.

  As a result of manufacturing by designing the impurity profile 31, the potential profile 32b in the first n-type photoelectric conversion region 13c is formed deeper than the potential profile 32a of the conventional example.

  Thus, when a voltage is applied to the semiconductor substrate 11, for example, when a voltage of about 15 V is applied to the substrate, the potential profile 33 b of the second embodiment is more easily removed from the charge storage region 13 b than the potential profile 33 a of the conventional example. Thus, the barrier adjacent to the charge accumulation region 13b when the charge is released to 11 can be formed low.

  Therefore, the solid-state imaging device 35 manufactured with the configuration of the second embodiment is more likely to release charges to the semiconductor substrate 11 than the configuration of the conventional example, and the electronic shutter voltage is reduced.

  That is, since the n-type impurity concentration of the first n-type photoelectric conversion region 13c is formed higher than the n-type impurity concentration of the second n-type photoelectric conversion region 13d, it is accumulated in the photoelectric conversion regions 13c, 13d, etc. A reduction in shutter voltage when sucking out carriers to the semiconductor substrate 11 side can be realized.

(Embodiment 3)
6A and 6B are diagrams showing a schematic configuration of the solid-state imaging device 40 according to the third embodiment of the present invention. FIG. 6A is a cross-sectional view, and FIG. 6B is an impurity profile 41 in the depth direction from the surface 16a. It is a figure which shows the change of the potential corresponding to this.

  As shown in FIG. 6A, the light receiving unit 13 includes a positive charge accumulation region 13a, a charge accumulation region 13b, and photoelectric conversion regions 13c and 13d.

  Then, a first n-type photoelectric conversion region 13c adjacent to the charge storage region 13b and a second n-type photoelectric conversion region 13d adjacent to the first n-type photoelectric conversion region 13c are formed, and the n-type impurity of the first n-type photoelectric conversion region 13c is formed. It is formed by a method in which the concentration is lower than the n-type impurity concentration of the second n-type photoelectric conversion region 13d. The difference between the n-type impurity concentration and the solid-state imaging device 10 shown in the first embodiment is that the n-type impurity concentration is added.

  As shown in FIGS. 6A and 6B, the third embodiment is different from the first n-type photoelectric conversion region 13c in the conventional device structure in comparison with the structure in which the photoelectric conversion region is uniform. Separated from the second n-type photoelectric conversion region 13d, the respective n-type impurity concentrations are different.

  A p-type semiconductor well layer 12 is provided adjacent to the second n-type photoelectric conversion region 13d on the semiconductor substrate 11 side. As a result of manufacturing by designing the impurity profile 41, the potential profile 41b in the first n-type photoelectric conversion region 13c is formed deeper than the potential profile 41a of the conventional example.

  With such a configuration, the pn junction capacitance between the second n-type photoelectric conversion region 13d and the p-type semiconductor well layer 12 increases, so that the overflow barrier 41c due to the uneven dopant concentration of the semiconductor substrate 11 is increased. Potential fluctuations can be controlled and variations in sensitivity can be suppressed.

  That is, since the n-type impurity concentration of the first n-type photoelectric conversion region 13c is formed lower than the n-type impurity concentration of the second n-type photoelectric conversion region 13d, overflow occurs due to the variation in the impurity concentration of the semiconductor substrate 11. It is possible to prevent the position of the barrier 41c in the depth direction from being determined, and it can be determined at a predetermined position. As a result, it is possible to improve sensitivity by suppressing variations in sensitivity.

(Embodiment 4)
7A and 7B are diagrams showing a schematic configuration of a solid-state imaging device 45 according to the fourth embodiment of the present invention. FIG. 7A is a cross-sectional view, and FIG. 7B is an impurity profile 46 in the depth direction from the surface 16a. It is a figure which shows the change of the potential corresponding to this.

  As shown in FIG. 7A, in the light receiving unit 13 of the solid-state imaging device 45 shown in the fourth embodiment, the solid-state imaging devices 35 and 40 of the second and third embodiments are different from the second n-type photoelectric conversion region. The width W2 of 13d is configured as a method of forming wider than the width W1 of the first n-type photoelectric conversion region 13c.

  By adopting such a method, the injection cross-sectional area of the second n-type photoelectric conversion region 13d is expanded, so that the substantial photoelectric conversion region in the near-infrared light region is further expanded, and the sensitivity is improved. Is possible.

  Similarly to the third embodiment, the potential profile 46b in the second n-type photoelectric conversion region 13d shown in FIG. 7B is formed deeper than the potential profile 46a of the conventional example. The pn junction capacitance between the n-type photoelectric conversion region 13d and the p-type semiconductor well layer 12 increases.

  As a result, the potential fluctuation of the overflow barrier 46c due to the uneven dopant concentration of the semiconductor substrate 11 can be controlled, so that variations in sensitivity can be reduced. Therefore, the shutter voltage can be lowered and the sensitivity can be improved by increasing the width W2 of the second n-type photoelectric conversion region 13d.

(Embodiment 5)
FIG. 8 is a diagram showing a schematic configuration of a solid-state imaging device 50 according to the fifth embodiment of the present invention. FIG. 8A is a cross-sectional view, and FIG. 8B is an impurity profile 51 in the depth direction from the surface 16a. It is a figure which shows the change of the potential corresponding to this.

  As shown in FIG. 8A, in the light receiving unit 13 of the solid-state imaging device 50, the photoelectric conversion regions 13c, 13d, and 13e are arranged in order from the side closer to the surface 16a of the semiconductor substrate 11, the first n-type photoelectric conversion region 13c, A second n-type photoelectric conversion region 13d and a third n-type photoelectric conversion region 13e are formed. As a method of forming the n-type impurity concentration of the second n-type photoelectric conversion region 13d lower than the n-type impurity concentration of the first n-type photoelectric conversion region 13c and the third n-type photoelectric conversion region 13e. It has been implemented.

  As shown in FIG. 8B, the potential profile 51b is formed deeper than the potential profile 51a of the conventional example, and it is shown that the potential fluctuation of the overflow barrier 51c can be controlled. Thus, it can be seen that both effects shown in the second and third embodiments are combined.

  Therefore, by adopting such a method, it is possible to realize a reduction in shutter voltage when the carriers accumulated in the photoelectric conversion regions 13c, 13d, and 13e are sucked out to the semiconductor substrate 11 side. At the same time, by setting the position of the overflow barrier 51c in the depth direction to a predetermined position, it is possible to suppress sensitivity variation and improve sensitivity.

  In the fifth embodiment, as in the fourth embodiment, the third n-type photoelectric conversion region 13e may be formed wider than the second n-type photoelectric conversion region 13d. Good. By adopting such a method, the width of the third n-type photoelectric conversion region 13e can be increased, so that the shutter voltage can be lowered and the sensitivity can be improved.

(Embodiment 6)
FIG. 9 is a diagram showing a schematic configuration of a solid-state imaging element 55 according to the sixth embodiment of the present invention. FIG. 9A is a cross-sectional view, and FIG. 9B is an impurity profile 56 in the depth direction from the surface 16a. It is a figure which shows the change of the potential corresponding to this.

  The solid-state imaging device 55 in FIG. 9A has substantially the same configuration as the solid-state imaging device 35 in FIG. 5A shown in the second embodiment, but the p-type semiconductor well layer 12 and the semiconductor substrate 11 have the same structure. The difference is that an n-type impurity implantation layer 13f is formed therebetween.

That is, in the manufacturing method of the sixth embodiment, the n-type impurity implantation layer 13f is formed on the semiconductor substrate 11 side adjacent to the p-type semiconductor well layer 12 by ion implantation from the back surface 16b side of the semiconductor substrate 11. It's a way. Here, the n-type impurity implantation layer 13f is formed as an n ⁺ -type impurity region into which impurities are implanted at a high concentration.

  FIG. 9B shows the potential profiles 56b and 57b of the sixth embodiment and the potential profiles 56a and 57a of the conventional example when voltage is applied and not applied.

As shown in FIGS. 9A and 9B, the pn junction capacitance between the p-type semiconductor well layer 12 and the n-type impurity implantation layer 13f formed as a high-concentration n ⁺ -type impurity region increases. is doing. As a result, the shutter voltage can be adjusted, and the shutter voltage can be reduced. Further, the potential fluctuation of the overflow barrier 56c due to the uneven density of the substrate is suppressed, and the variation in sensitivity can be reduced.

(Embodiment 7)
FIG. 10 is a cross-sectional view of a solid-state image sensor 60 manufactured by the method for manufacturing a solid-state image sensor according to the seventh embodiment of the present invention. Here, the solid-state imaging device 60 is a CMOS image sensor.

  As shown in FIG. 10, the manufacturing method of the seventh embodiment includes a first conductivity type semiconductor substrate 11, a CMOS transistor 61 formed on a p-type semiconductor well layer 12 adjacent to the semiconductor substrate 11, and light reception. And a solid-state imaging device manufacturing method including a CMOS image sensor including a unit 62.

  In addition, at least a part of the first n-type photoelectric conversion region 62a and the second n-type photoelectric conversion region 62b included in the light receiving unit 62 has the first injection step S103 and the second n-type photoelectric conversion region shown in FIG. It is manufactured by a manufacturing method including an implantation step S104 and a step S105 in which the p-type semiconductor well layer 12 is formed. As shown in FIG. 10, the light receiving unit 62 also includes a positive charge accumulation region 62c.

  Here, the first implantation step S103 is a step formed by an ion implantation method in which an ion beam 63 is implanted from the back surface 16b side of the semiconductor substrate 11 as shown in FIG.

  The second implantation step S104 is a step in which the element isolation region 64 adjacent to the light receiving portion 62 in the direction perpendicular to the depth direction is formed from the back surface 16b side of the semiconductor substrate 11 by the ion implantation method. After the first implantation step S103 and the second implantation step S104, step S105 in which the p-type semiconductor well layer 12 is formed is performed, and a p-type semiconductor well layer that functions as an overflow barrier is formed.

  By adopting such a method, photoelectric conversion regions 62a and 62b and an overflow barrier can be formed at a deep position from the surface 16a of the semiconductor substrate 11 without using a thick film resist as in the first to sixth embodiments. It is possible to cope with further miniaturization.

  As a result, the input light from the outside visible light region to the near infrared light region can be efficiently absorbed, so that the light receiving sensitivity of the solid-state imaging device 60 can be improved, and the sensitivity at the unit pixel is lowered. The number of pixels of the solid-state image sensor 60 can be increased without this.

  Alternatively, the semiconductor substrate 11 may be thinned from the back surface 16b side before performing the first implantation step S103 and the second implantation step S104.

  By adopting such a method, the photoelectric conversion regions 62a and 62b and the overflow barrier can be formed at a deep position from the surface 16a of the semiconductor substrate 11 without using a thick film resist. can do.

  Furthermore, by forming the second n-type photoelectric conversion region 62b by ion implantation from the back surface 16b of the semiconductor substrate 11, the region under the gate electrode 61a can also be used as a photoelectric conversion region, which improves sensitivity. Can be planned.

  It should be noted that the manufacturing method for forming the structure of the photoelectric conversion region constituting the light receiving portion described in the second to sixth embodiments is sufficiently applicable to the solid-state imaging device including the CMOS image sensor shown in the seventh embodiment. can do.

  The solid-state imaging device manufacturing method of the present invention can form a photoelectric conversion region and an overflow barrier at a deep position from the surface of a semiconductor substrate without using a thick film resist, and can cope with further miniaturization. it can.

  As a result, the light receiving sensitivity of the solid-state imaging device can be improved, and the number of pixels can be increased without lowering the sensitivity of the unit pixels, which is useful.

  Furthermore, by providing a characteristic to the implantation profile by the ion implantation method, by reducing the shutter voltage and setting the position in the depth direction of the overflow barrier to a predetermined position, it is possible to suppress sensitivity variations and improve sensitivity. Can be realized and useful.

(A) is sectional drawing of the solid-state image sensor produced by the manufacturing method of the solid-state image sensor concerning Embodiment 1 of this invention, (b) is a flowchart of the principal part of the manufacturing method. (A) to (c) are flowcharts in the previous stage of the manufacturing method of the solid-state imaging device according to the first embodiment of the present invention. (A) And (b) is a flowchart of the middle stage of the manufacturing method of the solid-state image sensor concerning Embodiment 1 of this invention. (A) And (b) is a flowchart of the latter stage of the manufacturing method of the solid-state image sensor concerning Embodiment 1 of this invention. It is a figure which shows schematic structure of the solid-state image sensor concerning Embodiment 2 of this invention, (a) is sectional drawing, (b) is the impurity profile of the depth direction from the surface, and the potential change corresponding to this. Illustration It is a figure which shows schematic structure of the solid-state image sensor concerning Embodiment 3 of this invention, (a) is sectional drawing, (b) is the impurity profile of the depth direction from the surface, and the potential change corresponding to this. Illustration It is a figure which shows schematic structure of the solid-state image sensor concerning Embodiment 4 of this invention, (a) is sectional drawing, (b) shows the impurity profile of the depth direction from the surface, and the change of the potential corresponding to this. Illustration It is a figure which shows schematic structure of the solid-state image sensor concerning Embodiment 5 of this invention, (a) is sectional drawing, (b) shows the impurity profile of the depth direction from the surface, and the change of the potential corresponding to this. Illustration It is a figure which shows schematic structure of the solid-state image sensor concerning Embodiment 6 of this invention, (a) is sectional drawing, (b) shows the impurity profile of the depth direction from the surface, and the change of the potential corresponding to this. Illustration Sectional drawing of the solid-state image sensor produced by the manufacturing method of the solid-state image sensor concerning Embodiment 7 of this invention.

Explanation of symbols

10, 30, 35, 40, 45, 50, 55, 60 Solid-state imaging device 11 Semiconductor substrate 11a Epitaxial layer 11b Channel stop region 11c, 11d, 63 Ion beam 12 p-type semiconductor well layer 13, 62 Light receiving portion 13a, 62c Positive Charge storage region 13b Charge storage region 13c, 62a First n-type photoelectric conversion region 13d, 62b Second n-type photoelectric conversion region 13e Third n-type photoelectric conversion region 13f n-type impurity injection layer 14 Read gate portion 15 Vertical Transfer register portion 15a Transfer channel region 15b P-type semiconductor well region 15c First p-type element isolation region 15d Second p-type element isolation region 16 Gate insulating film 16a Front surface (front surface)
16b Back surface 16c, 16d Resist 17 Transfer electrode 18 Interlayer insulating film 19 Light shielding film 20 Input light 21 On-chip color filter 21a BPSG film 22 On-chip lens 23 Flattening film 24 Glass substrate 25 Optical region 31, 41, 46, 51, 56 Impurity profile 32a, 32b, 33a, 33b, 41a, 41b, 46a, 46b, 51a, 51b, 56a, 56b, 57a, 57b Potential profile 41c, 46c, 51c, 56c Overflow barrier 61 CMOS transistor 61a Gate electrode 64 Element isolation region

Claims (10)

A method for manufacturing a solid-state imaging device, comprising: a first conductivity type semiconductor substrate; and a vertical transfer register portion, a read gate portion, and a light receiving portion on a p-type semiconductor well layer adjacent to the semiconductor substrate,
A first implantation step in which at least a part of the photoelectric conversion region included in the light receiving unit is formed by ion implantation from the back side of the semiconductor substrate;
A second implantation step in which an element isolation region included in the vertical transfer register portion is formed by ion implantation from the back side of the semiconductor substrate;
And a step of forming the p-type semiconductor well layer functioning as an overflow barrier after the first injection step and the second injection step. 2. The method of manufacturing a solid-state imaging device according to claim 1, wherein the semiconductor substrate is thinned from the back side before performing the first injection step and the second injection step. The light receiving unit is formed to include a positive charge accumulation region, a charge accumulation region, and the photoelectric conversion region, and the photoelectric conversion region is adjacent to the first n-type photoelectric conversion region adjacent to the charge storage region. And an n-type impurity concentration of the first n-type photoelectric conversion region is higher than an n-type impurity concentration of the second n-type photoelectric conversion region. The method of manufacturing a solid-state imaging device according to claim 1 or 2. The light receiving portion is formed including a positive charge accumulation region, a charge accumulation region, and the photoelectric conversion region, and the photoelectric conversion region is adjacent to the first n-type photoelectric conversion region adjacent to the charge storage region. And an n-type impurity concentration of the first n-type photoelectric conversion region is lower than an n-type impurity concentration of the second n-type photoelectric conversion region. The method of manufacturing a solid-state imaging device according to claim 1 or 2. The photoelectric conversion region is formed including a first n-type photoelectric conversion region, a second n-type photoelectric conversion region, and a third n-type photoelectric conversion region in order from the side closer to the surface of the semiconductor substrate. The n-type impurity concentration of the second n-type photoelectric conversion region is lower than the n-type impurity concentration of the first n-type photoelectric conversion region and the third n-type photoelectric conversion region. Item 3. A method for producing a solid-state imaging device according to Item 1 or 2. 5. The method of manufacturing a solid-state imaging device according to claim 3, wherein a width of the second n-type photoelectric conversion region is formed wider than a width of the first n-type photoelectric conversion region. 6. The method for manufacturing a solid-state imaging device according to claim 5, wherein the width of the third n-type photoelectric conversion region is formed wider than the width of the second n-type photoelectric conversion region. 8. The n-type impurity implantation layer is formed on the semiconductor substrate side adjacent to the p-type semiconductor well layer by ion implantation from the back surface side of the semiconductor substrate. The manufacturing method of the solid-state image sensor as described in an item. A method for producing a solid-state imaging device comprising a CMOS image sensor comprising a semiconductor substrate of a first conductivity type and a CMOS transistor and a light receiving portion formed on a p-type semiconductor well layer adjacent to the semiconductor substrate,
A first implantation step in which at least a part of the photoelectric conversion region included in the light receiving portion is formed by ion implantation from the back surface side of the semiconductor substrate;
A second implantation step in which an element isolation region adjacent to the light receiving portion in a direction perpendicular to the depth direction is formed from the back side of the semiconductor substrate by an ion implantation method;
And a step of forming the p-type semiconductor well layer functioning as an overflow barrier after the first injection step and the second injection step. 10. The method of manufacturing a solid-state imaging device according to claim 9, wherein the semiconductor substrate is thinned from the back side before the first injection step and the second injection step.

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