JP2009302437A - Component built-in printed wiring board and method of manufacturing the same - Google Patents

Component built-in printed wiring board and method of manufacturing the same Download PDF

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Publication number
JP2009302437A
JP2009302437A JP2008157595A JP2008157595A JP2009302437A JP 2009302437 A JP2009302437 A JP 2009302437A JP 2008157595 A JP2008157595 A JP 2008157595A JP 2008157595 A JP2008157595 A JP 2008157595A JP 2009302437 A JP2009302437 A JP 2009302437A
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Prior art keywords
component
printed wiring
wiring board
inner layer
chip
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Japanese (ja)
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Taku Ishioka
卓 石岡
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Kyocera Circuit Solutions Inc
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NEC Toppan Circuit Solutions Inc
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Priority to JP2008157595A priority Critical patent/JP2009302437A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable component built-in printed wiring board which does not increase manufacturing costs, prevents the formation of a void between a chip component and a base plate, and prevents the occurrence of an electrical connection failure on an inner layer when an electronic component is soldered to an outer layer. <P>SOLUTION: The component built-in printed wiring board includes a printed wiring board intermediate element which has a component-attached inner layer substrate made by disposing a chip component along a through-hole on a base plate composed of an insulating resin plate having the through-hole and a wiring layer, the chip component having an electrode soldered to the wiring layer and being thicker than the base plate, a first insulating resin layer formed by laminating open prepregs on the side of the chip component on the component-attached inner layer substrate, the open prepregs avoiding the chip component through prepreg openings, and a second insulating resin layer formed by laminating open prepregs on the surface opposite to the chip component formation surface on the component-attached inner layer substrate. The component built-in printed wiring board also includes a wiring layer as an outer layer on the printed wiring board intermediate element, and a through-hole penetrating the printed wiring board intermediate element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、多層の配線層と、多層のチップ部品の設置層を有する部品内蔵印刷配線板及びその製造方法に関する。   The present invention relates to a component built-in printed wiring board having a multilayer wiring layer and a multilayer chip component installation layer, and a method for manufacturing the same.

近年、半導体実装技術の発展により半導体装置を実装する印刷配線板においては、高密度、高精度の配線層を有する多層の印刷配線板が要求されている。高密度を実現する一つの方法として、抵抗、コンデンサー等のチップ部品を内蔵した印刷配線板が開発されている。従来技術における部品内蔵印刷配線板の製造方法は、特許文献1のように、はんだペーストによる加熱溶融接続などで電子部品の電極をベースプレートのランドにはんだ付けする。そして、電子部品を設置した第1の部品付き内層基板と、同様に電子部品を設置した第2の部品付き内層基板を、設置した電子部品を互いに向き合わせて、層間絶縁層を介して積層して部品内蔵印刷配線板を製造していた。   2. Description of the Related Art In recent years, a printed wiring board on which a semiconductor device is mounted has been required due to the development of semiconductor mounting technology, and a multilayer printed wiring board having a high-density and high-precision wiring layer is required. As one method for realizing high density, printed wiring boards incorporating chip parts such as resistors and capacitors have been developed. In a conventional method for manufacturing a component-embedded printed wiring board, as disclosed in Patent Document 1, the electrodes of an electronic component are soldered to a land of a base plate by heating and melting connection using a solder paste. Then, the inner layer board with the first component on which the electronic component is installed and the inner layer board with the second component on which the electronic component is similarly installed are stacked via the interlayer insulating layer with the installed electronic components facing each other. Was producing printed wiring boards with built-in components.

以下に公知文献を記す。
特開2005−142178号公報
The known literature is described below.
JP 2005-142178 A

この従来技術の部品内蔵印刷配線板は、ベースプレートに電子部品を設置し、積層工法を用いて電子部品を封止する際に、絶縁層間樹脂が電子部品とベースプレートの間の隙間に回り込まず、その隙間に空間が残る積層ボイドが発生する問題があった。この積層ボイドが発生すると、その部品内蔵印刷配線板の外層への部品のはんだ付け工程におけるはんだリフロー処理により、絶縁層間樹脂と絶縁層の接着部分の耐熱性が劣化し、層間剥離不良を引き起こし易くなる問題があった。また、この積層ボイドは、その部品内蔵印刷配線板の外層への部品のはんだ付け工程におけるはんだリフロー処理により、内蔵された電子部品の電極を内層の複数のランドにはんだ付けしていたはんだが再溶融し、内層のランド間の空間に形成された積層ボイドの中に流れ込んで複数のランドのはんだ同士が接触して内層のランド間をはんだで短絡させてしまう問題があった。   In this prior art printed wiring board with built-in components, when an electronic component is installed on a base plate and the electronic component is sealed using a lamination method, the insulating interlayer resin does not enter the gap between the electronic component and the base plate. There was a problem that a laminated void was generated in which a space remained in the gap. When this layered void occurs, the solder reflow process in the soldering process of the component to the outer layer of the printed wiring board with built-in component deteriorates the heat resistance of the bonded portion between the insulating interlayer resin and the insulating layer, and easily causes delamination failure. There was a problem. In addition, this laminated void is re-applied to the solder that soldered the electrodes of the built-in electronic components to the multiple lands on the inner layer by the solder reflow process in the soldering process of the components to the outer layer of the printed wiring board with built-in components. There is a problem that the melted and flowed into the laminated void formed in the space between the lands of the inner layer, the solders of a plurality of lands contacted, and the lands of the inner layer were short-circuited with the solder.

このため、少なくとも内層のランド間をはんだで短絡させないために、電子部品の電極を内層のランドに融点変化型はんだではんだ付けする改善策が考えられるが、その場合は、製造コストが上昇する問題があった。また、電子部品の電極をランドに高温はんだではんだ付けする改善策が考えられるが、その場合は、その高温はんだのはんだ付け温度が高いため、電子部品をはんだ付けしたベースプレートの損傷が大きくなり、部品内蔵印刷配線板の品質を悪化させる問題があった。あるいは、積層ボイドを発生させないために、ベースプレートへの電子部品のはんだ付けの後に、ベースプレートと電子部品の間の隙間にアンダーフィル樹脂を充填すると、製造コストを大幅に上昇させる問題があった。   For this reason, in order not to short-circuit between the lands of the inner layer with solder, an improvement measure for soldering the electrode of the electronic component to the land of the inner layer with a melting point change type solder can be considered, but in that case, the manufacturing cost increases was there. In addition, improvement measures to solder the electrode of the electronic component to the land with high temperature solder can be considered, but in that case, the soldering temperature of the high temperature solder is high, so the damage of the base plate to which the electronic component is soldered becomes large, There was a problem of deteriorating the quality of the printed wiring board with built-in components. Alternatively, in order not to generate laminated voids, if an underfill resin is filled in the gap between the base plate and the electronic component after the electronic component is soldered to the base plate, there is a problem that the manufacturing cost is significantly increased.

本発明は上記問題点に鑑み考案されたもので、製造コストを上昇させずに、チップ部品とベースプレートの間に積層ボイドが発生せず、外層に電子部品をはんだ付けする際にも内層の電気接続不良が発生しない信頼性の高い部品内蔵印刷配線板を得ることを目的とする。   The present invention has been devised in view of the above problems, and does not increase the manufacturing cost, does not generate a laminated void between the chip component and the base plate, and also when the electronic component is soldered to the outer layer, An object of the present invention is to obtain a printed wiring board with a built-in component that does not cause poor connection and has high reliability.

本発明は、この課題を解決するために、絶縁性樹脂板に貫通孔を形成し配線層を形成したベースプレートに、前記ベースプレートの厚さより厚いチップ部品を前記貫通孔を覆っ
て設置し、前記チップ部品の電極を前記配線層にはんだ付けした部品付き内層基板を製造する第1の工程と、前記部品付き内層基板上の前記チップ部品側に該チップ部品をプリプレグ開口部によって避けた開口プリプレグを設置し、前記部品付き内層基板上の前記チップ部品設置面と反対面側にプリプレグを設置して積層し加熱・加圧することで印刷配線板中間体を製造する第2の工程と、前記印刷配線板中間体にスルホール下孔を形成する第3の工程と、銅めっきにより前記スルホール下孔に形成したスルホールめっきと前記印刷配線板中間体の外層の配線層を形成する第4の工程を有することを特徴とする部品内蔵印刷配線板の製造方法である。
In order to solve this problem, the present invention is configured such that a chip component thicker than the thickness of the base plate is placed on a base plate in which a through hole is formed in an insulating resin plate and a wiring layer is formed so as to cover the through hole. A first step of manufacturing an inner layer substrate with components in which component electrodes are soldered to the wiring layer, and an open prepreg in which the chip components are avoided by a prepreg opening on the inner layer substrate with components are installed. A second step of manufacturing a printed wiring board intermediate by installing a prepreg on the surface opposite to the chip component setting surface on the inner layer substrate with components, laminating, heating and pressing, and the printed wiring board; A third step of forming a through-hole prepared hole in the intermediate body, and forming a through-hole plating formed in the through-hole prepared hole by copper plating and an outer wiring layer of the printed wiring board intermediate body It is a manufacturing method of the electronic component embedded printed wiring board and having a fourth step of.

また、本発明は、上記の部品内蔵印刷配線板の製造方法において、上記第1の工程で、上記部品付き内層基板を製造するとともに、第2のベースプレートの配線層にチップ部品又は集積回路チップの電極をはんだ付けした電子部品付き内層基板を製造し、上記第2の工程で、上記部品付き内層基板と前記電子部品付き内層基板を、上記チップ部品と前記電子部品を互いに向かい合わせて配置し、上記部品付き内層基板と前記電子部品付き内層基板の間に前記開口プリプレグを挟んで積層し加熱・加圧することで印刷配線板中間体を製造することを特徴とする部品内蔵印刷配線板の製造方法である。   According to the present invention, in the above-described method for manufacturing a printed wiring board with built-in components, in the first step, the inner substrate with components is manufactured, and a chip component or an integrated circuit chip is formed on the wiring layer of the second base plate. An inner layer substrate with an electronic component to which an electrode is soldered is manufactured, and in the second step, the inner layer substrate with a component and the inner layer substrate with an electronic component are disposed so that the chip component and the electronic component face each other. A method for producing a printed wiring board with built-in components, wherein a printed wiring board intermediate is produced by laminating the opening prepreg between the inner layer board with components and the inner layer board with electronic components, and heating and pressing. It is.

また、本発明は、絶縁性樹脂板に貫通孔を形成し配線層を形成したベースプレートに、前記配線層に電極がはんだ付けされた前記ベースプレートの厚さより厚いチップ部品を前記貫通孔を覆って設置した部品付き内層基板と、前記部品付き内層基板上の前記チップ部品側に該チップ部品をプリプレグ開口部によって避けた開口プリプレグを積層して形成された第1の絶縁性樹脂層と、前記部品付き内層基板上の前記チップ部品設置面と反対面側にプリプレグを積層して形成された第2の絶縁性樹脂層とを備えた印刷配線板中間体を有し、前記印刷配線板中間体の外層に配線層を備え、前記印刷配線板中間体を貫通するスルホールを備えたことを特徴とする部品内蔵印刷配線板である。   In the present invention, a chip component thicker than the thickness of the base plate in which an electrode is soldered to the wiring layer is installed on the base plate in which a through hole is formed in the insulating resin plate and the wiring layer is formed, covering the through hole. An inner layer substrate with components, a first insulating resin layer formed by laminating an opening prepreg avoiding the chip components by a prepreg opening on the chip component side on the inner layer substrate with components, and with the components A printed wiring board intermediate comprising a second insulating resin layer formed by laminating a prepreg on the side opposite to the chip component installation surface on the inner layer substrate, and an outer layer of the printed wiring board intermediate A printed wiring board with a built-in component, comprising a wiring layer and a through hole penetrating the printed wiring board intermediate body.

また、本発明は、上記の部品内蔵印刷配線板において、上記部品付き内層基板とともに、第2のベースプレートの配線層にチップ部品又は集積回路チップの電極をはんだ付けした電子部品付き内層基板を有し、上記部品付き内層基板と前記電子部品付き内層基板が、上記チップ部品と前記電子部品を互いに向かい合わせて配置し、上記部品付き内層基板と前記電子部品付き内層基板の間に上記開口プリプレグを挟んで積層して形成された上記第1の絶縁樹脂層を有することを特徴とする部品内蔵印刷配線板である。   According to the present invention, in the printed wiring board with built-in components, together with the inner layer substrate with components, an inner layer substrate with electronic components in which a chip component or an electrode of an integrated circuit chip is soldered to the wiring layer of the second base plate. The inner layer substrate with components and the inner layer substrate with electronic components are arranged so that the chip component and the electronic component face each other, and the opening prepreg is sandwiched between the inner layer substrate with components and the inner layer substrate with electronic components. A printed wiring board with a built-in component, comprising the first insulating resin layer formed by laminating.

本発明の部品内蔵印刷配線板では、ベースプレートに貫通孔を形成し、そのベースプレートのその貫通孔上にチップ部品を設置した部品付き内層基板を製造し、その部品付き内層基板の両面にプリプレグを設置して積層して部品内蔵印刷配線板を製造するので、プリプレグの樹脂が、ベースプレートの貫通孔からチップ部品とベースプレートの隙間に流れ込みその隙間を充填するので、積層ボイドの無い、信頼性の高い部品内蔵印刷配線板が得られる効果がある。   In the component built-in printed wiring board of the present invention, a through hole is formed in the base plate, a chip-mounted inner layer substrate is manufactured on the through hole of the base plate, and a prepreg is installed on both sides of the component inner layer substrate. Since the printed wiring board with built-in components is manufactured by laminating, the prepreg resin flows into the gap between the chip component and the base plate from the through hole of the base plate and fills the gap, so there is no highly reliable component without laminated voids. There is an effect that a built-in printed wiring board can be obtained.

<第1の実施形態>
以下、本発明の第1の実施の形態を、図1〜図6を用いて説明する。図1〜図6、本発明の部品内蔵印刷配線板の製造方法の工程を模式的に示す断面図である。
<First Embodiment>
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. 1 to 6 are cross-sectional views schematically showing the steps of the method for producing a component built-in printed wiring board of the present invention.

(工程1)
部品内蔵印刷配線板の製造方法は、先ず、図1(a)のように、複数の配線層11を有する厚さが0.04mmから0.1mmの、好適には厚さが0.03mmから0.1mmの絶縁性樹脂板の外層の配線層11の一部に、後の積層後に内層に埋め込まれるランド1
3のパターンを形成したベースプレート10aを製造する。このベースプレート10aには表裏の配線層11のみならず、内層にも配線層11を有する多層基板を用いることもできる。また、このベースプレート10aには、表裏を導通するスルホールやフィルドビアホールを作り込んでも良い。このベースプレート10aは、その絶縁性樹脂板にガラス繊維を含有し、基板の面方向の熱膨張係数(JIS−C6481で試験した30から120℃における熱膨張係数)が8〜12×10−6/ケルビン程度の小さい値であり、処理条件TMAで試験して得られるガラス転移温度Tg値が160〜170℃程度の高いTgを有する材料を使用する。このベースプレート10aは、この特性の材料を使用することにより内蔵部品をはんだ付けする温度に耐えることができ、また、製造工程での寸法安定性が優れる効果がある。
(Process 1)
First, as shown in FIG. 1A, the method of manufacturing a component-embedded printed wiring board has a thickness of 0.04 mm to 0.1 mm, preferably 0.03 mm, having a plurality of wiring layers 11. A land 1 embedded in the inner layer after the subsequent lamination in a part of the outer wiring layer 11 of the 0.1 mm insulating resin plate
The base plate 10a having the pattern 3 is manufactured. As the base plate 10a, a multilayer substrate having the wiring layer 11 in the inner layer as well as the front and back wiring layers 11 can be used. Further, a through hole or a filled via hole that conducts the front and back may be formed in the base plate 10a. This base plate 10a contains glass fibers in its insulating resin plate, and has a thermal expansion coefficient in the surface direction of the substrate (thermal expansion coefficient at 30 to 120 ° C. tested according to JIS-C6481) of 8 to 12 × 10 −6 / A material having a small Tg value of about Kelvin and a glass transition temperature Tg value obtained by testing under the processing condition TMA of about 160 to 170 ° C. is used. The base plate 10a can withstand the temperature at which the built-in component is soldered by using a material having this characteristic, and has an effect of excellent dimensional stability in the manufacturing process.

(工程2)
次に、図1(b)のように、ベースプレート10aに、プレス、ドリリング、レーザー等を用いて、所望の位置に所望のサイズの開口部14をくりぬく。そして、チップ部品20の設置予定箇所には、チップ部品領域内貫通孔14aをくりぬく。このチップ部品領域内貫通孔14aは、その上に設置するチップ部品20の寸法より小さく形成し、チップ部品20を設置することでチップ部品20で覆われる寸法に形成する。ここで、チップ部品領域内貫通孔14aは、その上に設置するチップ部品20の領域から一部分がはみ出すように形成しても良い。
(Process 2)
Next, as shown in FIG. 1B, an opening 14 of a desired size is hollowed out at a desired position using a press, drilling, laser, or the like on the base plate 10a. Then, a through hole 14 a in the chip component area is cut out at a planned installation location of the chip component 20. The through hole 14a in the chip component region is formed to be smaller than the size of the chip component 20 installed thereon, and formed to have a size covered with the chip component 20 by installing the chip component 20. Here, the through-hole 14a in the chip component region may be formed so that a part thereof protrudes from the region of the chip component 20 installed thereon.

(工程3)
次に、図1(c)のように、ベースプレート10aのランド13とチップ部品20の電極21とを以下のようにしてはんだ22ではんだ付けして、チップ部品20を、チップ部品領域内貫通孔14aを覆って設置した部品付き内層基板17を作製する。ここで設置するチップ部品20としては、大きさが0603タイプ(0.6mm×0.3mm×0.23mm)、0402タイプ(0.4m×0.2mm×0.12mm)、更には、0.3mm×0.15mm×0.07mmの微小チップ部品、
あるいは、10005の低背タイプの積層セラミックスチップコンデンサ、抵抗、あるいはその程度の寸法のインダクタ素子等のチップ部品20を設置する。これらのチップ部品20よりもベースプレート10aの厚さが薄く、そのチップ部品領域内貫通孔14aの深さがチップ部品20の高さより浅いため、樹脂により充填し易い効果がある。
(Process 3)
Next, as shown in FIG. 1C, the land 13 of the base plate 10a and the electrode 21 of the chip component 20 are soldered with the solder 22 as follows, and the chip component 20 is inserted into the through hole in the chip component region. The inner layer substrate 17 with components installed so as to cover 14a is produced. The chip component 20 installed here has a size of 0603 type (0.6 mm × 0.3 mm × 0.23 mm), 0402 type (0.4 m × 0.2 mm × 0.12 mm), 3 mm × 0.15 mm × 0.07 mm microchip parts,
Alternatively, a chip component 20 such as a 10005 low-profile type multilayer ceramic chip capacitor, a resistor, or an inductor element having a size of the same is installed. Since the base plate 10a is thinner than the chip components 20 and the depth of the through-holes 14a in the chip component region is shallower than the height of the chip components 20, there is an effect that it can be easily filled with resin.

次に、図2(a)のように、先に説明した工程1により、配線層11にランド13、13bのパターンを形成した厚さが0.03mmから0.1mmの第2のベースプレート10bを製造する。次に、図2(b)のように、工程2により、第2のベースプレート10bの所望の位置に所望のサイズの開口部14bをくりぬく。そして、チップ部品20の設置予定箇所には、チップ部品領域内貫通孔14cをくりぬく。次に、図2(c)のように、工程3により、ベースプレート10bのランド13に、チップ部品20の電極21をはんだ22で接合して、チップ部品20を実装した部品付き内層基板17bを作製する。   Next, as shown in FIG. 2A, the second base plate 10b having a thickness of 0.03 mm to 0.1 mm, in which the patterns of the lands 13 and 13b are formed on the wiring layer 11 by the step 1 described above, is formed. To manufacture. Next, as shown in FIG. 2B, in step 2, an opening 14b having a desired size is hollowed out at a desired position of the second base plate 10b. Then, the chip component region through-hole 14c is hollowed out at a planned installation location of the chip component 20. Next, as shown in FIG. 2C, in step 3, the electrode 21 of the chip component 20 is joined to the land 13 of the base plate 10b with the solder 22 to produce the component-attached inner layer substrate 17b on which the chip component 20 is mounted. To do.

(工程4)
次に、図3(d)のように、高さが300μm以下の集積回路チップ30で、銅や金などの金属のバンプ電極31を有する集積回路チップ30を用いて、その金属のバンプ電極31の先端にはんだバンプ32を形成し、その集積回路チップ30のはんだバンプ32を赤外線で約200℃に加熱することで、はんだバンプ32を溶かし、この集積回路チップ30をベースプレート10bにバンプ電極31側を向けて(フェイスダウン)、溶けたはんだバンプ32をベースプレート10bのランド13bに接触させる。こうして、図3(e)のように、ベースプレート10bのランド13bに、集積回路チップ30のバンプ電極31をはんだバンプ32ではんだ付けする。
(Process 4)
Next, as shown in FIG. 3D, an integrated circuit chip 30 having a height of 300 μm or less and a metal bump electrode 31 such as copper or gold is used, and the metal bump electrode 31 is used. A solder bump 32 is formed at the tip of the semiconductor chip, and the solder bump 32 of the integrated circuit chip 30 is heated to about 200 ° C. with infrared rays, so that the solder bump 32 is melted and the integrated circuit chip 30 is attached to the base plate 10b on the bump electrode 31 side. (Face down), the melted solder bump 32 is brought into contact with the land 13b of the base plate 10b. Thus, as shown in FIG. 3E, the bump electrodes 31 of the integrated circuit chip 30 are soldered to the lands 13b of the base plate 10b with the solder bumps 32.

(工程5)
次に、図3(f)のように、ベースプレート10bの集積回路チップ30の下面とベースプレート10bの間の空間のランド13bとバンプ電極31の接続部に、ディスペンサー等で封止樹脂を注入して加熱硬化させて保護樹脂層33を形成した部品付き内層基板17bを作成する。また、先にベースプレート10a上に作成した部品付き内層基板17も、同様に、チップ部品20とランド部13の接続部にディスペンサー等で耐薬品性を有する樹脂を塗布し、加熱硬化させて保護樹脂層33を形成した部品付き内層基板17を作製する。耐薬品性を有する樹脂としては、UV−熱硬化性エポキシ樹脂が好ましい。
(Process 5)
Next, as shown in FIG. 3 (f), a sealing resin is injected into the connecting portion between the land 13b of the space between the lower surface of the integrated circuit chip 30 of the base plate 10b and the base plate 10b and the bump electrode 31 with a dispenser or the like. The component-attached inner layer substrate 17b on which the protective resin layer 33 is formed by heat curing is created. Similarly, the inner layer substrate 17 with components prepared on the base plate 10a is similarly protected by applying a resin having chemical resistance to the connecting portion between the chip component 20 and the land portion 13 with a dispenser or the like, followed by heat curing. The component-attached inner layer substrate 17 on which the layer 33 is formed is produced. As the resin having chemical resistance, a UV-thermosetting epoxy resin is preferable.

(工程6)
次に、部品付き内層基板17、17b上の配線層11の表面を粗化処理液を用いて粗化処理を行う。この粗化処理は、強アルカリの化学処理で行い、黒化還元処理、硫酸過水系の黒化代替処理(銅粗化処理)等が使用可能である。この粗化処理を行うことにより、配線層11の表面に複雑且つ微細な凹凸を形成し、後記する絶縁樹脂層形成時の樹脂の接着性を向上させ、チップ部品の破損及びチップ部品とランドとの接着部の破損を防止できる。このように配線層11の表面を粗化処理する際に、保護樹脂層33が、はんだ22とはんだバンプ32と集積回路チップ30やチップ部品20の電極21が処理液に汚染されて基板の絶縁性及び耐熱性が劣化するのを防止する。
(Step 6)
Next, the surface of the wiring layer 11 on the inner layer substrates 17 and 17b with components is roughened using a roughening solution. This roughening treatment is performed by a strong alkali chemical treatment, and a blackening reduction treatment, a sulfuric acid-hydrogen peroxide blackening alternative treatment (copper roughening treatment), or the like can be used. By performing this roughening treatment, complex and fine irregularities are formed on the surface of the wiring layer 11, and the adhesion of the resin when forming an insulating resin layer to be described later is improved. It is possible to prevent breakage of the bonded portion. Thus, when the surface of the wiring layer 11 is roughened, the protective resin layer 33 is contaminated with the solder 22, the solder bump 32, the integrated circuit chip 30, and the electrode 21 of the chip component 20 with the processing liquid, thereby insulating the substrate. To prevent deterioration of heat resistance and heat resistance.

(変形例1)
以上の工程5と工程6は、以下の変形工程5−1と変形工程6−1で行うこともできる。
(変形工程5−1)
図3(f)のように、ベースプレート10bの集積回路チップ30の下面とベースプレート10bの間の空間のランド13bとバンプ電極31の接続部に、ディスペンサー等で封止樹脂を注入して加熱硬化させて保護樹脂層33を形成した部品付き内層基板17bを作成する。この際に、先にベースプレート10a上に作成した部品付き内層基板17については、チップ部品20とランド13の接続部には、保護樹脂層33は特に形成しない。(変形工程6−1)
次に、部品付き内層基板17、17b上の銅の配線層11の表面を、脂肪酸カルボン酸1モルに対して2モル以上のアルカノールアミンを含有し銅イオン源とハロゲンイオン源を含有するマイクロエッチング剤で粗化し、次に、配線層11の表面にアゾール化合物と有機酸を含有する水溶液を接触させ配線層11の表面にアゾール化合物の厚い被膜を形成させることで後記する絶縁樹脂層形成時の樹脂の接着性を向上させる処理を行う。この変形工程6−1の処理のマイクロエッチング剤は腐食性が低いため、チップ部品20とランド13の接続部を侵さずに粗化でき、変形工程5−1では、その部分への耐薬品性を有する樹脂の塗布を省略できる。
(Modification 1)
The above steps 5 and 6 can also be performed in the following deformation step 5-1 and deformation step 6-1.
(Deformation step 5-1)
As shown in FIG. 3F, a sealing resin is injected into the connecting portion between the land 13b and the bump electrode 31 in the space between the lower surface of the integrated circuit chip 30 of the base plate 10b and the base plate 10b and the bump electrode 31, and is cured by heating. Thus, the component-attached inner layer substrate 17b on which the protective resin layer 33 is formed is prepared. At this time, the protective resin layer 33 is not particularly formed at the connection portion between the chip component 20 and the land 13 for the component-attached inner layer substrate 17 previously formed on the base plate 10a. (Deformation step 6-1)
Next, the surface of the copper wiring layer 11 on the inner substrates 17 and 17b with parts contains 2 mol or more of alkanolamine with respect to 1 mol of fatty acid carboxylic acid, and contains a copper ion source and a halogen ion source. Next, the surface of the wiring layer 11 is contacted with an aqueous solution containing an azole compound and an organic acid to form a thick film of the azole compound on the surface of the wiring layer 11. A treatment for improving the adhesiveness of the resin is performed. Since the microetching agent in the process of the deforming step 6-1 has low corrosiveness, it can be roughened without damaging the connection part between the chip component 20 and the land 13. Application of a resin having can be omitted.

(工程7)
次に、プリプレグ40の所定位置に、ドリル加工、パンチング、レーザー加工等の孔加工により集積回路チップ30とチップ部品20の大きさのプリプレグ開口部41を形成した開口プリプレグ42を形成する(図4(a)参照)。ここで、プリプレグ開口部41は、集積回路チップ30とチップ部品20の大きさに合わせた孔を加工してあるため、後記する印刷配線板中間体50を形成する際、加熱、加圧成型時の加圧圧力がチップ部品20に集中しないようにでき、チップ部品の位置ずれ、チップ部品破壊、チップ部品20の電極21ととランド13のはんだ22のクラック発生を防止する効果がある。また、プリプレグ40の絶縁材料は、硬化後の基板面方向の熱膨張係数(JIS−C6481で試験した30から120℃における熱膨張係数)が8〜12×10−6/ケルビン程度の小さい値であり、処理条件TMAで試験して得られるガラス転移温度Tg値が160〜170℃程度の高いTgを有する材料を使用する。この特性を有する材料を使用することにより、
ベースプレート10a、10bの絶縁性樹脂板の特性と整合し、以降の製造工程において基板内部にストレスが残留せず基板が反らず製造が安定する効果がある。
(Step 7)
Next, an opening prepreg 42 in which the prepreg opening 41 having the size of the integrated circuit chip 30 and the chip component 20 is formed by drilling, punching, laser processing or the like at a predetermined position of the prepreg 40 (FIG. 4). (See (a)). Here, since the prepreg opening 41 is processed with holes according to the sizes of the integrated circuit chip 30 and the chip component 20, when forming the printed wiring board intermediate 50 to be described later, during heating and pressure molding This pressure pressure can be prevented from concentrating on the chip component 20, and there is an effect of preventing the chip component displacement, chip component destruction, and cracks in the electrode 21 of the chip component 20 and the solder 22 of the land 13. Moreover, the insulating material of the prepreg 40 has a small coefficient of thermal expansion coefficient (thermal expansion coefficient at 30 to 120 ° C. tested in accordance with JIS-C6481) in the direction of the substrate surface after curing of about 8 to 12 × 10 −6 / Kelvin. Yes, a glass transition temperature Tg value obtained by testing under processing conditions TMA is used, and a material having a high Tg of about 160 to 170 ° C. is used. By using materials with this characteristic,
Matching with the characteristics of the insulating resin plates of the base plates 10a and 10b, there is an effect that in the subsequent manufacturing process, no stress remains in the substrate and the substrate is not warped and the manufacturing is stabilized.

(工程8)
次に、図4(a)のように、銅箔52の上に厚さが約0.06mmのプリプレグ40と、その上に部品付き内層基板17bと、その上に、チップ部品20を、プリプレグ開口部41によって避けた開口プリプレグ42と、その上に部品付き内層基板17と、その上に厚さが約0.06mmのプリプレグ40と、その上に銅箔51を位置合わせして積層し、加熱、加圧する。この積層工程の条件は、積層開始時点から約30分から60分の間の真空度を4kPa以下に減圧し、その後、大気圧に戻す。基板の加圧は、積層開始時点から10〜30分の間は0.5MPaで加圧し、その後に2〜3MPaに圧力を上げて加圧する。熱盤温度は80℃から130℃まで1.5〜2.5分で昇温し、真空度を大気圧に戻した後に基板温度が170℃以上に達するようにし、その基板温度に達したら加熱保持時間40分以上(例えば45分)保持して積層する。真空度は、基板温度が170℃以上に達する以前に大気圧に戻すが、このタイミングで真空度を大気圧に戻さないと樹脂中に気泡が発生する不具合を生じる。また、基板温度を170℃以上で40分以上保持しないと開口プリプレグ42からの樹脂による印刷配線板中間体50のチップ部品20及び集積回路チップ30と開口プリプレグ42の間の間隙の樹脂による充填性が悪くなる不具合を生じる。
(Process 8)
Next, as shown in FIG. 4 (a), a prepreg 40 having a thickness of about 0.06 mm on the copper foil 52, an inner layer substrate 17b with components thereon, and a chip component 20 thereon are mounted. The opening prepreg 42 avoided by the opening 41, the inner layer substrate 17 with components thereon, the prepreg 40 having a thickness of about 0.06 mm thereon, and the copper foil 51 are aligned and laminated thereon, Heat and pressurize. The condition of this lamination process is that the degree of vacuum between about 30 minutes and 60 minutes from the start of lamination is reduced to 4 kPa or less, and then returned to atmospheric pressure. Pressurization of the substrate is performed at 0.5 MPa for 10 to 30 minutes from the start of lamination, and then the pressure is increased to 2 to 3 MPa. The hot platen temperature is raised from 80 ° C. to 130 ° C. in 1.5 to 2.5 minutes, and after returning the degree of vacuum to atmospheric pressure, the substrate temperature is allowed to reach 170 ° C. or higher. The holding time is 40 minutes or more (for example, 45 minutes) and the layers are stacked. The degree of vacuum is returned to the atmospheric pressure before the substrate temperature reaches 170 ° C. or higher. However, if the degree of vacuum is not returned to the atmospheric pressure at this timing, there is a problem that bubbles are generated in the resin. Further, if the substrate temperature is not kept at 170 ° C. or higher for 40 minutes or more, the filling property of the printed wiring board intermediate 50 by the resin from the opening prepreg 42 and the gap between the integrated circuit chip 30 and the opening prepreg 42 by the resin This causes a problem that makes it worse.

この積層工程の際に、プリプレグから溶け出した樹脂が、ベースプレートのチップ部品20の設置面とは反対側の面から、チップ部品領域内貫通孔14a及び14cを通って、チップ部品20とベースプレート10a、10bの間の隙間に充填される。このチップ部品領域内貫通孔14a及び14cの深さは、チップ部品20よりもベースプレート10aおよび10bの厚さが薄いため、チップ部品20の高さより浅い。そのため、これらのチップ部品領域内貫通孔14a及び14cは樹脂により充填し易い効果がある。チップ部品領域内貫通孔14aが、その上に設置するチップ部品20の領域から一部分がはみ出すように形成した場合は、チップ部品領域内貫通孔14aから流入する樹脂が、チップ部品20の領域からはみ出した部分を介してベースプレート10aおよび10bの上下の面間を流通するため、ベースプレート10a又は10bのチップ部品20と反対側の面からチップ部品領域内貫通孔14aを通してチップ部品20を押すことによりチップ部品20がベースプレート10aまたは10bから外される不具合の発生を避けられる効果がある。   In this laminating process, the resin melted from the prepreg passes through the chip component region through holes 14a and 14c from the surface of the base plate opposite to the mounting surface of the chip component 20, and the chip component 20 and the base plate 10a. 10b. The depths of the through hole 14 a and 14 c in the chip component region are shallower than the height of the chip component 20 because the base plates 10 a and 10 b are thinner than the chip component 20. Therefore, these through-holes 14a and 14c in the chip component region have an effect of being easily filled with resin. When the through-hole 14a in the chip component region is formed so that a part thereof protrudes from the region of the chip component 20 installed thereon, the resin flowing in from the through-hole 14a in the chip component region protrudes from the region of the chip component 20. Chip part 20 by pushing the chip part 20 through the through hole 14a in the chip part region from the surface opposite to the chip part 20 of the base plate 10a or 10b. There is an effect of avoiding the occurrence of a problem that 20 is removed from the base plate 10a or 10b.

また、平坦なベースプレート10aおよび10bにチップ部品20をはんだ付けして実装し、そのチップ部品20を、プリプレグ開口部41によって避けたベースプレート10aおよび10b上には、開口プリプレグ42が設置されるので、チップ部品20の周囲をチップ部品20と同じ高さの開口プリプレグ42で支え、全空間が充填される効果がある。これにより、チップ部品20とベースプレート10a、10bの間の隙間に積層ボイドを発生させない効果がある。こうして、図4(b)に示すように、部品付き内層基板17と17bがチップ部品20および集積回路チップ30を対向して設置され、その間に開口プリプレグ42が設置され、外側にプリプレグ40による絶縁樹脂層46と47と銅箔51及び52が積層された印刷配線板中間体50を製造する。   Since the chip component 20 is soldered and mounted on the flat base plates 10a and 10b and the chip component 20 is avoided by the prepreg opening 41, the opening prepreg 42 is installed on the base plates 10a and 10b. The periphery of the chip component 20 is supported by an opening prepreg 42 having the same height as the chip component 20, and the entire space is filled. As a result, there is an effect that no laminated void is generated in the gap between the chip component 20 and the base plates 10a and 10b. In this way, as shown in FIG. 4B, the inner substrates 17 and 17b with components are placed facing the chip component 20 and the integrated circuit chip 30, the opening prepreg 42 is placed between them, and the outer side is insulated by the prepreg 40. The printed wiring board intermediate body 50 in which the resin layers 46 and 47 and the copper foils 51 and 52 are laminated is manufactured.

この工程8では、上記の方法以外に、以下のようにして印刷配線板中間体50を製造することもできる。すなわち、第2の製造方法は、銅箔52とその上のプリプレグ40の代わりに樹脂付き銅箔を用い、銅箔51とその下のプリプレグ40の代わりに樹脂付き銅箔を用いて積層して印刷配線板中間体50を製造することもできる。   In this step 8, in addition to the above method, the printed wiring board intermediate 50 can be manufactured as follows. That is, in the second manufacturing method, a copper foil with resin is used instead of the copper foil 52 and the prepreg 40 thereon, and the copper foil with resin is used instead of the copper foil 51 and the prepreg 40 thereunder. The printed wiring board intermediate 50 can also be manufactured.

また、第3の製造方法として、部品付き内層基板17bと、その上の開口プリプレグ42と、その上の部品付き内層基板17のみを積層して、基板温度を170℃以上で40分以上保持する積層工程で基板を積層し、次に、その基板の表裏に樹脂付き銅箔をラミネートして図4(b)に示す印刷配線板中間体50を製造することも可能である。   As a third manufacturing method, only the inner layer substrate 17b with components, the opening prepreg 42 thereon, and the inner layer substrate 17 with components thereon are stacked, and the substrate temperature is maintained at 170 ° C. or higher for 40 minutes or longer. A printed wiring board intermediate 50 shown in FIG. 4B can be manufactured by laminating a substrate in a laminating step and then laminating a copper foil with resin on both sides of the substrate.

(工程9)
次に、印刷配線板中間体50の外層の銅箔51と52をエッチングして除去する。次に、図5(c)のように、印刷配線板中間体50にドリル加工で直径が0.06mmから2mmのスルホール下孔53を形成する。次に、絶縁樹脂層46と47に、高調波YAGレーザやエキシマレーザなどの紫外線レーザ、炭酸ガスレーザなどの赤外線レーザで穴開け加工することで、配線層11のパターン上に直径が0.04mmから0.2mmのビアホール用穴54を形成する。
(Step 9)
Next, the copper foils 51 and 52 on the outer layer of the printed wiring board intermediate 50 are removed by etching. Next, as shown in FIG. 5C, a through-hole prepared hole 53 having a diameter of 0.06 mm to 2 mm is formed in the printed wiring board intermediate 50 by drilling. Next, the insulating resin layers 46 and 47 are punched with an ultraviolet laser such as a harmonic YAG laser or an excimer laser, or an infrared laser such as a carbon dioxide gas laser, so that the diameter of the wiring layer 11 is 0.04 mm. A 0.2 mm via hole 54 is formed.

(工程10)
次に、絶縁樹脂層46と47の表面に、デスミア、めっき触媒付与及び無電解銅めっきを行って、めっき下地層(図示せず)を形成する。次に、めっき下地層の外側に、レジストを塗布するか、感光性ドライフィルムを貼着するかの方法で感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってめっきレジストパターンを形成する。次に、硫酸銅めっき浴中に浸漬し、めっき下地層をカソードにして電解銅めっきを行うことで、図5(d)のように、絶縁樹脂層46と47の表面に配線層56を形成し、配線層56と一体に、ビアホール用穴54を銅めっきで充填したフィルドビアホール55を形成し、スルホール下孔53の側壁面に銅めっきによるスルホールめっき57を形成する。次に、めっきレジストパターンを剥離処理し、めっきレジストパターン下部にあっためっき下地層をフラッシュエッチングで除去し、配線層56のパターンを形成する。
(Process 10)
Next, desmear, plating catalyst application, and electroless copper plating are performed on the surfaces of the insulating resin layers 46 and 47 to form a plating base layer (not shown). Next, a photosensitive layer is formed by applying a resist or a photosensitive dry film on the outside of the plating base layer, and a series of patterning processes such as pattern exposure and development are performed to form a plating resist pattern. Form. Next, the wiring layer 56 is formed on the surfaces of the insulating resin layers 46 and 47 as shown in FIG. 5D by dipping in a copper sulfate plating bath and performing electrolytic copper plating using the plating base layer as a cathode. Then, a filled via hole 55 in which the via hole hole 54 is filled with copper plating is formed integrally with the wiring layer 56, and a through hole plating 57 by copper plating is formed on the side wall surface of the through hole lower hole 53. Next, the plating resist pattern is peeled off, and the plating base layer under the plating resist pattern is removed by flash etching, thereby forming a pattern of the wiring layer 56.

以上の処理では、配線層56のパターンの形成に、セミアディティブ法を用いたが、これに限定されず、以下のようにして配線総56のパターンを形成することができる。すなわち、先ず、絶縁樹脂層46と47の表面のめっき下地層の外側にめっき下地層をカソードにした電解銅めっきにより、全面形成された配線層56と一体に形成されたフィルドビアホール55とスルホールめっき57を形成し、次に、全面形成された配線層56の外側に、感光性ドライフィルムを貼着して感光層を形成し、パターン露光、現像等の一連のパターニング処理を行ってエッチングレジストパターンを形成する。そして、そのエッチングレジストパターンを保護膜にして配線層56をエッチングして配線層56のパターンを形成することもできる。   In the above processing, the semi-additive method is used for forming the pattern of the wiring layer 56. However, the present invention is not limited to this, and the pattern of the total wiring 56 can be formed as follows. That is, first, filled via holes 55 and through-hole plating formed integrally with the wiring layer 56 formed on the entire surface by electrolytic copper plating using the plating base layer as a cathode outside the plating base layer on the surfaces of the insulating resin layers 46 and 47. 57 is formed, and then a photosensitive dry film is attached to the outside of the wiring layer 56 formed on the entire surface to form a photosensitive layer, and a series of patterning processes such as pattern exposure and development are performed to form an etching resist pattern. Form. Then, the wiring layer 56 can be formed by etching the wiring layer 56 using the etching resist pattern as a protective film.

(工程11)
次に、図5(e)のように、この基板の両面に絶縁樹脂層48を形成する。
(工程12)
次に、図6(f)のように、絶縁樹脂層48の所定位置にスルホール下孔53b、ビアホール用穴54bを形成する。
(工程13)
次に、図6(g)のように、銅めっきにより、ビアホール用穴54bにフィルドビアホール55bを形成し、絶縁樹脂層48の表面に配線層56bを形成し、スルホール下孔53bの側壁面にスルホールめっき57bを形成する。さらに必要であれば、絶縁樹脂層、フィルドビアホール及び配線層56b形成を所定回数繰り返すことにより、所望の層数の配線層56bを形成する。
(Step 11)
Next, as shown in FIG. 5E, insulating resin layers 48 are formed on both surfaces of the substrate.
(Step 12)
Next, as shown in FIG. 6 (f), through-hole lower holes 53 b and via hole holes 54 b are formed at predetermined positions of the insulating resin layer 48.
(Step 13)
Next, as shown in FIG. 6 (g), a filled via hole 55b is formed in the via hole 54b by copper plating, a wiring layer 56b is formed on the surface of the insulating resin layer 48, and the sidewall surface of the through hole lower hole 53b is formed. Through-hole plating 57b is formed. If necessary, the wiring layers 56b having a desired number of layers are formed by repeating the formation of the insulating resin layer, the filled via hole, and the wiring layer 56b a predetermined number of times.

(工程14)
次に、この基板にCZ処理を施し、次に、感光性ソルダーレジストをスプレーコート、ロールコート、カーテンコート、スクリーン法で約20μmの厚さに塗布し乾燥させて外層にソルダーレジストを形成する。または感光性ドライフィルム・ソルダーレジストをロールラミネートで基板に貼り付けてソルダーレジストを形成する。次に、ソルダーレジストを露光・現像し外部接続パッド用開口部を開口させ、加熱硬化させる。次に、外部接続パッド用開口部に、無電解Niめっきを3μm以上形成し、その上に無電解Auめっきを0.03μm以上形成する。無電解Auめっきは1μm以上形成することも可能である。更にその上にはんだプリコートすることも可能である。また、無電解めっきでなく、電解Niめっきを3μm以上形成し、その上に電解Auめっきを0.5μm以上形成することも可能である。あるいは、めっき処理以外に、タフエースなどの有機防錆皮膜を形成することも可能である。
(工程15)
出来上がった基板の外形をダイサーなどで加工することで、個々の部品内蔵印刷配線板を得る。
(Step 14)
Next, the substrate is subjected to CZ treatment, and then a photosensitive solder resist is applied to a thickness of about 20 μm by spray coating, roll coating, curtain coating, or screen method and dried to form a solder resist on the outer layer. Alternatively, a photosensitive dry film / solder resist is attached to a substrate by roll lamination to form a solder resist. Next, the solder resist is exposed and developed to open an opening for the external connection pad, and is cured by heating. Next, 3 μm or more of electroless Ni plating is formed in the external connection pad opening, and 0.03 μm or more of electroless Au plating is formed thereon. The electroless Au plating can be formed to 1 μm or more. Further, it is possible to pre-coat with solder. Further, instead of electroless plating, electrolytic Ni plating can be formed to 3 μm or more, and electrolytic Au plating can be formed thereon to 0.5 μm or more. Alternatively, an organic rust preventive film such as tough ace can be formed in addition to the plating treatment.
(Step 15)
The printed circuit board with built-in components is obtained by processing the outer shape of the finished board with a dicer.

また、本実施形態で、図5(d)のスルホールめっき57、及び図6(g)のスルホールめっき57bを、スルホール下孔53及び53bの孔の空間全体を充填する充填型のスルホールめっき57、57bで形成することも可能である。   Further, in this embodiment, the through-hole plating 57 of FIG. 5D and the through-hole plating 57b of FIG. 6G are replaced with a filling-type through-hole plating 57 that fills the entire space of the through-hole lower holes 53 and 53b, It is also possible to form with 57b.

本実施形態では、チップ部品20及び集積回路チップ30をベースプレート10a、10bのランド13及び13bにはんだ22及びはんだバンプ312で接合した部品付き内層基板17a、17bを形成し、工程8の積層工程で、部品付き内層基板17a、17bのチップ部品20及び集積回路チップ30を対向させて、その基板間に開口プリプレグ42を挟んで、積層して印刷配線板中間体50を形成した。そして、その積層の際に、チップ部品20とベースプレート10a、10bとの間の隙間に、チップ部品領域内貫通孔14a、14cを通して十分に樹脂が充填されて積層ボイドの発生を防いだので、完成した部品内蔵印刷配線板に部品をはんだ付けする際の加熱処理によってチップ部品20の電極21とランド13を接合するはんだが再溶融しても、そのはんだは位置を移動せず、内蔵したチップ部品20のランド13間が再溶融はんだで短絡する不具合は発生しない、信頼性の高い部品内蔵印刷配線板が得られる効果がある。そのため、チップ部品20の電極21とランド13を接合するはんだ付けに高温はんだを使わないでも良いため、はんだ付け温度を高温にせずベースプレート10a、10bに与える損傷を少なくできるので品質の良い部品内蔵印刷配線板が得られる効果がある。   In this embodiment, the component-attached inner layer substrates 17a and 17b are formed by joining the chip component 20 and the integrated circuit chip 30 to the lands 13 and 13b of the base plates 10a and 10b with the solder 22 and the solder bumps 312. The printed circuit board intermediate 50 was formed by stacking the chip component 20 and the integrated circuit chip 30 of the inner layer substrates 17a and 17b with components facing each other and sandwiching the opening prepreg 42 between the substrates. During the lamination, the gap between the chip component 20 and the base plates 10a and 10b is sufficiently filled with the resin through the through-holes 14a and 14c in the chip component region to prevent the generation of laminated voids. Even if the solder for joining the electrode 21 and the land 13 of the chip component 20 is remelted by heat treatment when soldering the component to the printed wiring board with built-in component, the solder does not move, and the embedded chip component There is an effect that a highly reliable printed wiring board with a built-in component can be obtained without causing a problem that the 20 lands 13 are short-circuited with remelted solder. Therefore, since it is not necessary to use high-temperature solder for soldering to join the electrode 21 and the land 13 of the chip component 20, it is possible to reduce damage to the base plates 10 a and 10 b without increasing the soldering temperature, so that high-quality component built-in printing is possible. There is an effect that a wiring board is obtained.

<第2の実施形態>
第2の実施形態として、図7のように、チップ部品領域内貫通孔14cを形成したベースプレート10bに、チップ部品20の表面にディスペンサー等で保護樹脂液を塗布し、その保護樹脂液をベースプレート10bのチップ部品領域内貫通孔14cから流出させることで、チップ部品20とベースプレート10bの間隙を保護樹脂で充填した保護樹脂層33を形成しても良い。一方、集積回路チップ30を、バンプ電極31を上方に向け(フェイスアップ)、背面を接着剤34でベースプレート10bに接着して設置して部品付き内層基板17bを形成し、工程8の積層工程で、図4に示すように、こうして形成した部品付き内層基板17bと開口プリプレグ40等を積層して印刷配線板中間体を形成し、その後のビルドアップ工程を経て、所望の部品内蔵印刷配線板を製造することも可能である。
<Second Embodiment>
As a second embodiment, as shown in FIG. 7, a protective resin liquid is applied to the surface of the chip component 20 with a dispenser or the like on the base plate 10b in which the through hole 14c in the chip component region is formed, and the protective resin liquid is applied to the base plate 10b. The protective resin layer 33 in which the gap between the chip component 20 and the base plate 10b is filled with the protective resin may be formed by flowing out of the through hole 14c in the chip component region. On the other hand, the integrated circuit chip 30 is placed with the bump electrode 31 facing upward (face up) and the back surface adhered to the base plate 10b with an adhesive 34 to form the component-attached inner substrate 17b. As shown in FIG. 4, a printed wiring board intermediate body is formed by laminating the thus formed inner substrate 17b with components, the opening prepreg 40, etc., and a desired built-in printed wiring board is obtained through a subsequent build-up process. It is also possible to manufacture.

また、本発明は、チップ部品20の厚さより薄い絶縁性樹脂板にチップ部品領域内貫通孔14aを形成し配線層11及びランド13を形成したベースプレート10aに、そのチップ部品領域内貫通孔14a上にチップ部品20を設置し、その電極21を配線層11のランド13にはんだ付けした部品付き内層基板17を製造することに特徴がある。図4に示す工程8の積層工程において、必ずしも、第2の部品付き内層基板17bを対向させずに、部品付き内層基板17のチップ部品20を避けるプリプレグ開口部41を形成した開口プリプレグ42とプリプレグ40と銅箔51および52を積層することで、部品内蔵印刷配線板を得ることができる。その場合においても、積層の際に、チップ部品20とベースプレート10aとの間の隙間に、チップ部品領域内貫通孔14aを通して十分に樹脂が充填されて積層ボイドの発生を防ぎ、完成した部品内蔵印刷配線板に部品をはんだ付けする際の加熱処理によってもチップ部品20の電極21とランド13を接合するはんだが位置を移動せず、内蔵したチップ部品20のランド13間が再溶融はんだで短絡する不具合が発生しない、信頼性の高い部品内蔵印刷配線板が得られる効果がある。   Further, the present invention provides a base plate 10a in which a through hole 14a in a chip component region is formed in an insulating resin plate thinner than the thickness of the chip component 20 and a wiring layer 11 and a land 13 are formed on the through hole 14a in the chip component region. The chip component 20 is installed on the inner layer substrate 17 and the component inner layer substrate 17 is manufactured by soldering the electrode 21 to the land 13 of the wiring layer 11. In the stacking step of step 8 shown in FIG. 4, the prepreg 42 and the prepreg in which the prepreg opening 41 that avoids the chip component 20 of the inner layer substrate 17 with components is formed without necessarily facing the inner layer substrate 17b with second components. By laminating 40 and copper foils 51 and 52, a component built-in printed wiring board can be obtained. Even in such a case, during the stacking, the gap between the chip component 20 and the base plate 10a is sufficiently filled with the resin through the through hole 14a in the chip component region to prevent the generation of the stacked void, and the completed component built-in printing The solder for joining the electrode 21 and the land 13 of the chip component 20 does not move even by the heat treatment when soldering the component to the wiring board, and the land 13 of the built-in chip component 20 is short-circuited by remelting solder. There is an effect that a highly reliable printed wiring board with built-in components that does not cause defects can be obtained.

なお、本発明のベースプレート10a又は10bの配線層11に、造りこみ素子設置用のランド13を形成し、そのランド13に電気接続する抵抗体ペーストをスクリーン印刷して内部抵抗部品を形成し、そのベースプレート10a又は10bにチップ部品20を設置して部品付き内層基板17又は17bを形成することができる。それに対して、以降の第1の実施形態の工程5から工程15の製造工程により、部品内蔵印刷配線を製造することができる。   In addition, a land 13 for forming a built-in element is formed on the wiring layer 11 of the base plate 10a or 10b of the present invention, and a resistor paste electrically connected to the land 13 is screen printed to form an internal resistance component. The chip component 20 can be installed on the base plate 10a or 10b to form the component-attached inner layer substrate 17 or 17b. On the other hand, the component built-in printed wiring can be manufactured by the following manufacturing steps from Step 5 to Step 15 of the first embodiment.

本発明の第1の実施形態の第1の部品付き内層基板の製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the 1st component-attached inner layer board | substrate of the 1st Embodiment of this invention. 本発明の第1の実施形態の第2の部品付き内層基板の製造工程の一部を模式的に示す断面図である。It is sectional drawing which shows typically a part of manufacturing process of the 2nd layer inner board | substrate with a component of the 1st Embodiment of this invention. 本発明の第1の実施形態の第2の部品付き内層基板の製造工程の一部を模式的に示す断面図である。It is sectional drawing which shows typically a part of manufacturing process of the 2nd layer inner board | substrate with a component of the 1st Embodiment of this invention. 本発明の実施形態の印刷配線板中間体の製造工程を模式的に示す断面図である。It is sectional drawing which shows typically the manufacturing process of the printed wiring board intermediate body of embodiment of this invention. 本発明の実施形態の部品内蔵印刷配線板の製造工程の一部を模式的に示す断面図である。It is sectional drawing which shows typically a part of manufacturing process of the component built-in printed wiring board of embodiment of this invention. 本発明の実施形態の部品内蔵印刷配線板の製造工程の一部を模式的に示す断面図である。It is sectional drawing which shows typically a part of manufacturing process of the component built-in printed wiring board of embodiment of this invention. 本発明の第2の実施形態の部品付き内層基板を模式的に示す断面図である。It is sectional drawing which shows typically the inner layer board | substrate with components of the 2nd Embodiment of this invention.

符号の説明Explanation of symbols

10a、10b……ベースプレート
11、56、56b・・・配線層
13、13b・・・ランド
14、14b・・・開口部
14a、14c・・・チップ部品領域内貫通孔
17、17b・・・部品付き内層基板
20・・・チップ部品
21・・・電極
22・・・はんだ
30・・・集積回路チップ
31・・・バンプ電極
32・・・はんだバンプ
33・・・保護樹脂層
34・・・接着剤
40・・・プリプレグ
41・・・プリプレグ開口部
42・・・開口プリプレグ
46、47、48・・・絶縁樹脂層
50・・・印刷配線板中間体
51、52……銅箔
53、53b・・・スルホール下孔
54、54b・・・ビアホール用穴
55、55b・・・フィルドビアホール
57、57b・・・スルホールめっき
10a, 10b ... Base plates 11, 56, 56b ... Wiring layers 13, 13b ... Lands 14, 14b ... Openings 14a, 14c ... Through holes 17, 17b in the chip component region Inner layer substrate 20 ... chip component 21 ... electrode 22 ... solder 30 ... integrated circuit chip 31 ... bump electrode 32 ... solder bump 33 ... protective resin layer 34 ... adhesion Agent 40 ... Prepreg 41 ... Prepreg opening 42 ... Opening prepreg 46, 47, 48 ... Insulating resin layer 50 ... Printed wiring board intermediate 51, 52 ... Copper foil 53, 53b ..Through hole lower holes 54, 54b ... Via hole holes 55, 55b ... Filled via holes 57, 57b ... Through hole plating

Claims (4)

絶縁性樹脂板に貫通孔を形成し配線層を形成したベースプレートに、前記ベースプレートの厚さより厚いチップ部品を前記貫通孔を覆って設置し、前記チップ部品の電極を前記配線層にはんだ付けした部品付き内層基板を製造する第1の工程と、前記部品付き内層基板上の前記チップ部品側に該チップ部品をプリプレグ開口部によって避けた開口プリプレグを設置し、前記部品付き内層基板上の前記チップ部品設置面と反対面側にプリプレグを設置して積層し加熱・加圧することで印刷配線板中間体を製造する第2の工程と、前記印刷配線板中間体にスルホール下孔を形成する第3の工程と、銅めっきにより前記スルホール下孔に形成したスルホールめっきと前記印刷配線板中間体の外層の配線層を形成する第4の工程を有することを特徴とする部品内蔵印刷配線板の製造方法。   A component in which a chip component thicker than the thickness of the base plate is installed on a base plate in which a through hole is formed in an insulating resin plate and a wiring layer is formed, and the electrode of the chip component is soldered to the wiring layer A first step of manufacturing an inner layer substrate with a chip, and an opening prepreg avoiding the chip component by a prepreg opening on the chip component side on the inner layer substrate with a component, and the chip component on the inner layer substrate with a component A second step of producing a printed wiring board intermediate by installing a prepreg on the opposite side of the installation surface, laminating, heating and pressurizing, and a third step of forming a through-hole prepared hole in the printed wiring board intermediate; And a fourth step of forming a through hole plating formed in the through hole prepared hole by copper plating and an outer wiring layer of the printed wiring board intermediate body. Method for producing that component embedded printed wiring board. 請求項1記載の部品内蔵印刷配線板の製造方法において、前記第1の工程で、前記部品付き内層基板を製造するとともに、第2のベースプレートの配線層にチップ部品又は集積回路チップの電極をはんだ付けした電子部品付き内層基板を製造し、前記第2の工程で、前記部品付き内層基板と前記電子部品付き内層基板を、前記チップ部品と前記電子部品を互いに向かい合わせて配置し、前記部品付き内層基板と前記電子部品付き内層基板の間に前記開口プリプレグを挟んで積層し加熱・加圧することで印刷配線板中間体を製造することを特徴とする部品内蔵印刷配線板の製造方法。   2. The method of manufacturing a component built-in printed wiring board according to claim 1, wherein in the first step, the inner substrate with the component is manufactured, and an electrode of a chip component or an integrated circuit chip is soldered to the wiring layer of the second base plate. In the second step, the inner layer substrate with components and the inner layer substrate with electronic components are arranged so that the chip components and the electronic components face each other, and with the components A method of manufacturing a printed wiring board with a built-in component, wherein a printed wiring board intermediate is manufactured by laminating an opening prepreg between an inner layer board and the inner layer board with electronic components, and heating and pressing. 絶縁性樹脂板に貫通孔を形成し配線層を形成したベースプレートに、前記配線層に電極がはんだ付けされた前記ベースプレートの厚さより厚いチップ部品を前記貫通孔を覆って設置した部品付き内層基板と、前記部品付き内層基板上の前記チップ部品側に該チップ部品をプリプレグ開口部によって避けた開口プリプレグを積層して形成された第1の絶縁性樹脂層と、前記部品付き内層基板上の前記チップ部品設置面と反対面側にプリプレグを積層して形成された第2の絶縁性樹脂層とを備えた印刷配線板中間体を有し、前記印刷配線板中間体の外層に配線層を備え、前記印刷配線板中間体を貫通するスルホールを備えたことを特徴とする部品内蔵印刷配線板。   An inner layer substrate with components in which a chip component thicker than the thickness of the base plate in which an electrode is soldered to the wiring layer is installed on the base plate in which a through hole is formed in an insulating resin plate to form a wiring layer; A first insulating resin layer formed by laminating an opening prepreg on which the chip component is avoided by a prepreg opening on the chip component side on the inner layer substrate with the component, and the chip on the inner layer substrate with the component A printed wiring board intermediate having a second insulating resin layer formed by laminating a prepreg on the side opposite to the component installation surface, and a wiring layer on the outer layer of the printed wiring board intermediate; A component built-in printed wiring board comprising a through hole penetrating the printed wiring board intermediate body. 請求項3記載の部品内蔵印刷配線板において、前記部品付き内層基板とともに、第2のベースプレートの配線層にチップ部品又は集積回路チップの電極をはんだ付けした電子部品付き内層基板を有し、前記部品付き内層基板と前記電子部品付き内層基板が、前記チップ部品と前記電子部品を互いに向かい合わせて配置し、前記部品付き内層基板と前記電子部品付き内層基板の間に前記開口プリプレグを挟んで積層して形成された前記第1の絶縁樹脂層を有することを特徴とする部品内蔵印刷配線板。   4. The component built-in printed wiring board according to claim 3, further comprising an inner layer substrate with an electronic component in which an electrode of a chip component or an integrated circuit chip is soldered to a wiring layer of a second base plate together with the inner layer substrate with the component. The inner layer substrate with an electronic component and the inner layer substrate with an electronic component are arranged such that the chip component and the electronic component face each other and the opening prepreg is sandwiched between the inner layer substrate with the component and the inner layer substrate with the electronic component. A printed wiring board with a built-in component, comprising the first insulating resin layer formed as described above.
JP2008157595A 2008-06-17 2008-06-17 Component built-in printed wiring board and method of manufacturing the same Pending JP2009302437A (en)

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JP2008157595A JP2009302437A (en) 2008-06-17 2008-06-17 Component built-in printed wiring board and method of manufacturing the same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113891582A (en) * 2021-09-26 2022-01-04 东莞康源电子有限公司 Novel method for processing embedded chip carrier plate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204167A (en) * 2001-10-26 2003-07-18 Matsushita Electric Works Ltd Sheet material for circuit board and manufacturing method thereof, and multilayer board and manufacturing method thereof
JP2004311736A (en) * 2003-04-08 2004-11-04 Nec Toppan Circuit Solutions Inc Method for manufacturing built-up multilayer wiring board incorporating chip comp0nents
JP2006041000A (en) * 2004-07-23 2006-02-09 Cmk Corp Component built-in printed wiring board and its manufacturing method
JP2007035689A (en) * 2005-07-22 2007-02-08 Matsushita Electric Ind Co Ltd Method of manufacturing electronic component built-in substrate

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003204167A (en) * 2001-10-26 2003-07-18 Matsushita Electric Works Ltd Sheet material for circuit board and manufacturing method thereof, and multilayer board and manufacturing method thereof
JP2004311736A (en) * 2003-04-08 2004-11-04 Nec Toppan Circuit Solutions Inc Method for manufacturing built-up multilayer wiring board incorporating chip comp0nents
JP2006041000A (en) * 2004-07-23 2006-02-09 Cmk Corp Component built-in printed wiring board and its manufacturing method
JP2007035689A (en) * 2005-07-22 2007-02-08 Matsushita Electric Ind Co Ltd Method of manufacturing electronic component built-in substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113891582A (en) * 2021-09-26 2022-01-04 东莞康源电子有限公司 Novel method for processing embedded chip carrier plate

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