JP2009302216A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2009302216A
JP2009302216A JP2008153628A JP2008153628A JP2009302216A JP 2009302216 A JP2009302216 A JP 2009302216A JP 2008153628 A JP2008153628 A JP 2008153628A JP 2008153628 A JP2008153628 A JP 2008153628A JP 2009302216 A JP2009302216 A JP 2009302216A
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semiconductor chip
substrate
flexible wiring
wiring board
electrode
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Tomokazu Honda
友和 本田
Yuji Noda
勇次 野田
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Yaskawa Electric Corp
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Yaskawa Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that eliminates trouble such as deformation, contacting, etc., of a wire in a resin sealing stage, and is reduced in height when mounted on a printed wiring board etc., to be made thin, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device includes a semiconductor chip 3 mounted on a substrate 4, a flexible wiring board 1 processed into a shape substantially conforming with an external surface of the semiconductor chip 3, and a resin 2 sealing the semiconductor chip 3 and flexible wiring board 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置およびその製造方法、特に、半導体チップおよびフレキシブル配線基板を樹脂封止した半導体装置に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor chip and a flexible wiring substrate are sealed with a resin.

従来の半導体装置のパッケージの一例が図６に示されている。この例では、半導体チップ３が接着剤によりインターポーザー基板４上に接合され、半導体チップ３上の電極パッドとインターポーザー基板４上のパッドとがボンディングワイヤー６３により電気的に接続され、樹脂モールド２により封止されていた。インターポーザー基板４の下面のパッドにはプリント配線板に接続するためのはんだボール６１が設けられている。   An example of a conventional semiconductor device package is shown in FIG. In this example, the semiconductor chip 3 is bonded onto the interposer substrate 4 with an adhesive, and the electrode pads on the semiconductor chip 3 and the pads on the interposer substrate 4 are electrically connected by the bonding wires 63, and the resin mold 2. It was sealed by. Solder balls 61 for connecting to the printed wiring board are provided on the pads on the lower surface of the interposer substrate 4.

上記の例では、樹脂封止の工程おいて熱硬化前の溶融樹脂をパッケージ成型用の金型に注入する際に、樹脂内に内在する気泡または樹脂の注入中に巻き込んだ気泡が金型内に発生する。この気泡はボンディングワイヤーに圧力を与え、結果的に、ワイヤーの変形または隣接するワイヤー同士の接触等の問題を発生させる可能性がある。変形、接触等は半導体装置のパッケージ不良の一因にもなり、最終的には、半導体装置の製造工程における歩留まりの低下にもつながる。そのため、樹脂封止の工程では、樹脂の粘性、注入スピード、金型における注入位置を考慮して、樹脂や気泡の流れがワイヤーに影響を与えない条件を選定する必要があった。   In the above example, when the molten resin before thermosetting is injected into the mold for molding the resin in the resin sealing process, the bubbles present in the resin or the bubbles entrained during the injection of the resin are contained in the mold. Occurs. The bubbles may apply pressure to the bonding wire, and as a result, may cause problems such as deformation of the wire or contact between adjacent wires. Deformation, contact, and the like also contribute to package defects of the semiconductor device, and ultimately lead to a decrease in yield in the manufacturing process of the semiconductor device. Therefore, in the resin sealing process, it is necessary to select conditions under which the flow of the resin or bubbles does not affect the wire in consideration of the viscosity of the resin, the injection speed, and the injection position in the mold.

このようなワイヤーを用いたパッケージに代わって、フレキシブル基板を用いた半導体パッケージが提案されている。このパッケージの一例が図７に示される。この例では、半導体チップ３とフレキシブル基板１を接合し、そのフレキシブル基板１で半導体チップ３の全面を覆うように形成している。
特開平８−９７３１２号 特開平９−１８６２６７号 A semiconductor package using a flexible substrate has been proposed in place of the package using such a wire. An example of this package is shown in FIG. In this example, the semiconductor chip 3 and the flexible substrate 1 are joined, and the flexible substrate 1 is formed so as to cover the entire surface of the semiconductor chip 3.
JP-A-8-97312 JP-A-9-186267

図７に示された例では、フレキシブル基板で半導体チップのほぼ全面を覆う構造となるので、フレキシブル基板の成形工程や半導体パッケージの製造工程が複雑になる。また、はんだボールの高さやフレキシブル基板の厚みが積み重なり、プリント配線板に実装する際、半導体装置の高さが高くなってしまうという問題がある。
本発明はこのような問題点に鑑みてなされたものであり、樹脂封止の工程におけるワイヤーの変形、接触等の不具合を無くすとともに、半導体装置をプリント配線基板等に実装する際の半導体装置の高さを低減し、薄型化を実現することができる半導体装置およびその半導体装置の製造方法を提供することを目的とする。 In the example shown in FIG. 7, the flexible substrate covers almost the entire surface of the semiconductor chip, which complicates the flexible substrate molding process and the semiconductor package manufacturing process. In addition, the height of the solder balls and the thickness of the flexible substrate are stacked, and there is a problem that the height of the semiconductor device becomes high when mounted on a printed wiring board.
The present invention has been made in view of such problems, and eliminates defects such as wire deformation and contact in the resin sealing process, and also provides a semiconductor device for mounting a semiconductor device on a printed wiring board or the like. It is an object of the present invention to provide a semiconductor device that can be reduced in height and thinned and a method for manufacturing the semiconductor device.

上記の目的を達成するため、本発明は以下の構成より成る。   In order to achieve the above object, the present invention comprises the following arrangement.

請求項１記載の発明は、
複数の基板電極が形成された電極形成領域と、搭載領域と、前記複数の電極に接続された複数の配線とを備えた基板と、
複数のチップ電極が形成された主表面と、前記主表面と反対側の裏面とを有し、前記搭載領域に前記裏面を対向させて搭載された半導体チップと、
前記複数の基板電極に前記電極形成領域内で接続された第１電極群と、前記複数のチップ電極に前記主表面上で接続された第２電極群とを有し、少なくても前記電極形成領域上から前記主表面上まで延在した、可とう性材料より構成されたフレキシブル配線基板と、
前記半導体チップおよび前記フレキシブル配線基板を被覆する樹脂とを備える半導体装置である。 The invention described in claim 1
A substrate including an electrode formation region in which a plurality of substrate electrodes are formed, a mounting region, and a plurality of wirings connected to the plurality of electrodes;
A semiconductor chip that has a main surface on which a plurality of chip electrodes are formed and a back surface opposite to the main surface, and is mounted with the back surface facing the mounting region;
A first electrode group connected to the plurality of substrate electrodes in the electrode formation region; and a second electrode group connected to the plurality of chip electrodes on the main surface. A flexible wiring board made of a flexible material extending from above the region to the main surface;
A semiconductor device comprising the semiconductor chip and a resin covering the flexible wiring board.

請求項２記載の発明は、請求項１記載の構成に加え、
前記電極形成領域は第１の領域および第２の領域からなり、前記搭載領域は前記第１の領域と前記第２の領域間に配置され、前記第１の領域には前記複数の基板電極の内の第１の電極が形成され、前記第２の領域には前記複数の基板電極の内の第２の電極が形成され、
前記フレキシブル配線基板は前記第１の領域から前記第２の領域まで前記主表面を介して延在すると共に、前記半導体チップの外表面に実質的に対応した形状に加工されている。 In addition to the structure of Claim 1, the invention of Claim 2 has
The electrode formation region includes a first region and a second region, the mounting region is disposed between the first region and the second region, and the first region includes a plurality of substrate electrodes. A first electrode is formed, and a second electrode of the plurality of substrate electrodes is formed in the second region,
The flexible wiring board extends from the first region to the second region via the main surface and is processed into a shape substantially corresponding to the outer surface of the semiconductor chip.

請求項３記載の発明は、請求項２記載の構成に加え、
前記半導体チップは第１の半導体チップおよび第２の半導体チップからなり、前記第１の半導体チップには第１のＭＯＳＦＥＴが形成され、前記第２の半導体チップには第２のＭＯＳＦＥＴが形成され、前記第１のＭＯＳＦＥＴと前記第２のＭＯＳＦＥＴとは出力ノードを介して直列接続されたインバータ回路を構成する。 In addition to the structure of Claim 2, the invention of Claim 3 is
The semiconductor chip comprises a first semiconductor chip and a second semiconductor chip, a first MOSFET is formed on the first semiconductor chip, and a second MOSFET is formed on the second semiconductor chip, The first MOSFET and the second MOSFET constitute an inverter circuit connected in series via an output node.

請求項４記載の発明は、請求項３記載の構成に加え、
前記搭載領域は前記第１の半導体チップを搭載する第１の搭載領域と前記第２の半導体チップを搭載する第２の搭載領域とに分割され、前記第１の搭載領域と前記第２の搭載領域間には前記複数の基板電極の内の第３の電極が形成され、前記出力ノードは前記第３の電極に接続されている。 In addition to the structure of Claim 3, the invention of Claim 4 is
The mounting area is divided into a first mounting area for mounting the first semiconductor chip and a second mounting area for mounting the second semiconductor chip, and the first mounting area and the second mounting area. A third electrode of the plurality of substrate electrodes is formed between the regions, and the output node is connected to the third electrode.

請求項５記載の発明は、請求項３または４記載の構成に加え、
半導体装置における前記出力ノードが接続された制御端子を有するモータである。 The invention according to claim 5 is in addition to the structure according to claim 3 or 4,
A motor having a control terminal to which the output node is connected in a semiconductor device.

請求項６記載の発明は、
半導体チップを可とう性材料より構成されたフレキシブル配線基板上に実装し、前記半導体チップ上に形成された電極と前記フレキシブル配線基板上に形成された電極とを接続する工程と、
前記半導体チップおよび前記フレキシブル配線基板を金型内に挿入し、前記フレキシブル配線基板を前記半導体チップの外表面に実質的に対応した形状に加工する工程と、
前記加工する工程の後、前記半導体チップの前記電極が形成された表面とは反対側の裏面および前記フレキシブル配線基板の端部を基板上に接合する工程と、
前記基板上の前記半導体チップおよび前記フレキシブル配線基板を樹脂により被覆する工程とを備える半導体装置の製造方法である。 The invention described in claim 6
Mounting a semiconductor chip on a flexible wiring board made of a flexible material, and connecting the electrode formed on the semiconductor chip and the electrode formed on the flexible wiring board;
Inserting the semiconductor chip and the flexible wiring board into a mold, and processing the flexible wiring board into a shape substantially corresponding to the outer surface of the semiconductor chip;
After the step of processing, a step of bonding the back surface of the semiconductor chip opposite to the surface on which the electrode is formed and the end of the flexible wiring substrate on the substrate;
And a step of coating the semiconductor chip and the flexible wiring board on the substrate with a resin.

請求項７記載の発明は、請求項６記載の構成に加え、
前記フレキシブル配線基板を構成する可とう性材料は、前記樹脂の硬化温度より高いガラス転移温度を有する。 In addition to the structure of Claim 6, this invention of Claim 7
The flexible material constituting the flexible wiring board has a glass transition temperature higher than the curing temperature of the resin.

請求項８記載の発明は、請求項６または７記載の構成に加え、
前記フレキシブル配線基板の端部を前記基板上に接合することにより、前記フレキシブル配線基板上に形成された電極と前記基板上に形成された電極とが電気的に接続される。
請求項９記載の発明は、請求項１乃至４記載の半導体装置を備えたモータの制御装置である。 The invention described in claim 8 has the configuration described in claim 6 or 7,
By joining the end portion of the flexible wiring substrate onto the substrate, the electrode formed on the flexible wiring substrate and the electrode formed on the substrate are electrically connected.
A ninth aspect of the present invention is a motor control device including the semiconductor device according to the first to fourth aspects.

請求項１記載の発明によれば、信頼性の高い、薄型の半導体装置を実現することができる。   According to the first aspect of the present invention, a thin semiconductor device with high reliability can be realized.

請求項２記載の発明によれば、請求項１記載の発明により得られる効果に加え、半導体チップの一側面側から他側面側まで、フレキシブル配線基板が半導体チップの外表面に実質的に対応した形状で延在するので、半導体チップおよびフレキシブル配線基板上の電極のレイアウトに余裕ができ、設計の自由度が上がる。さらに、年々、薄くなっている半導体チップを外的な応力からフレキシブル配線基板により保護することもできる。   According to the invention described in claim 2, in addition to the effects obtained by the invention described in claim 1, the flexible wiring board substantially corresponds to the outer surface of the semiconductor chip from one side surface side to the other side surface side of the semiconductor chip. Since it extends in shape, there is room in the layout of the electrodes on the semiconductor chip and the flexible wiring board, and the degree of freedom in design increases. Furthermore, a semiconductor chip that is becoming thinner year by year can be protected from external stress by a flexible wiring board.

請求項３記載の発明によれば、請求項２記載の発明により得られる効果に加え、薄型化されたインバータ回路を実現することができる。   According to the invention described in claim 3, in addition to the effect obtained by the invention described in claim 2, a thinned inverter circuit can be realized.

請求項４記載の発明によれば、請求項３記載の発明により得られる効果に加え、半導体チップ間の配線距離を短くすることができる。   According to the invention described in claim 4, in addition to the effect obtained by the invention described in claim 3, the wiring distance between the semiconductor chips can be shortened.

請求項５記載の発明によれば、請求項３または４記載の発明により得られる効果に加え、小型化、およびノイズに強い制御またはノイズを出し難い制御を可能にしたモータを実現できる。   According to the invention described in claim 5, in addition to the effects obtained by the invention described in claim 3 or 4, it is possible to realize a motor that can be downsized and control resistant to noise or difficult to generate noise.

請求項６乃至８記載の発明によれば、信頼性の高い、薄型の半導体装置を少ない工程で製造することができる。
請求項９記載の発明によれば、小型化されたモータの制御装置を実現することができる。 According to the sixth to eighth aspects of the invention, a highly reliable and thin semiconductor device can be manufactured with a small number of steps.
According to the ninth aspect of the present invention, it is possible to realize a motor control device that is downsized.

以下、本発明の実施の形態について図面を参照して説明する。本実施形態における図面では、発明の理解を容易にするため、一部の要素においては模式的に示されている。本欄では、前出の構成要素については同一符号を付すことにより、その説明が省略されることもある。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings in the present embodiment, some elements are schematically shown in order to facilitate understanding of the invention. In this section, the same components as those described above are denoted by the same reference numerals, and the description thereof may be omitted.

本実施形態における半導体装置の断面図を図１に示し、二等角斜投影図を図２に示す。図には、フレキシブル配線基板１、樹脂２、半導体チップ３、インターポーザー基板４、フレキシブル配線基板１と半導体チップ３との間の接合材料５（これに対応するフレキシブル配線基板１と半導体チップ３間の接合部２５が図２に示される）、フレキシブル配線基板１とインターポーザー基板４との間の接合材料６（これに対応するフレキシブル配線基板１とインターポーザー基板４との間の接合部２６が図２に示される）、インターポーザー基板４と半導体チップ３とを接着する接着剤７が示されている。   A cross-sectional view of the semiconductor device according to the present embodiment is shown in FIG. 1, and an isometric view is shown in FIG. The figure shows a flexible wiring substrate 1, a resin 2, a semiconductor chip 3, an interposer substrate 4, and a bonding material 5 between the flexible wiring substrate 1 and the semiconductor chip 3 (between the corresponding flexible wiring substrate 1 and the semiconductor chip 3. 2), the bonding material 6 between the flexible wiring substrate 1 and the interposer substrate 4 (the corresponding bonding portion 26 between the flexible wiring substrate 1 and the interposer substrate 4 is provided). An adhesive 7 for bonding the interposer substrate 4 and the semiconductor chip 3 is shown in FIG.

半導体チップ３の主表面上には複数のチップ電極が形成され、その電極上に接合材料５が形成されている。この主表面と反対側の裏面は接着剤７によりインターポーザー基板４の表面上に固定されている。   A plurality of chip electrodes are formed on the main surface of the semiconductor chip 3, and a bonding material 5 is formed on the electrodes. The back surface opposite to the main surface is fixed on the surface of the interposer substrate 4 with an adhesive 7.

インターポーザー基板４には、複数の基板電極が形成された電極形成領域Ｘと、半導体チップ３が搭載される搭載領域Ｙ１、Ｙ２とが定義されている。複数の基板電極は、接合材料６を介してフレキシブル配線基板５の電極群とそれぞれ接続される。   The interposer substrate 4 defines an electrode formation region X in which a plurality of substrate electrodes are formed, and mounting regions Y1 and Y2 on which the semiconductor chip 3 is mounted. The plurality of substrate electrodes are respectively connected to the electrode group of the flexible wiring substrate 5 through the bonding material 6.

フレキシブル配線基板１は可とう性の材料により構成され、半導体チップ３の外表面に実質的に対応した形状に加工され、電極形成領域Ｙ１から半導体チップ３の主表面上を介して電極形成領域Ｙ２まで延在している。ここで言う実質的に対応した形状とは、半導体チップに対して概してコンフォーマルな形状、すなわち、現実的に可能な範囲の加工形状を言うものである。このフレキシブル配線基板１には、電極形成領域Ｘでインターポーザー基板４の基板電極と接続する複数の電極（第１電極群）および半導体チップ３の主表面上でチップ電極と接続する複数の電極（第２電極群）が形成されている。なお、第１電極群および第２電極群の形成された位置は図２の接合部２６、接合部２５がそれぞれ対応する。   The flexible wiring board 1 is made of a flexible material and is processed into a shape substantially corresponding to the outer surface of the semiconductor chip 3, and the electrode forming area Y <b> 2 passes through the main surface of the semiconductor chip 3 from the electrode forming area Y <b> 1. It extends to. The substantially corresponding shape mentioned here refers to a generally conformal shape with respect to the semiconductor chip, that is, a processing shape that is practically possible. The flexible wiring board 1 includes a plurality of electrodes (first electrode group) connected to the substrate electrode of the interposer substrate 4 in the electrode formation region X and a plurality of electrodes (first electrode group) connected to the chip electrode on the main surface of the semiconductor chip 3 ( A second electrode group) is formed. The positions where the first electrode group and the second electrode group are formed correspond to the joint portion 26 and the joint portion 25 in FIG. 2, respectively.

本実施形態におけるフレキシブル配線基板１はポリイミドと銅から構成され、厚さは２０μｍである。本実施形態で用いた半導体チップ３の厚さは７００μｍであるので、フレキシブル配線基板１は半導体チップ３に比べ、格段に薄い。なお、フレキシブル配線基板の構成材料および厚さは、半導体チップの厚さ、製造工程の条件により適宜設定されるものであるが、本実施形態のようにフレキシブル配線基板の厚さは半導体チップの厚さより３０分の１（１／３０）以上薄いものが好ましい。   The flexible wiring board 1 in the present embodiment is made of polyimide and copper and has a thickness of 20 μm. Since the thickness of the semiconductor chip 3 used in this embodiment is 700 μm, the flexible wiring board 1 is much thinner than the semiconductor chip 3. The constituent material and thickness of the flexible wiring board are appropriately set according to the thickness of the semiconductor chip and the conditions of the manufacturing process, but the thickness of the flexible wiring board is the thickness of the semiconductor chip as in this embodiment. In addition, a thin film of 1/30 or more is preferable.

本実施形態のフレキシブル配線基板１は、樹脂２の硬化温度より高いガラス転移温度を有するものを用いる。本実施形態の樹脂２の硬化温度は１７０℃―１９０℃なので、ガラス転移温度が３５０℃のフレキシブル配線基板を用いる。   As the flexible wiring board 1 of the present embodiment, one having a glass transition temperature higher than the curing temperature of the resin 2 is used. Since the curing temperature of the resin 2 of this embodiment is 170 ° C.-190 ° C., a flexible wiring board having a glass transition temperature of 350 ° C. is used.

インターポーザー基板４上の半導体チップ３およびフレキシブル配線基板１は、樹脂２により被覆され、封止されている。   The semiconductor chip 3 and the flexible wiring board 1 on the interposer substrate 4 are covered with a resin 2 and sealed.

図３には、接合材料５、６の代わりに、異方性導電性フィルム（ＡＣＦ）２７と導電性接着剤２８を用いた場合の半導体装置の断面図が示されている。   FIG. 3 shows a cross-sectional view of a semiconductor device in which an anisotropic conductive film (ACF) 27 and a conductive adhesive 28 are used instead of the bonding materials 5 and 6.

本実施形態の半導体装置によれば、図６および図７に示された半導体装置において生じるような問題を克服した、信頼性の高い、薄型の半導体装置を実現することができる。   According to the semiconductor device of this embodiment, it is possible to realize a highly reliable and thin semiconductor device that overcomes the problems that occur in the semiconductor device shown in FIGS.

さらに、本実施形態のように半導体チップの一側面側（Ｙ１）から他側面側（Ｙ２）まで、フレキシブル配線基板が半導体チップの外表面に実質的に対応した形状で延在するので、半導体チップおよびフレキシブル配線基板上の電極のレイアウトに余裕ができ、設計の自由度が上がる。さらに、年々、薄くなっている半導体チップを外的な応力からフレキシブル配線基板により保護することもできる。   Furthermore, since the flexible wiring board extends in a shape substantially corresponding to the outer surface of the semiconductor chip from one side surface (Y1) to the other side surface (Y2) of the semiconductor chip as in this embodiment, the semiconductor chip In addition, the layout of the electrodes on the flexible wiring board can be afforded, and the degree of design freedom increases. Furthermore, a semiconductor chip that is becoming thinner year by year can be protected from external stress by a flexible wiring board.

さらに、本実施形態では、半導体チップとフレキシブル配線基板を同時に樹脂封止できるので、その製造過程を簡便化することもできる。   Furthermore, in this embodiment, since the semiconductor chip and the flexible wiring board can be sealed with resin simultaneously, the manufacturing process can be simplified.

図４には、本実施形態の半導体装置の製造工程が示される。   FIG. 4 shows a manufacturing process of the semiconductor device of this embodiment.

まず、テープ状のフレキシブル配線基板１と半導体チップ３を図４（ａ）に示すようにフリップ・チップ実装する。接合材料５は、はんだバンプまたは異方性導電性フィルム（ＡＣＦ）を用いる。また、テープ状のフレキシブル基板１と接合する半導体チップ３は、後述のように複数であってもかまわない。   First, the tape-like flexible wiring board 1 and the semiconductor chip 3 are flip-chip mounted as shown in FIG. As the bonding material 5, a solder bump or an anisotropic conductive film (ACF) is used. Moreover, the semiconductor chip 3 joined to the tape-shaped flexible substrate 1 may be plural as will be described later.

その後、図４（ｂ）に示すように金型３２を用いてフレキシブル配線基板１を半導体チップ３に沿った形にフォーミングし、テープ状のフレキシブル基板１の余分な部分を切り落とす。フレキシブル配線基板１は、金型３２内で１５０℃の熱と圧力を加えながら、曲げ加工が施される。これにより、フレキシブル配線基板３は半導体チップ３の外表面に実質的に対応した形状に加工される。ここで言う実質的に対応した形状とは、半導体チップに対して概してコンフォーマルな形状、すなわち、現実的に可能な範囲の加工形状を言うものである。   Thereafter, as shown in FIG. 4B, the flexible wiring board 1 is formed into a shape along the semiconductor chip 3 using a mold 32, and an excess portion of the tape-like flexible board 1 is cut off. The flexible wiring board 1 is bent while applying heat and pressure of 150 ° C. in the mold 32. Thereby, the flexible wiring board 3 is processed into a shape substantially corresponding to the outer surface of the semiconductor chip 3. The substantially corresponding shape mentioned here refers to a generally conformal shape with respect to the semiconductor chip, that is, a processing shape that is practically possible.

その後、図４（ｃ）に示すように、フレキシブル配線基板１上に、はんだバンプまたは導電性接着剤を形成し、半導体チップ３の裏面に接着剤７を塗布し、裏返してインターポーザー基板４にフレキシブル基板１を接合する。   Thereafter, as shown in FIG. 4 (c), solder bumps or conductive adhesive is formed on the flexible wiring substrate 1, the adhesive 7 is applied to the back surface of the semiconductor chip 3, and turned over to the interposer substrate 4. The flexible substrate 1 is joined.

その後、図４（ｄ）に示すようにインターポーザー基板４上の半導体チップ３およびフレキシブル配線基板１を樹脂２により被覆して、樹脂封止する。樹脂封止する工程においては、必要により真空脱法処理を併せて行ってもよい。   Thereafter, as shown in FIG. 4D, the semiconductor chip 3 and the flexible wiring board 1 on the interposer substrate 4 are covered with the resin 2 and sealed with resin. In the step of resin sealing, if necessary, vacuum detreatment may be performed.

このような製造方法によれば、信頼性の高い、薄型の半導体装置を少ない工程で製造することができる。すなわち、従来、発生していたようなワイヤーの変形、接触等の問題を考慮する必要がないので、樹脂封止に使用する溶融樹脂の粘性や注入スピードの調整が不要になる。また、半導体チップとフレキシブル基板、またはフレキシブル基板とインターポーザー基板との接続時に配線を一括して接続できる。   According to such a manufacturing method, a highly reliable and thin semiconductor device can be manufactured with a small number of steps. That is, since there is no need to consider problems such as wire deformation and contact that have occurred in the past, there is no need to adjust the viscosity of the molten resin used for resin sealing and the injection speed. Moreover, wiring can be connected collectively at the time of connection between a semiconductor chip and a flexible substrate or between a flexible substrate and an interposer substrate.

本実施形態の半導体装置の応用例を図５および図６を参照して以下に説明する。   An application example of the semiconductor device of the present embodiment will be described below with reference to FIGS.

図５（ａ）は上述の実施形態を２個の半導体チップより成るインバータ回路Ｉを備えた半導体装置に適用した例の断面図であり、図５（ｂ）はインバータ回路の等価回路図である。この応用例ではプリント配線基板４５を用いているが、本応用例ではこのプリント配線基板４５を前述のインタポーザー基板４と同等なものと見なして、前述の説明を参酌すする。   FIG. 5A is a cross-sectional view of an example in which the above-described embodiment is applied to a semiconductor device including an inverter circuit I composed of two semiconductor chips, and FIG. 5B is an equivalent circuit diagram of the inverter circuit. . In this application example, the printed wiring board 45 is used. In this application example, the printed wiring board 45 is regarded as equivalent to the above-described interposer board 4 and the above description is referred to.

インバータ回路Ｉは、出力ノードＮを介して直列に接続されたＭＯＳＦＥＴ４１とＭＯＳＦＥＴ４２を備えている。図５（ａ）、図５（ｂ）には、ＭＯＳＦＥＴ４１、４２のゲート、ソース面４３、ＭＯＳＦＥＴ４１、４２のドレーン面４４、ＭＯＳＦＥＴ４１のゲートに接続された制御線４７、ＭＯＳＦＥＴ４２のゲートに接続された制御線４８、ＭＯＳＦＥＴ４１のソース４９、ＭＯＳＦＥＴ４１のドレーン５０、ＭＯＳＦＥＴ４２のソース５１、ＭＯＳＦＥＴ４２のドレーン５２が示されている。ＭＯＳＦＥＴ４１のソース４９には、正側入力端子５３が接続され、出力ノードＮには出力端子５４が接続され、ＭＯＳＦＥＴ４２のドレーン５２には負側入力端子５５が接続されている。正側入力端子５３、出力端子５４、負側入力端子５５はプリント配線板４５上の導体層４６から外部へ引き出すことができる。   The inverter circuit I includes a MOSFET 41 and a MOSFET 42 connected in series via an output node N. 5A and 5B, the gates of the MOSFETs 41 and 42, the source surface 43, the drain surface 44 of the MOSFETs 41 and 42, the control line 47 connected to the gate of the MOSFET 41, and the gate of the MOSFET 42 are connected. A control line 48, a source 49 of the MOSFET 41, a drain 50 of the MOSFET 41, a source 51 of the MOSFET 42, and a drain 52 of the MOSFET 42 are shown. A positive input terminal 53 is connected to the source 49 of the MOSFET 41, an output terminal 54 is connected to the output node N, and a negative input terminal 55 is connected to the drain 52 of the MOSFET 42. The positive input terminal 53, the output terminal 54, and the negative input terminal 55 can be drawn out from the conductor layer 46 on the printed wiring board 45.

この応用例では、２つの導体チップの間の電極形成領域Ｚにも基板電極が形成することも可能であり、これに対応するフレキシブル配線基板の電極群も形成できる。また、この電極形成領域Ｚに出力ノードＮを配置することにより、配線の引き回しを短くすることもできる。   In this application example, a substrate electrode can also be formed in the electrode formation region Z between two conductor chips, and an electrode group of a flexible wiring board corresponding to this can be formed. Further, by arranging the output node N in the electrode formation region Z, the wiring routing can be shortened.

この応用例の半導体装置は、上述の製造方法の説明を参酌すれば、製造することができる。すなわち、図４（ａ）における半導体チップ３を２つの半導体チップに置き換えることにより、その製造方法を理解することができる。   The semiconductor device of this application example can be manufactured by referring to the above description of the manufacturing method. That is, the manufacturing method can be understood by replacing the semiconductor chip 3 in FIG. 4A with two semiconductor chips.

この応用例のような半導体装置をモータの制御に用いれば、小型化と耐ノイズ性と低ノイズ性を可能にしたモータを実現することができる。この場合、出力ノードＮまたは出力端子５４にモータの制御端子が接続される。   If a semiconductor device such as this application example is used for motor control, it is possible to realize a motor capable of miniaturization, noise resistance and low noise. In this case, the control terminal of the motor is connected to the output node N or the output terminal 54.

本発明の実施形態における半導体装置の側断面図Side sectional view of a semiconductor device in an embodiment of the present invention 本発明の実施形態における半導体装置の斜投影図An oblique projection of a semiconductor device according to an embodiment of the present invention 本発明の実施形態における半導体装置の側断面図Side sectional view of a semiconductor device in an embodiment of the present invention 本発明の実施形態における半導体装置の製造方法を示す工程図Process drawing which shows the manufacturing method of the semiconductor device in embodiment of this invention 本発明の応用例における半導体装置の断面図と等価回路図Sectional view and equivalent circuit diagram of semiconductor device in application example of the present invention 従来の半導体パッケージConventional semiconductor package 従来の半導体パッケージConventional semiconductor package

符号の説明Explanation of symbols

１ フレキシブル配線基板
２ 樹脂
３ 半導体チップ
４ インターポーザー基板
５ 接合材料
６ 接合材料
７ 接着剤
２５ フレキシブル基板と半導体チップ間の接続部
２６ フレキシブル基板とインターポーザー基板間の接続部
Ｘ 搭載領域
Ｙ１、Ｙ２、Ｚ 電極形成領域 DESCRIPTION OF SYMBOLS 1 Flexible wiring board 2 Resin 3 Semiconductor chip 4 Interposer board 5 Bonding material 6 Bonding material 7 Adhesive 25 Connection part 26 between flexible substrate and semiconductor chip Connection part X between flexible substrate and interposer board Mounting region Y1, Y2, Z electrode formation region

Claims (9)

複数の基板電極が形成された電極形成領域と、搭載領域と、前記複数の電極に接続された複数の配線とを備えた基板と、
複数のチップ電極が形成された主表面と、前記主表面と反対側の裏面とを有し、前記搭載領域に前記裏面を対向させて搭載された半導体チップと、
前記複数の基板電極に前記電極形成領域内で接続された第１電極群と、前記複数のチップ電極に前記主表面上で接続された第２電極群とを有し、少なくても前記電極形成領域上から前記主表面上まで延在した、可とう性材料より構成されたフレキシブル配線基板と、
前記半導体チップおよび前記フレキシブル配線基板を被覆する樹脂とを備えたことを特徴とする半導体装置。 A substrate including an electrode formation region in which a plurality of substrate electrodes are formed, a mounting region, and a plurality of wirings connected to the plurality of electrodes;
A semiconductor chip that has a main surface on which a plurality of chip electrodes are formed and a back surface opposite to the main surface, and is mounted with the back surface facing the mounting region;
A first electrode group connected to the plurality of substrate electrodes in the electrode formation region; and a second electrode group connected to the plurality of chip electrodes on the main surface. A flexible wiring board made of a flexible material extending from above the region to the main surface;
A semiconductor device comprising: a resin covering the semiconductor chip and the flexible wiring board. 前記電極形成領域は第１の領域および第２の領域からなり、前記搭載領域は前記第１の領域と前記第２の領域間に配置され、前記第１の領域には前記複数の基板電極の内の第１の電極が形成され、前記第２の領域には前記複数の基板電極の内の第２の電極が形成され、
前記フレキシブル配線基板は前記第１の領域から前記第２の領域まで前記主表面を介して延在すると共に、前記半導体チップの外表面に実質的に対応した形状に加工されたことを特徴とする請求項１記載の半導体装置。 The electrode formation region includes a first region and a second region, the mounting region is disposed between the first region and the second region, and the first region includes a plurality of substrate electrodes. A first electrode is formed, and a second electrode of the plurality of substrate electrodes is formed in the second region,
The flexible wiring board extends from the first region to the second region via the main surface and is processed into a shape substantially corresponding to the outer surface of the semiconductor chip. The semiconductor device according to claim 1. 前記半導体チップは第１の半導体チップおよび第２の半導体チップからなり、前記第１の半導体チップには第１のＭＯＳＦＥＴが形成され、前記第２の半導体チップには第２のＭＯＳＦＥＴが形成され、前記第１のＭＯＳＦＥＴと前記第２のＭＯＳＦＥＴとは出力ノードを介して直列接続されたインバータ回路を構成することを特徴とする請求項２記載の半導体装置。   The semiconductor chip comprises a first semiconductor chip and a second semiconductor chip, a first MOSFET is formed on the first semiconductor chip, and a second MOSFET is formed on the second semiconductor chip, 3. The semiconductor device according to claim 2, wherein the first MOSFET and the second MOSFET constitute an inverter circuit connected in series via an output node. 前記搭載領域は前記第１の半導体チップを搭載する第１の搭載領域と前記第２の半導体チップを搭載する第２の搭載領域とに分割され、前記第１の搭載領域と前記第２の搭載領域間には前記複数の基板電極の内の第３の電極が形成され、前記出力ノードは前記第３の電極に接続されたことを特徴とする請求項３記載の半導体装置。   The mounting area is divided into a first mounting area for mounting the first semiconductor chip and a second mounting area for mounting the second semiconductor chip, and the first mounting area and the second mounting area. 4. The semiconductor device according to claim 3, wherein a third electrode of the plurality of substrate electrodes is formed between the regions, and the output node is connected to the third electrode. 請求項３または４記載の半導体装置における前記出力ノードが接続された制御端子を有するモータ。   5. A motor having a control terminal to which the output node is connected in the semiconductor device according to claim 3. 半導体チップを可とう性材料より構成されたフレキシブル配線基板上に実装し、前記半導体チップ上に形成された電極と前記フレキシブル配線基板上に形成された電極とを接続する工程と、
前記半導体チップおよび前記フレキシブル配線基板を金型内に挿入し、前記フレキシブル配線基板を前記半導体チップの外表面に実質的に対応した形状に加工する工程と、
前記加工する工程の後、前記半導体チップの前記電極が形成された表面とは反対側の裏面および前記フレキシブル配線基板の端部を基板上に接合する工程と、
前記基板上の前記半導体チップおよび前記フレキシブル配線基板を樹脂により被覆する工程とを備えたことを特徴とする半導体装置の製造方法。 Mounting a semiconductor chip on a flexible wiring board made of a flexible material, and connecting the electrode formed on the semiconductor chip and the electrode formed on the flexible wiring board;
Inserting the semiconductor chip and the flexible wiring board into a mold, and processing the flexible wiring board into a shape substantially corresponding to the outer surface of the semiconductor chip;
After the step of processing, a step of bonding the back surface of the semiconductor chip opposite to the surface on which the electrode is formed and the end of the flexible wiring substrate on the substrate;
And a step of covering the semiconductor chip and the flexible wiring board on the substrate with a resin. 前記フレキシブル配線基板を構成する可とう性材料は、前記樹脂の硬化温度より高いガラス転移温度を有することを特徴とする請求項６記載の半導体装置の製造方法。   The method for manufacturing a semiconductor device according to claim 6, wherein the flexible material constituting the flexible wiring board has a glass transition temperature higher than a curing temperature of the resin. 前記フレキシブル配線基板の端部を前記基板上に接合することにより、前記フレキシブル配線基板上に形成された電極と前記基板上に形成された電極とが電気的に接続されることを特徴とする請求項６または７記載の半導体装置の製造方法。   The electrode formed on the flexible wiring substrate and the electrode formed on the substrate are electrically connected by bonding an end of the flexible wiring substrate onto the substrate. Item 8. A method for manufacturing a semiconductor device according to Item 6 or 7. 請求項１乃至４記載の半導体装置を備えたモータの制御装置。   A motor control device comprising the semiconductor device according to claim 1.
JP2008153628A 2008-06-12 2008-06-12 Semiconductor device and method of manufacturing the same Pending JP2009302216A (en)

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