JP2009302198A - Semiconductor chip, semiconductor chip group, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a chip for simplifying the structures of a circuit and a wiring around an integrated circuit and miniaturizing the chip body. <P>SOLUTION: This semiconductor chip 1 includes a plate-like chip body 3 having a substantially rectangular planar shape a plurality of integrated circuits 5a, 5b provided on the surface of the chip body 3, wirings 13a to 13f provided on the rear face of the chip body 3 as other circuits, and contacts 11a, 11b as connecting means for connecting the integrated circuits 5a, 5b with the wirings 13a to 13f. The contacts 11a, 11b are conductive substances provided penetrating the chip body 3. Thus, by providing a wiring for connecting the integrated circuits 5a, 5b to each other on the rear face 2b of the chip body 3, the structures of other circuits (wiring) around the integrated circuits are more simplified than in the case where the wiring is provided on the surface 2a. In other words, the semiconductor 1 is more miniaturized than that in the related art. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor chip, a semiconductor chip group, and a semiconductor device having these.

  In recent years, along with miniaturization and high performance of electronic devices, there is a demand for miniaturization of semiconductor chips used in electronic devices.

  On the other hand, the miniaturization has been conventionally achieved by the high integration of the integrated circuit by the progress of the process technology.

  On the other hand, there is also known a method of not only reducing the size by high integration but also increasing the area of the integrated circuit by increasing the number of places where the integrated circuit is formed in the chip, thereby reducing the size of the chip.

  For example, FIG. 1 of Patent Document 1 discloses a structure in which integrated circuits are formed on both front and back surfaces of a semiconductor chip (Patent Document 1).

  There is also known a method of increasing an area where an integrated circuit can be formed by providing a wiring part on a side surface of a semiconductor chip (Patent Document 2).

JP-A-11-297873 JP 2001-223293 A

  However, even if the high integration or the area of the integrated circuit is increased, it is difficult to reduce the size of the surrounding wiring and circuit. Therefore, in the above technology, the increase in the number of surrounding circuits and wiring and the complexity of the routing of the wiring lead to a semiconductor chip (chip The miniaturization of the main body was insufficient.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a chip capable of simplifying the circuit and wiring structure around the integrated circuit and reducing the size of the chip body. is there.

  In order to achieve the above-described object, the first invention provides a chip body having a front surface and a back surface, an integrated circuit provided on the surface of the chip body, and a back surface of the chip body. And another circuit connected to the semiconductor chip.

  A second invention is a semiconductor chip group formed by electrically connecting a plurality of semiconductor chips according to the first invention.

  A third invention is a semiconductor device comprising the semiconductor chip according to the first invention.

  A fourth invention is a semiconductor device comprising the semiconductor chip group described in the second invention.

  The fifth invention includes a step (a) of providing an integrated circuit on the surface of a chip body having a front surface and a back surface, a step (b) of providing another circuit on the back surface of the chip body, the integrated circuit, And a step (c) of connecting to another circuit.

  A sixth invention is a method of manufacturing a semiconductor chip group, comprising a step of electrically connecting a plurality of semiconductor chips according to the first invention.

  According to the present invention, it is possible to provide a chip capable of simplifying the structure of the circuit and wiring around the integrated circuit and reducing the size of the chip body.

  That is, it is possible to provide a chip having a size that can sufficiently utilize the miniaturization process technology.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

  First, a schematic configuration of the semiconductor chip 1 according to the first embodiment of the present invention will be described with reference to FIGS.

  As shown in FIGS. 1 to 3, the semiconductor chip 1 has a plate-like chip body 3 having a substantially square planar shape and having a front surface 2 a and a back surface 2 b, and a plurality of integrated circuits provided on the front surface 2 a of the chip body 3. 5a, 5b, 5c, 5d, wirings 13a-13f as other circuits provided on the back surface 2b of the chip body 3, and connection means for connecting the integrated circuits 5a, 5b, 5c, 5d and the wirings 13a-13f Contacts 7a, 7b, 7c, 7d, 9a, 9b, 9c, 9d, 11a, 11b, 11c, and 11d.

  Specifically, the chip body 3 is made of a material such as silicon or germanium, and the integrated circuits 5a to 5d are logic circuits such as a microprocessor, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), or the like. Is a memory circuit.

  The contacts 7a, 7b, 7c, 7d, 9a, 9b, 9c, 9d, 11a, 11b, 11c, and 11d are conductive materials provided through the inside of the chip body 3 (specifically, contacts) Reference numerals 7a, 9a, and 11a are connected to the integrated circuit 5a, and contacts 7b, 9b, and 11c are connected to the integrated circuit 5b.

  On the other hand, the contacts 7c, 9c, and 11c are connected to the integrated circuit 5c, and the contacts 7d, 9d, and 11d are connected to the integrated circuit 5d.

  The wirings 13a to 13f are wirings for connecting the integrated circuits 5a, 5b, 5c, and 5d to each other through the above-described contacts.

  Specifically, the wiring 13a connects the integrated circuits 5a and 5c via the contacts 7a and 7c, and the wiring 13b connects the integrated circuits 5a and 5b via the contacts 9a and 9b.

  Similarly, the wiring 13c connects the integrated circuits 5a and 5d via the contacts 11a and 11d, and the wiring 13d connects the integrated circuits 5b and 5d via the contacts 7b and 7d.

  Further, the wiring 13e connects the integrated circuits 5b and 5c via contacts 11b and 11c, and the wiring 13f connects the integrated circuits 5c and 5d via contacts 9c and 9d.

  Thus, by providing the wiring for connecting the integrated circuits 5a, 5b, 5c, and 5d on the back surface 2b of the chip body 3, the wiring around the integrated circuit can be compared with the case where the wiring is provided on the front surface 2a. The structure of another circuit (wiring) can be simplified.

  That is, when the wiring is provided in the semiconductor chip 1, the space on the back surface 2b can be fully utilized, so that it is possible to route the wiring with only one layer without using a plurality of layers of wiring.

  In addition, since no other circuit area on the surface 2a is required, the chip body 3 can be made smaller than before.

  That is, the semiconductor chip 1 can be made smaller than before.

  Further, by effectively utilizing the space on the back surface 2b of the chip body 3, the characteristics of the semiconductor chip 1 can be improved, and the cost of the semiconductor chip 1 can be reduced.

  Next, a method for manufacturing the semiconductor chip 1 will be briefly described.

  The process of manufacturing the semiconductor chip 1 includes the following processes.

  (A) A step of forming the integrated circuits 5a to 5d on the surface 2a of the chip body 3 as in the prior art.

  (B) A step of providing wiring as another circuit on the back surface 2 b of the chip body 3.

  (C) A step of providing a contact on the chip body 3.

  In addition, the order of these processes is not specifically limited.

  The contact is formed by, for example, injecting a conductive material into the through hole after providing the through hole in the chip body 3. However, the conductive material is directly injected into the chip body 3 without providing the through hole. May be formed.

  Next, the structure of the semiconductor device 15 (semiconductor package) using the semiconductor chip 1 will be briefly described.

  The semiconductor chip 1 according to the first embodiment can be incorporated into various semiconductor packages, and is not particularly limited to the structure of the incorporated semiconductor package.

  Here, with reference to FIG. 4 and FIG. 5, the case where the semiconductor chip 1 is incorporated in an SOP package (Small Outline Package) and a BGA (Ball Grid Array) package will be briefly described.

  As shown in FIG. 4, when the semiconductor chip 1 is incorporated in the semiconductor device 15 that is an SOP package, the chip body 3 is provided with a pad 17, and the pad 17 is connected to a signal terminal 21a such as a lead via bonding wires 19a and 19b. Connect to 21b.

  Thereafter, the periphery of the signal terminals 21 a and 21 b except for the tips thereof is sealed with the package resin 23, thereby forming the semiconductor device 15.

  On the other hand, as shown in FIG. 5, when the semiconductor chip 1 is incorporated in the semiconductor device 15 which is a BGA package, a pad 17 is provided on the chip body 3, and the pad 17 is connected to the package substrate 25 via bonding wires 19a and 19b. To do.

  The bonding wires 19a and 19b are electrically connected to balls 27 such as solder balls provided on the back side of the package substrate 25 through internal wiring (not shown) in the package substrate 25.

  Thereafter, the periphery of the semiconductor chip 1 and the bonding wire 19a is sealed with the package resin 23, whereby the semiconductor device 15a is formed.

  As described above, according to the first embodiment, the semiconductor chip 1 is provided on the chip body 3, the plurality of integrated circuits 5 a, 5 b, 5 c, 5 d provided on the surface of the chip body 3, and the back surface of the chip body 3. The integrated circuits 5a to 5d and the wirings 13a to 13f are connected to each other through contacts provided through the chip body 3.

  Therefore, the structure of other circuits (wirings) around the integrated circuit can be simplified as compared with the case where the wiring is provided on the surface 2a.

  That is, when the wiring is provided in the semiconductor chip 1, the space on the back surface 2b can be fully utilized, so that it is possible to route the wiring with only one layer without using a plurality of layers of wiring.

  In addition, since no other circuit area on the surface 2a is required, the chip body 3 can be made smaller than before.

  That is, the semiconductor chip 1 can be made smaller than before.

  Further, by effectively utilizing the space on the back surface 2b of the chip body 3, the characteristics of the semiconductor chip 1 can be improved, and the cost of the semiconductor chip 1 can be reduced.

  Next, a semiconductor chip 1a according to the second embodiment will be described with reference to FIG.

  In the semiconductor chip 1a according to the second embodiment, the power supply wiring 31 and the GND wiring 33 are routed in a zigzag (meander structure) as other circuits in the semiconductor chip 1 according to the first embodiment.

In the second embodiment, elements having the same functions as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 6, the semiconductor chip 1a has a power supply wiring 31 and a GND wiring 33 on the back surface 2b.

  The power supply wiring 31 is connected to the integrated circuits 5a, 5b, 5c, and 5d through contacts 33a, 33b, 33c, and 33d.

  The GND wiring 33 is connected to the integrated circuits 5a, 5b, 5c, and 5d through contacts 35a, 35b, 35c, and 35d.

  Here, as is clear from FIG. 6, the power supply wiring 31 and the GND wiring 33 are routed so as to have a planar shape combined in a zigzag manner.

  By adopting such a shape, sufficient routing between the power supply wiring 31 and the GND wiring 33 can be ensured, and noise interference can be reduced as compared with the conventional case.

  Note that the manufacturing method of the semiconductor chip 1a and the structure and method of incorporating the semiconductor chip 1a into the package are the same as those in the first embodiment, and thus the description thereof is omitted.

  Thus, according to the second embodiment, the semiconductor chip 1a is formed on the chip body 3, the plurality of integrated circuits 5a, 5b, 5c, 5d provided on the front surface 2a of the chip body 3, and the back surface 2b of the chip body 3. The power supply wiring 31 and the GND wiring 33 are provided, and the power supply wiring 31 and the GND wiring 33 are connected to the integrated circuits 5a, 5b, 5c, and 5d through contacts provided through the chip body 3. ing.

  Accordingly, the same effects as those of the first embodiment are obtained.

  According to the second embodiment, the power supply wiring 31 and the GND wiring 33 have a planar shape combined in a zigzag manner.

  For this reason, it is possible to sufficiently ensure the routing of the power supply wiring 31 and the GND wiring 33, and noise interference can be mitigated as compared with the conventional case.

  Next, a semiconductor chip 1b according to a third embodiment will be described with reference to FIG.

  The wiring board 1b according to the third embodiment is obtained by routing the power supply wiring 31 and the GND wiring 33 in a ring shape in the second embodiment.

  Note that in the third embodiment, elements that perform the same functions as those in the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 7, in the semiconductor chip 1 b, the power supply wiring 31 has an annular shape in plan view, and the GND wiring 33 is formed in an annular shape (planar shape) inside the power supply wiring 31.

  By adopting such a shape, sufficient routing between the power supply wiring 31 and the GND wiring 33 can be ensured, and noise interference can be reduced as compared with the conventional case.

  Note that the manufacturing method of the semiconductor chip 1b and the structure and method of incorporating the semiconductor chip 1b into the package are the same as those in the first embodiment, and thus description thereof is omitted.

  Thus, according to the third embodiment, the semiconductor chip 1b is provided on the chip body 3, the plurality of integrated circuits 5a, 5b, 5c, 5d provided on the front surface 2a of the chip body 3, and the back surface 2b of the chip body 3. The power supply wiring 31 and the GND wiring 33 are provided, and the power supply wiring 31 and the GND wiring 33 are connected to the integrated circuits 5a, 5b, 5c, and 5d through contacts provided through the chip body 3. ing.

  Accordingly, the same effects as those of the second embodiment are obtained.

  Next, a semiconductor chip 1c according to the fourth embodiment will be described with reference to FIG.

  The semiconductor chip 1c according to the fourth embodiment is the same as the semiconductor chip 1 according to the first embodiment except that the power supply wiring 31 and the GND wiring 33 are provided as other circuits, and the storage capacitor portion 37 is provided on the back surface 2b. It is.

  In the fourth embodiment, elements having the same functions as those in the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 6, the semiconductor chip 1c has a power supply wiring 31 and a GND wiring 33 in the vicinity of the outer periphery of the back surface 2b.

  Further, the semiconductor chip 1 c has a storage capacitor portion 37 so as to be surrounded by the power supply wiring 31 and the GND wiring 33.

  The storage capacitor portion 37 is connected to the integrated circuits 5a, 5b, 5c, and 5d by contacts 39a, 39b, 39c, and 39d provided through the semiconductor chip 1c.

  Here, the integrated circuits 5a, 5b, 5c, and 5d are not supplied from the outside, such as step-down or step-up potentials or substrate potentials, and the potentials generated in the integrated circuits 5a, 5b, 5c, and 5d themselves are A storage capacitor for storing the potential is required.

  When such a storage capacitor portion is provided on the surface 2a of the semiconductor chip 1c, it hinders the miniaturization of the semiconductor chip 1c.

  However, since the storage capacitor portion 37 is provided on the back surface 2b in the semiconductor chip 1c, it is possible to reduce the chip size while ensuring a sufficient size of the storage capacitor portion 37.

  Note that the manufacturing method of the semiconductor chip 1c and the structure and method of incorporating the semiconductor chip 1c into the package are the same as those in the first embodiment, and thus the description thereof is omitted.

  Thus, according to the fourth embodiment, the semiconductor chip 1c is formed on the chip body 3, the plurality of integrated circuits 5a, 5b, 5c, 5d provided on the surface 2a of the chip body 3, and the back surface 2b of the chip body 3. The power supply wiring 31 and the GND wiring 33 are provided, and the power supply wiring 31 and the GND wiring 33 are connected to the integrated circuits 5a, 5b, 5c, and 5d through contacts provided through the chip body 3. ing.

  Accordingly, the same effects as those of the first embodiment are obtained.

  Further, according to the fourth embodiment, in the semiconductor chip 1c, the storage capacitor portion 37 is provided on the back surface 2b.

  Therefore, it is possible to reduce the chip size of the semiconductor chip 1c while ensuring a sufficient size of the storage capacitor portion 37.

  Next, a semiconductor chip 1d according to a fifth embodiment will be described with reference to FIG.

  A semiconductor chip 1d according to the fifth embodiment is provided with a power diffusion layer capacitor 41 and a GND wiring capacitor 45 on the back surface 2b.

  Note that in the fifth embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 9, the semiconductor chip 1d has a power diffusion layer capacitor 41 and a GND wiring capacitor 45 on the back surface 2b.

  The power diffusion layer capacitor 41 and the GND wiring capacitor 45 are respectively connected to the integrated circuits 5a to 5d through contacts 43a, 43b, 43c, 43d and contacts 47a, 47b, 47c, 47d provided through the chip body 3. It is connected.

  The power source diffusion layer capacitor 41 and the GND wiring capacitor 45 are formed by using the power source and GND as capacitors, respectively. In FIG. 9, the power source is configured as a diffusion layer, and GND is configured as a wiring. A capacitor is formed between the wirings.

  The same effect can be obtained by configuring GND as a diffusion layer to form a GND diffusion layer capacitor, and configuring a power source as wiring to form a power supply wiring capacitor.

  In addition, the conventional semiconductor device has a structure in which the power supply and GND are connected with an external capacitor and noise interference is reduced as a bypass capacitor. However, the same effect can be produced.

  Note that the manufacturing method of the semiconductor chip 1d and the structure and method of incorporating the semiconductor chip 1d into the package are the same as those in the first embodiment, and thus the description thereof is omitted.

  As described above, according to the fifth embodiment, the semiconductor chip 1d is formed on the chip body 3, the plurality of integrated circuits 5a, 5b, 5c, and 5d provided on the surface 2a of the chip body 3, and the back surface 2b of the chip body 3. The power supply diffusion layer capacitor 41 and the GND wiring capacitor 45 are provided, and the power diffusion layer capacitor 41 and the GND wiring capacitor 45 and the integrated circuits 5a, 5b, 5c, and 5d penetrate the chip body 3. Are connected through contacts provided.

  Accordingly, the same effects as those of the first embodiment are obtained.

  In addition, according to the fifth embodiment, the semiconductor chip 1 d has the power diffusion layer capacitor 41 and the GND wiring capacitor 45 provided on the back surface 2 b of the chip body 3.

  For this reason, it is possible to achieve both downsizing and enhancement of power supply and GND as compared with the conventional semiconductor chip.

  Next, a semiconductor chip 1e according to a sixth embodiment will be described with reference to FIGS.

  In the semiconductor chip 1e according to the sixth embodiment, the input protection circuit 79 is provided in front of the input first stage circuit 81 of the integrated circuits 5a and 5b (between the pad 17 and the input first stage circuit 81) in the first embodiment. Is.

  Note that in the sixth embodiment, elements that perform the same functions as in the first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted.

  First, an outline of the input protection circuit 79 will be described with reference to a circuit diagram shown in FIG.

  As shown in FIG. 10, the integrated circuits 5 a and 5 b have an input first stage circuit 81.

  The input first stage circuit 81 forms a CMOS (Complementary Metal Oxide Semiconductor) inverter circuit in which a PMOS (Positive channel Metal Oxide Semiconductor) 81a and an NMOS (Negative Channel Metal Oxide Semiconductor) 81b are combined between a power source 71 and a GND 73.

  When an input signal to the integrated circuits 5a and 5b is input from the pad 17, it is applied to the gate of the CMOS inverter circuit, and the input first stage circuit 81 becomes an inverted signal and is input into the integrated circuits 5a and 5b.

  In such a case, if a high potential due to static electricity or the like is applied to the input first stage circuit 81, the CMOS inverter circuit may be destroyed, and the integrated circuits 5a and 5b may not operate normally.

  Therefore, the semiconductor chip 1e is provided with the input protection circuit 79 before the input first stage circuit 81, that is, between the pad 17 and the input first stage circuit 81.

  The input protection circuit 79 includes a first diode 75 provided in the forward direction (direction toward the power supply 71) between the pad 17 (contact 61 b) and the power supply wiring 31, and between the pad 17 (contact 61 b) and the GND wiring 33. The second diode 77 is provided in the forward direction.

  With such a configuration, when a high potential is applied to the input protection circuit 79, a current flows to the GND 73 side due to the avalanche phenomenon, so that the input first stage circuit 81 can be protected.

  Note that the avalanche phenomenon is a phenomenon in which a reverse current rapidly increases when a high potential reverse bias voltage is applied to a diode and the potential becomes a certain level or more.

  In FIG. 10, the internal structure of the integrated circuits 5a and 5b is not shown, but it is understood that when the applied voltage is not high, the input signal is directly input to the gate of the input first stage circuit 81. It should be possible.

  Next, a specific structure of the semiconductor chip 1e having the input protection circuit 79 will be described with reference to FIGS.

  As shown in FIGS. 11 to 13, on the back surface 2b of the semiconductor chip 1a, an elongated P-type semiconductor layer 51 (first P-type semiconductor layer) and an N-type semiconductor layer 53 ( A first N-type semiconductor layer) is formed.

  The P-type semiconductor layer 51 and the N-type semiconductor layer 53 are configured to be connectable to the power supply 71 and the GND 73, respectively. The P-type semiconductor layer 51 and the N-type semiconductor layer 53 are connected to the power supply wiring 31 and the GND wiring 33, respectively. Has been.

  The power supply wiring 31 and the GND wiring 33 are connected to the integrated circuits 5a and 5b by contacts 63c and 65c.

  An N-type semiconductor layer 55 (second N-type semiconductor layer) having a rectangular planar shape is provided on the surface of the P-type semiconductor layer 51, and a P-type semiconductor layer having a rectangular planar shape on the surface of the N-type semiconductor layer 53. 57 (second P-type semiconductor layer) is provided.

  In FIG. 11, the N-type semiconductor layer 55 and the P-type semiconductor layer 57 are staggered with respect to each other.

  The N-type semiconductor layer 55 and the P-type semiconductor layer 57 are connected by a back signal wiring 59 and are electrically connected to each other by contacts 61 c and 61 a of the back signal wiring 59.

  Further, a contact 61b is provided between the connection portions of the back surface signal wiring 59 with the N-type semiconductor layer 55 and the P-type semiconductor layer 57 (between the contacts 61c and 61a), and the contact 61b penetrates the chip body 3. It is connected to the pad 17.

  With such a structure, a plurality of P-type semiconductor layers 51 and N-type semiconductor layers 55 are formed in the forward direction (direction toward the power supply 71) between the pad 17 (contact 61 b) and the power supply 71 (power supply wiring 31). A first diode 75 is provided.

  On the other hand, a plurality of second diodes 77 each including an N-type semiconductor layer 53 and a P-type semiconductor layer 57 are provided between the pad 17 (contact 61b) and the GND 73 (GND wiring 33) in the forward direction.

  The number and shape of the diodes are not limited to those shown in FIGS. 11 to 13, and an input protection circuit using MOS or bipolar or an input protection circuit using clamp MOS or parasitic MOS instead of the diode. It is also possible to configure.

  Note that the manufacturing method of the semiconductor chip 1e and the structure and method of incorporating the semiconductor chip 1e into the package are the same as those in the first embodiment, and thus the description thereof is omitted.

  Thus, according to the sixth embodiment, the semiconductor chip 1e is provided with the chip body 3, and the plurality of integrated circuits 5a and 5b provided on the front surface 2a of the chip body 3, and the power supply wiring provided on the back surface 2b of the chip body 3 31 and a GND wiring 33, and the power supply wiring 31 and the GND wiring 33 are connected to the integrated circuits 5a and 5b through contacts provided through the chip body 3.

  Accordingly, the same effects as those of the first embodiment are obtained.

  Further, according to the sixth embodiment, the semiconductor chip 1e is provided between the pad 17 and the power supply wiring 31 in the forward direction (direction toward the power supply 71), and between the pad 17 and the GND wiring 33. An input protection circuit 79 having a second diode 77 provided in the forward direction therebetween is provided.

  Therefore, the input first stage circuit 81 can be protected when a high potential is applied to the semiconductor chip 1.

  Next, a semiconductor chip 1f according to a seventh embodiment will be described with reference to FIG.

  The semiconductor chip 1f according to the seventh embodiment is obtained by connecting two chip bodies with wiring 93 on the back surface 2b in the first embodiment.

  Note that in the seventh embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 14, the semiconductor chip 1 f has a plurality of chip main bodies 3, and the plurality of chip main bodies 3 are respectively connected via wirings 93 provided on the back surface 2 b and contacts 91 a provided penetrating the chip main body 3. Are connected to each other.

  In general, when a semiconductor chip is formed on a wafer 4 in a diffusion process, a plurality of chip bodies 3 are formed on the wafer 4 and then cut one by one to form a semiconductor chip.

  Here, a memory product or the like is mounted on a substrate in order to increase the memory capacity like a module.

  In some cases, a plurality of the same semiconductor chips are stacked and assembled into one.

  On the other hand, the semiconductor chip 1f has a configuration in which the chip body 3 is cut from the wafer 4 by two chips and connected by the back surface 2b.

  With such a configuration, when the semiconductor chip 1f is a memory, it can be formed as a memory having a double capacity.

  FIG. 14 discloses a structure in which the chip body 3 is cut by two chips. However, if there are a plurality of chips, there is no need to limit to two chips. For example, the chip body 3 is cut every three chips or every four chips. It is good also as a structure.

  Since the structure and method for incorporating the semiconductor chip 1f into the package are the same as those in the first embodiment, description thereof is omitted.

  As described above, according to the seventh embodiment, the semiconductor chip 1f includes the plurality of chip bodies 3, and the plurality of chip bodies 3 are provided through the wirings 93 and the chip body 3 provided on the back surface 2b. They are connected to each other through contacts 91a.

  Accordingly, the same effects as those of the first embodiment are obtained.

  Further, according to the seventh embodiment, the semiconductor chip 1f is configured such that the chip body 3 is cut by two chips and connected on the back surface.

  Therefore, when the semiconductor chip 1f is a memory, it can be formed as a memory having a double capacity.

  Next, an eighth embodiment will be described with reference to FIG.

  A semiconductor chip 1g according to the eighth embodiment is obtained by connecting two chip bodies 3 and 3a having different dimensions with a wiring 93a on the back surface 2b in the seventh embodiment.

  Note that, in the eighth embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 15, the semiconductor chip 1g has two chip bodies 3 and 3a having different dimensions, and the two chip bodies 3 and 3a having different dimensions have wirings 93a and chip bodies 3 provided on the back surface 2b, respectively. They are connected to each other through contacts 91a provided therethrough.

  Thus, in the present invention, chip bodies having different dimensions can be coupled. For example, if the chip body 3a is formed as a memory chip and the chip body 3 is formed as a memory controller for controlling the memory, the semiconductor chip 1g alone Can produce a completed memory product.

  Further, the above structure is not limited to the memory. For example, if the chip body 3a is formed as a CPU (Central Processing Unit) and the chip body 3 is formed as a peripheral data control chip for controlling the memory or the like, similarly. A completed control unit can be manufactured.

  As described above, according to the eighth embodiment, the semiconductor chip 1g includes the two chip bodies 3 and 3a having different dimensions, and the two chip bodies 3 and 3a having different dimensions are provided on the back surface 2b. And they are connected to each other through a contact 91a provided through the chip body 3.

  Accordingly, the same effects as those of the seventh embodiment are obtained.

  Further, according to the eighth embodiment, the semiconductor chip 1g has the two chip bodies 3, 3a having different dimensions.

  Therefore, a semiconductor chip 1g alone can be manufactured as a memory product or a control unit.

  Next, a ninth embodiment will be described with reference to FIGS.

  In the ninth embodiment, the back surfaces of the semiconductor chips 1a according to the first embodiment are joined together to form a semiconductor chip group 1.

  Note that in the ninth embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 16, the semiconductor chip group 101 is configured by routing wiring in consideration of mirror inversion of the back surface 2 b of the semiconductor chip 1 and connecting two back surfaces (wirings) of the semiconductor chip 1 to each other. Yes.

  Note that an insulating film 95 is provided in a region other than the region where the wiring is provided on the back surface 2b of the semiconductor chip 1 for safety (to prevent a short circuit between the wirings).

  In this way, by connecting the backside wirings of the semiconductor chip 1, a semiconductor chip group 101 in which a plurality of chips are integrated can be configured.

  Here, the structure of the semiconductor devices 15b and 15c (semiconductor package) using the semiconductor chip group 101 will be briefly described.

  The semiconductor chip group 101 can be incorporated into various packages similarly to the semiconductor chip 1, and is not particularly limited to the structure of the package to be incorporated.

  Here, with reference to FIG. 17 and FIG. 18, a case where the semiconductor chip group 101 is incorporated in an SOP package (Small Outline Package) and a BGA (Ball Grid Array) package will be briefly described.

  As shown in FIG. 17, when the semiconductor chip group 101 is incorporated in the semiconductor device 15 which is an SOP package, the pads 17 are provided on the individual semiconductor chips 1, and the pads 17 are connected to the signals such as leads via bonding wires 19a and 19b. Connect to terminals 103a and 103b.

  Thereafter, the periphery of the signal terminals 103a and 103b except for the tips thereof is sealed with the package resin 23, whereby the semiconductor device 15b is formed.

  On the other hand, as shown in FIG. 18, when the semiconductor chip group 101 is incorporated in the semiconductor device 15 which is a BGA package, the pads 17 are provided on the individual semiconductor chips 1 and the pads 17 are connected to the package substrate via bonding wires 19a and 19b. 25.

  The bonding wires 19a and 19b are electrically connected to balls 27 provided on the back side of the package substrate 25 through internal wiring (not shown) in the package substrate 25.

  Thereafter, the periphery of the semiconductor chip 1 and the bonding wire 19a is sealed with the package resin 23, whereby the semiconductor device 15c is formed.

  As described above, according to the ninth embodiment, the semiconductor chip group 101 is configured by connecting the backside wirings of the semiconductor chip 1 together.

  Accordingly, the same effects as those of the first embodiment can be obtained.

  Next, a tenth embodiment will be described with reference to FIGS.

  In the tenth embodiment, a plurality of semiconductor chips 1 according to the first embodiment are used and bonded by shifting the planar positions of the back surfaces to form a semiconductor chip group 101b.

  Note that in the tenth embodiment, elements performing the same functions as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 19, the semiconductor chip group 101 b is configured by routing wiring in consideration of mirror inversion of the back surface 2 b of the semiconductor chip 1 and connecting back surfaces (wirings) of the plurality of semiconductor chips 1. However, the planar positions of the semiconductor chips 1 are shifted and connected in a direction parallel to one side of the chip body 3.

  By connecting in this way, the projected area of the plane can be reduced as compared with the case where the semiconductor chips are arranged side by side.

  Here, the structure of the semiconductor devices 15d and 15e (semiconductor package) using the semiconductor chip group 101b will be briefly described.

  The semiconductor chip group 101b can be incorporated into various packages similarly to the semiconductor chip 1, and is not particularly limited to the structure of the package to be incorporated.

  Here, a case where the semiconductor chip group 101b is incorporated in an SOP package (Small Outline Package) and a BGA (Ball Grid Array) package will be briefly described with reference to FIGS.

  As shown in FIG. 20, when the semiconductor chip group 101b is incorporated in the semiconductor device 15 which is an SOP package, the pads 17 are provided on the individual semiconductor chips 1, and the pads 17 are connected to the signals such as leads via bonding wires 19a and 19b. The terminals 113a, 113b, 115a, and 115b are connected.

  Thereafter, the periphery of the signal terminals 113a and 113b except for the tips thereof is sealed with the package resin 23, whereby the semiconductor device 15d is formed.

  On the other hand, as shown in FIG. 21, when the semiconductor chip group 101 is incorporated in the semiconductor device 15e which is a BGA package, the pads 17 are provided on the individual semiconductor chips 1, and the pads 17 are packaged via bonding wires 19a, 19b and the like. Connect to substrate 25.

  The bonding wires 19a and 19b are electrically connected to balls 27 provided on the back side of the package substrate 25 through internal wiring (not shown) in the package substrate 25.

  Thereafter, the periphery of the semiconductor chip 1 and the bonding wires 19a and 19b is sealed with the package resin 23, whereby the semiconductor device 15e is formed.

  Thus, according to the tenth embodiment, the semiconductor chip group 101b is configured by connecting the backside wirings of the semiconductor chip 1a.

  Accordingly, the same effects as those of the ninth embodiment are obtained.

  Further, according to the tenth embodiment, the semiconductor chip group 101b is configured such that a plurality of semiconductor chips 1 can be connected to one semiconductor chip 1 by shifting the connection portions of the semiconductor chips 1 and connecting them. .

  Therefore, the projected area of the plane can be reduced as compared with the case where the semiconductor chips are arranged directly beside.

  Next, an eleventh embodiment will be described with reference to FIGS.

  In the eleventh embodiment, a plurality of semiconductor chips 1 according to the first embodiment are used, the plane positions of one front surface and one back surface are shifted and connected one by one to form a semiconductor chip group 101c. .

  Note that, in the eleventh embodiment, elements that perform the same functions as in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 22, the semiconductor chip group 101c is configured to use a plurality of semiconductor chips 1 and to connect one by one while shifting the planar positions of one front surface and one back surface.

  When connected in this way, as shown in FIG. 22, the semiconductor chip 1 can be disposed obliquely, and the height of the semiconductor chip group 101c can be reduced.

  Furthermore, as shown in FIG. 22, since the semiconductor chip group 101c only needs to provide the pads 17 only on the semiconductor chip 1 at the extreme end, it can be easily incorporated into the semiconductor package.

  Here, the structure of the semiconductor devices 15f and 15g (semiconductor package) using the semiconductor chip group 101c will be briefly described.

  The semiconductor chip group 101c can be incorporated into various packages like the semiconductor chip 1, and is not particularly limited to the structure of the package to be incorporated.

  Here, with reference to FIGS. 23 to 25, a case where the semiconductor chip group 101 c is mounted on a module substrate and a semiconductor chip group 101 c is incorporated into a BGA (Ball Grid Array) package will be briefly described.

  As shown in FIG. 23, when the semiconductor chip group 101c is incorporated on the module substrate, the pads 17 are provided on the individual semiconductor chips 1 and connected to the package substrate 25 via the bonding wires 19a.

  As shown in FIGS. 23 and 24, the package substrate 25 is provided with a signal terminal 117, which is connected to the signal terminal 117 via an internal wiring (not shown).

  Thereafter, the periphery of the semiconductor chip group 101c is sealed with the package resin 23, whereby the semiconductor device 15f is formed.

  On the other hand, as shown in FIG. 25, when the semiconductor chip group 101 is incorporated in the semiconductor device 15g which is a BGA package, the pads 17 are provided on the individual semiconductor chips 1, and the pads 17 are packaged via bonding wires 19a and 19b. Connect to substrate 25.

  The bonding wires 19a and 19b are electrically connected to balls 27 provided on the back side of the package substrate 25 through internal wiring (not shown) in the package substrate 25.

  Thereafter, the periphery of the semiconductor chip 1 and the bonding wire 19a is sealed with the package resin 23, whereby the semiconductor device 15g is formed.

  Thus, according to the eleventh embodiment, the semiconductor chip group 101 c is configured by connecting a plurality of semiconductor chips 1.

  Accordingly, the same effects as those of the ninth embodiment are obtained.

  In addition, according to the eleventh embodiment, a plurality of semiconductor chips 1 are used, and one front surface and one back surface are shifted and connected one by one.

  Therefore, the semiconductor chip 1 can be disposed obliquely, and the height of the semiconductor chip group 101c can be reduced.

  Furthermore, according to the eleventh embodiment, since the semiconductor chip group 101c only needs to provide the pads 17 only on the semiconductor chip 1 at the extreme end, it is easier to incorporate in the semiconductor package than in the ninth embodiment. is there.

  In the above-described embodiment, the case where the present invention is applied to an SOP type or BGA type package has been described. However, the present invention is not limited to this and can be applied to other package structures. .

1 is a plan view of a semiconductor chip 1 according to a first embodiment. It is AA sectional drawing of FIG. 2 is a rear view of the semiconductor chip 1. FIG. 1 is a cross-sectional view showing a semiconductor device 15 in which a semiconductor chip 1 is incorporated. It is sectional drawing which shows the semiconductor device 15a incorporating the semiconductor chip 1. FIG. It is a reverse view of the semiconductor chip 1a. It is a reverse view of the semiconductor chip 1b. It is a reverse view of the semiconductor chip 1c. It is a reverse view of the semiconductor chip 1d. It is a circuit diagram of semiconductor chip 1e. It is a reverse view of the semiconductor chip 1e. FIG. 12 is an enlarged view of the vicinity of a back signal wiring 59 in FIG. 11. It is BB sectional drawing of FIG. It is a reverse view of the semiconductor chip 1f. It is a reverse view of the semiconductor chip 1g. 2 is a cross-sectional view showing a semiconductor chip group 101. FIG. It is sectional drawing which shows the semiconductor device 15b incorporating the semiconductor chip group 101. FIG. It is sectional drawing which shows the semiconductor device 15c incorporating the semiconductor chip group 101. FIG. It is sectional drawing which shows the semiconductor chip group 101b. It is sectional drawing which shows the semiconductor device 15d incorporating the semiconductor chip group 101b. It is sectional drawing which shows the semiconductor device 15e incorporating the semiconductor chip group 101b. It is sectional drawing which shows the semiconductor chip group 101c. It is sectional drawing which shows the semiconductor device 15f incorporating the semiconductor chip group 101c. It is a C direction arrow directional view of FIG. It is sectional drawing which shows the semiconductor device 15g incorporating the semiconductor chip group 101c.

Explanation of symbols

1 ………… Semiconductor chip 3 ………… Chip body 5a ………… Integrated circuit 7a ……… Contact 9a ……… Contact 11a …… Contact 13a …… Wiring 15 ……… Semiconductor device 17 ……… Pad 19a …… Bonding wire 21a …… Signal terminal 23 ……… Package resin 25 ……… Package substrate 27 ……… Ball 31 ……… Power supply wiring 33 ……… GND wiring 35a …… Contact 37 ……… Storage capacitor 39a …… Contact 41 ... …… Power diffusion layer capacitor 43a …… Contact 45 ……… GND wiring capacitor 47a …… Contact 71 ……… Power source 73 ……… GND
75... First diode 77 ... Second diode 79 ... Input protection circuit 81 ... Input first stage circuit 101 ... Semiconductor chip group

Claims (38)

A chip body having a front surface and a back surface;
An integrated circuit provided on the surface of the chip body;
Another circuit provided on the back surface of the chip body and connected to the integrated circuit;
A semiconductor chip comprising:   2. The semiconductor chip according to claim 1, wherein the integrated circuit and the other circuit are connected to each other by connection means provided through the chip body. A plurality of the integrated circuits are provided,
The other circuit has wiring,
The semiconductor chip according to claim 2, wherein the plurality of integrated circuits are electrically connected to each other by the wiring of the other circuit on the back surface of the chip body.   4. The semiconductor chip according to claim 3, wherein the wiring includes a power supply wiring and a GND wiring.   5. The semiconductor chip according to claim 4, wherein the power supply wiring and the GND wiring are routed in a zigzag manner.   5. The semiconductor chip according to claim 4, wherein the power supply wiring and the GND wiring are routed in a ring shape.   3. The semiconductor chip according to claim 2, wherein the other circuit has a storage capacitor portion. The other circuit is:
3. The semiconductor chip according to claim 2, further comprising any one of a power supply diffusion layer capacitor and a GND wiring capacitor, or a power supply wiring capacitor and a GND diffusion layer capacitor.   5. The semiconductor chip according to claim 4, wherein the other circuit includes an input protection circuit. The input protection circuit is
A pad provided on the chip body and electrically connectable to the outside;
A first diode connected in a forward direction between the pad and the power supply wiring;
A second diode connected in a forward direction between the pad and the GND wiring;
10. The semiconductor chip according to claim 9, further comprising: The input protection circuit is
A first P-type semiconductor layer connected to the power supply wiring;
A first N-type semiconductor layer connected to the GND wiring;
A second N-type semiconductor layer provided on the surface of the first P-type semiconductor layer;
A second P-type semiconductor layer provided on the surface of the first N-type semiconductor layer;
Provided to connect the second N-type semiconductor layer and the second P-type semiconductor layer, and between the connection portions of the second N-type semiconductor layer and the second P-type semiconductor layer; Signal wiring to which the pads are connected;
11. The semiconductor chip according to claim 10, further comprising: The connecting means includes
A hole provided through the chip, a conductive material provided in the hole,
The semiconductor chip according to claim 2, further comprising: The connecting means includes
3. The semiconductor chip according to claim 2, further comprising a conductive material injected so as to penetrate the chip. A plurality of the chip bodies are provided,
The other circuit has wiring,
3. The semiconductor chip according to claim 2, wherein the integrated circuits of the plurality of chip bodies are connected by the wiring of the other circuit.   A semiconductor chip group comprising a plurality of the semiconductor chips according to any one of claims 1 to 13 electrically connected thereto.   The semiconductor chip according to claim 15, comprising two semiconductor chips according to claim 1, wherein the back surfaces of the two semiconductor chips are electrically connected to each other. group. A plurality of the semiconductor chips according to any one of claims 1 to 13,
The plurality of semiconductor chips are:
16. The semiconductor chip group according to claim 15, wherein the back surfaces are electrically connected in a state in which the positions on the plane are shifted from each other. A plurality of the semiconductor chips according to any one of claims 1 to 13,
The plurality of semiconductor chips are:
16. The semiconductor chip group according to claim 15, wherein the front surface and the back surface are electrically connected to other semiconductor chips one by one in a state where the positions on the plane are shifted from each other.   A semiconductor device comprising the semiconductor chip according to claim 1.   A semiconductor device comprising the semiconductor chip group according to claim 15. Providing an integrated circuit on the surface of the chip body having a front surface and a back surface;
Providing another circuit on the back surface of the chip body (b);
Connecting the integrated circuit and the other circuit (c);
A method for manufacturing a semiconductor chip, comprising: The step (c)
22. The method of manufacturing a semiconductor chip according to claim 21, wherein the integrated circuit and the other circuit are connected by a connecting means provided through the chip body. The step (a) is a step of providing a plurality of the integrated circuits,
The step (c)
23. The method of manufacturing a semiconductor chip according to claim 22, wherein the plurality of integrated circuits are electrically connected to each other by the other circuit on the back surface of the chip body. The step (b)
23. The method of manufacturing a semiconductor chip according to claim 22, wherein the other circuit is a step of routing a power supply wiring and a GND wiring. The step (b)
25. The method of manufacturing a semiconductor chip according to claim 24, wherein the other circuit is a step of drawing a power supply wiring and a GND wiring in a zigzag manner. The step (b)
25. The method of manufacturing a semiconductor chip according to claim 24, wherein the other circuit is a step of drawing a power supply wiring and a GND wiring in a ring shape.   23. The method of manufacturing a semiconductor chip according to claim 22, wherein the step (b) is a step of providing a storage capacitor section as the other circuit.   23. The method of manufacturing a semiconductor chip according to claim 22, wherein the step (b) includes a step of providing a power diffusion layer capacitor and a GND diffusion layer capacitor as the other circuit.   The method of manufacturing a semiconductor chip according to claim 22, wherein the step (b) includes a step of providing an input protection circuit as the other circuit. The step of providing the input protection circuit includes:
Providing a pad on the chip body;
Providing a first diode in a forward direction between the pad and the power supply wiring;
Providing a second diode in a forward direction between the pad and the GND wiring;
30. The method of manufacturing a semiconductor chip according to claim 29, comprising: The step of providing the input protection circuit includes:
Providing a first P-type semiconductor layer and connecting to the power supply wiring;
Providing a first N-type semiconductor layer and connecting to the GND wiring;
Providing a second N-type semiconductor layer on the surface of the first P-type semiconductor layer;
Providing a second P-type semiconductor layer on the surface of the first N-type semiconductor layer;
The second N-type semiconductor layer and the second P-type semiconductor layer are connected by a signal wiring, and a connection portion of the signal wiring with the second N-type semiconductor layer and the second P-type semiconductor layer is connected. Connecting the pad in between,
31. The method of manufacturing a semiconductor chip according to claim 30, further comprising: The step (c)
23. The method of manufacturing a semiconductor chip according to claim 22, further comprising the step of providing connection means having a hole provided through the chip and a conductive material provided in the hole. The step (c)
23. The method of manufacturing a semiconductor chip according to claim 22, further comprising a step of providing a connection means by injecting a conductive material so as to penetrate the chip.   23. The method of manufacturing a semiconductor chip according to claim 22, wherein the step (c) is a step of connecting the integrated circuits of the plurality of chip bodies by the wirings and / or other circuits.   A method of manufacturing a semiconductor chip group, comprising a step of electrically connecting a plurality of semiconductor chips according to claim 1.   36. The method of manufacturing a semiconductor chip group according to claim 35, further comprising a step of electrically connecting the back surfaces of two of the semiconductor chips according to any one of claims 1 to 13.   The semiconductor chip according to claim 36, further comprising a step of electrically connecting a plurality of the semiconductor chips according to any one of claims 1 to 13 by shifting the positions of the back surfaces from each other on a plane. Group manufacturing method.   A step of electrically connecting a plurality of the semiconductor chips according to any one of claims 1 to 13 one by one by shifting a position on a plane between the front surface and the back surface. 36. A method of manufacturing a semiconductor chip group according to item 35.

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