JP2009301678A - Semiconductor memory device, display device, electronic equipment, and manufacturing method of semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device having high reliability of information reading, a display device having such semiconductor memory device, an electronic equipment, and a manufacturing method of such a semiconductor memory device. <P>SOLUTION: A plurality of nonvolatile memory elements of which the polarities are same and a reading part are formed on an insulating substrate. the reading part has a reading circuit and a load resistance element. Structure of the load resistance element is made same as structure of the nonvolatile memory element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, a display device, an electronic apparatus, and a method for manufacturing the semiconductor memory device. In particular, the present invention relates to a semiconductor memory device in which memory cells each including a field effect transistor having a memory portion having a function of holding electric charge are arranged. The present invention also relates to a display device and an electronic device including the semiconductor memory device, and a method for manufacturing the semiconductor memory device for manufacturing the semiconductor memory device.

  Conventional non-volatile semiconductor memory devices include those described in US Pat. No. 5,444,656 (Patent Document 1).

  FIG. 10 is a diagram showing a nonvolatile memory element array which is the nonvolatile semiconductor device.

  This non-volatile memory element array includes non-volatile memory elements 71ma1, 71ma2, 71mb1, 71mb2, a reference element 71r, select transistors 72ma, 72mb, 72r, drain bias circuits 73ma, 73mb, 73r, load resistance elements 74m, 74r and a sense amplifier 76.

  In this nonvolatile memory element array, a nonvolatile memory element to be read is selected according to an input address signal.

  For example, when the nonvolatile memory element 71ma2 is selected by an input address signal, the read current passes through the selection transistor 72ma and the drain bias circuit 73ma. A voltage on the input side of the load resistance element 74m based on the current passing through the drain bias circuit 73ma and the load resistance element 74m is input to the sense amplifier 76.

  On the other hand, the read current also passes through the selection transistor 72r and the drain bias circuit 73r in the reference element 71r set to an intermediate state between the program state and the erase state of the nonvolatile memory element. A voltage on the input side of the load resistance element 74r based on the current passing through the drain bias circuit 73r and the load resistance element 74r is input to the sense amplifier 76. In the sense amplifier 76, two input voltages are compared, and information stored in the nonvolatile memory element 71ma2 is read out.

  Incidentally, in recent years, in a display device such as a liquid crystal display, improvement in manufacturing yield and homogenization of quality by suppressing variation between manufacturing have become major issues.

As a countermeasure, there is a method in which a nonvolatile memory element is formed on a substrate on which a display device is formed, and various parameters for correcting variations are stored in the nonvolatile memory element in a test before shipping the display device.
US Pat. No. 5,444,656

  Most of the substrates used in the display device are insulating substrates having a much lower heat-resistant temperature than a single crystal silicon substrate, so that it is difficult to obtain a high-quality thin film on the substrate by high-temperature film formation.

  For this reason, the element formed on the insulating substrate has a very large characteristic variation between the elements compared to the element formed on the single crystal silicon substrate.

  Therefore, when the circuit formed on the single crystal silicon substrate is formed on the insulating substrate as it is, the resistance variation of the load resistance element and the circuit operation characteristic of the sense amplifier vary due to the characteristic variation between the elements.

  For this reason, the non-volatile memory element formed on the insulating substrate has a high possibility that information is erroneously read even when information is stored in a predetermined state.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device with high reliability of information reading, a display device and an electronic device having such a semiconductor memory device, and a method for manufacturing such a semiconductor memory device. It is in.

In order to solve the above problems, a semiconductor memory device according to the present invention provides:
A plurality of non-volatile memory elements formed on an insulating substrate and having the same polarity;
A reading unit for reading information stored in the nonvolatile memory element,
The reading unit includes the same memory function-containing element having a nonvolatile memory function having the same structure as that of the nonvolatile memory element.

  In addition, the said same structure means that structures other than polarity are the same.

  According to the present invention, since the reading unit includes the same memory function-containing element having a non-volatile memory function having the same structure as the non-volatile memory element, in order to accurately read information from the non-volatile memory element The characteristics of the reading unit can be easily adjusted. In other words, information in the nonvolatile memory element can be read easily. Therefore, the probability of erroneous reading due to characteristic variation can be greatly reduced, the reliability during the reading operation can be increased, and a highly reliable semiconductor memory device can be provided.

In one embodiment,
The polarity of the same memory function-containing element is opposite to the polarity of the nonvolatile memory element.

  According to the embodiment, since the polarity of the same memory function-containing element is opposite to the polarity of the nonvolatile memory element, it is possible to perform a reliable read operation at a low voltage. A highly reliable semiconductor memory device can be provided.

In one embodiment,
The reading unit is a reading circuit having a plurality of thin film transistor elements.

According to the above embodiment,
According to the above embodiment, by adjusting the element characteristics of the same memory function-containing element of the readout circuit formed on the insulating substrate, it is possible to improve the reliability during the readout operation, and the highly reliable semiconductor A storage device can be provided.

In one embodiment,
The readout section is a readout circuit having a plurality of thin film transistor elements,
The readout circuit has at least two of the same memory function-containing elements,
One of the two identical memory function-containing elements and the other of the two identical memory function-containing elements have opposite polarities.

  According to the embodiment, when the same memory function-containing element plays a role of comparing the most important current in the element constituting the reading unit formed on the insulating substrate, a pair of two identical elements By adjusting the difference in the characteristics of the memory function-containing elements, it is possible to greatly improve the reliability during the read operation, and it is possible to provide a highly reliable semiconductor memory device.

In one embodiment,
The plurality of nonvolatile memory elements include a first nonvolatile memory element and a second nonvolatile memory element,
Each of the first nonvolatile memory element and the second nonvolatile memory element can take a first state or a second state,
When storing the first information, the first nonvolatile memory element is set to the first state, while the second nonvolatile memory element is set to the second state.
When storing the second information, the first nonvolatile memory element is set to the second state, while the second nonvolatile memory element is set to the first state.
By simultaneously referring to the first nonvolatile memory element and the second nonvolatile memory element, it is read whether the first information is written or the second information is written.

  According to the above embodiment, information can be stored and read accurately.

In one embodiment,
The same memory function-containing element is a load resistance element.

  According to the above embodiment, since the same memory function-containing element is a load resistance element, the characteristics of the reading unit can be adjusted easily and quickly, and the information stored in the nonvolatile memory can be read accurately. be able to.

The display device of the present invention is
The semiconductor memory device of the present invention is provided.

  Here, for example, there is a liquid crystal display device as the display device.

  According to the present invention, in the display device, the reliability of the semiconductor memory device can be increased, the manufacturing yield can be increased, and the reliability of the device can be improved.

The electronic device of the present invention is
The semiconductor memory device of the present invention is provided.

  Here, the electronic device refers to, for example, a portable information terminal such as a cellular phone, a portable audio device, a portable video device, a DVD, and a television.

  According to the present invention, the reliability of the semiconductor memory device can be increased, the manufacturing yield can be increased, and the reliability of the device can be increased.

Also, a method for manufacturing a semiconductor memory device of the present invention includes
A plurality of nonvolatile memory elements formed on an insulating substrate and having the same polarity, and a reading unit for reading information stored in the nonvolatile memory element, wherein the reading unit includes the nonvolatile memory element Including one or more load resistance elements having a nonvolatile memory function of the same structure as the volatile memory element, each of the nonvolatile memory element and the load resistance element being a thin film transistor;
The threshold voltage of the load resistance element is varied by injecting electric charge into the load resistance element.

  According to the present invention, since the threshold voltage of the load resistance element is set to a predetermined voltage by injecting charges into the load resistance element, this step also facilitates the characteristics of the reading unit. The information of the nonvolatile memory element can be read accurately.

Also, a method for manufacturing a semiconductor memory device of the present invention includes
A plurality of nonvolatile memory elements formed on an insulating substrate and having the same polarity, and a readout circuit for reading out information stored in the nonvolatile memory element, the readout circuit including the nonvolatile memory element A semiconductor memory device having a nonvolatile memory function having the same structure as that of the volatile memory element and having a first thin film transistor and a second thin film transistor connected symmetrically in the readout circuit;
When the current flowing through the first node in the readout circuit is a predetermined current, a voltage applied to the first thin film transistor and a second symmetrically positioned at the first node in the readout circuit When the current flowing through the node is the predetermined current, the first thin film transistor or the second thin film transistor is charged so that the difference from the voltage applied to the second thin film transistor is equal to or lower than the predetermined voltage. It is characterized by injecting.

  According to the present invention, by using the memory functions of the first thin film transistor and the second thin film transistor arranged symmetrically with each other, the circuit characteristics of the readout circuit can be easily adjusted so that the readout is accurate.

  According to the present invention, it is possible to easily adjust the reading characteristics of the reading unit, and to accurately read information.

  According to one embodiment, the information stored in the non-volatile memory element is read by setting the load resistance element formed in the same structure as the non-volatile memory element to a predetermined range of characteristics. The characteristics of the read section can be corrected, the reliability during the read operation can be improved, and a highly reliable semiconductor memory device can be provided.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a circuit diagram showing a semiconductor memory device according to the first embodiment of the present invention.

  This semiconductor memory device is formed on an insulating substrate. This semiconductor memory device includes a plurality of nonvolatile memory elements 11ma1, 11ma2, 11mb1, 11mb2, a reference memory element 11r, selection transistors 12ma, 12mb, a selection transistor 12r, and a load resistance element 14m as an element having the same memory function. 14r and a sense amplifier 16.

  The reference memory element 11r, the selection transistors 12ma and 12mb, the selection transistor 12r, the load resistance elements 14m and 14r as the same memory function-containing elements, and the sense amplifier 16 constitute a reading unit.

  As shown in FIG. 1, the plurality of nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb2 are arranged in a matrix. Although not described in detail, each of the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb2 is selected by an address signal controlled by a switching element or the like.

  FIG. 2 is a sectional view of the load resistance elements 14m and 14r, and FIG. 3 is a circuit symbol of the load resistance elements 14m and 14r.

  The load resistance elements 14m and 14r are N-type TFTs (thin film transistors). As shown in FIG. 2, the load resistance elements 14m and 14r include a gate electrode 41n, N-type source / drain regions 42na and 42nb, and a gate having a three-layer structure of silicon oxide 44na, silicon oxide 44nc and silicon nitride 44nb. The semiconductor layer 45n includes an insulating film 43n and a semiconductor layer 45n, and the semiconductor layer 45n is formed of non-single crystal silicon in which a channel region is formed.

  4 is a cross-sectional view of the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb, and FIG. 5 is a circuit symbol of the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb.

  The nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11m are P-type TFTs. The nonvolatile memory elements 11 ma 1, 11 ma 2, 11 mb 1, 11 m include a gate having a three-layer structure of a gate electrode 41 p, N-type source / drain regions 42 pa, 42 pb, silicon oxide 44 pa, silicon nitride 44 pb, and silicon oxide 44 pc. The semiconductor layer 45 includes an insulating film 43p and a semiconductor layer 45, and the semiconductor layer 45 is formed of non-single crystal silicon in which a channel region is formed.

  The load resistance elements 14m and 14r and the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb have the same structure, but have polarities opposite to each other.

  In this semiconductor device, information stored in each of the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb is read as follows.

  First, as a first step, a circuit characteristic for reading information stored in a nonvolatile memory element formed on an insulating substrate is tested, and the circuit characteristic is corrected if necessary.

  The circuit characteristics are tested as follows, for example.

  Referring to FIG. 1, first, the nonvolatile memory elements 11ma1, 11ma2, 11mb1, 11mb2, the reference memory element 11r and the selection transistor are all turned off, while the selection transistors 12ma and 12r are turned on.

  Next, in this state, a current equal to the bit lines 18m1 and 18r is supplied, for example, the voltage applied to the gate electrode of the load resistance element 14r is fixed, and the voltage applied to the 14m gate electrode is swept. . Then, by monitoring the data output from the sense amplifier 17 in each state, the voltage when the data output value is inverted is detected.

  As a result of detecting the inversion voltage, a voltage difference between the voltage applied to the gate electrode of the load resistance element 14r and the voltage applied to the gate electrode of the load resistance element 14m when the data output value is inverted is determined in advance. If the voltage is larger than the applied voltage, the charge resistance is weakly injected into the load resistance element 14m or the load resistance element 14r having a nonvolatile memory function (an example of electron injection will be described below. May be injected).

  In this way, by adjusting the characteristics of the load resistance element 14m or the load resistance element 14r, the voltage applied to the gate electrode of the load resistance element 14r and the voltage applied to the gate electrode of the load resistance element 14m. The difference is adjusted so as to be within a predetermined voltage range.

  For example, when electrons are injected into the load resistance element 14m, a voltage of about 15V is applied to the gate electrode of the load resistance element 14m and a voltage of about 10V is applied to the bit line 18m1. By applying about 100 milliseconds, hot electrons are generated, and the hot electrons are injected into the load resistance element 14m, that is, the storage area of the nonvolatile memory element.

  When electrons are injected into the load resistance element 14r, hot electrons are generated by applying a voltage of about 15V to the gate electrode of the load resistance element 14r and a voltage of about 10V to the bit line 18r for about 100 milliseconds, The hot electrons are injected into the load resistance element 14r, that is, the storage area of the nonvolatile memory element.

  In this way, when the circuit characteristics are not in a predetermined range, charge injection is performed on both or one of the load resistance elements 14m and 14r as necessary, and the circuit characteristics are Adjust within the predetermined circuit characteristic range.

  Further, by injecting charges into the reference element, the state of the reference element is set to an intermediate state between a predetermined program state and an erase state.

  Next, as a second step, information is stored in the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb2.

  Thereafter, as a third step, a nonvolatile memory element is selected according to the address signal, and information stored in each of the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb2 is read.

  For example, when the nonvolatile memory element 11ma2 is selected by the selection signal, the read current passes through the selection transistor 12ma. A voltage on the input side of the load resistance element 14m based on the current passing through the selection transistor 12ma and the load resistance element 14m is input to the sense amplifier 16.

  On the other hand, the read current also passes through the selection transistor 12r in the reference element 11r set to an intermediate state between the program state and the erase state of the nonvolatile memory element. A voltage on the input side of the load resistance element 14r based on the current passing through the selection transistor 12r and the load resistance element 14r is input to the sense amplifier 16.

  Thereafter, the sense amplifier 16 compares the two input voltages, and the information stored in the nonvolatile memory element 11ma2 is read out.

  In the first embodiment, N-type TFTs are used as the load resistance elements 14r and 14m, and P-type TFTs are used as the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb2. Conversely, P-type TFTs are used as the load resistance elements. An N-type TFT may be used as the TFT and the nonvolatile memory element. Further, a P-type TFT may be used for both the load resistance element and the nonvolatile memory element, and an N-type TFT may be used for both the load resistance element and the nonvolatile memory element.

  Further, the charge injection into the load resistance elements 14m and 14r is not necessarily performed if the circuit characteristics are in a predetermined range.

  In general, a memory portion of a nonvolatile memory element formed on an insulating substrate has a high defect density and a high operating voltage. Therefore, the threshold voltage shift due to rewriting is a nonvolatile memory formed on single crystal silicon. Larger than that of sex memory.

  Therefore, in consideration of the worst case of the window width of the threshold voltage due to rewriting, if it is determined that erroneous reading is not performed by the tested reading circuit, charge injection to the load resistance elements 14m and 14r is necessarily performed. There is no need.

  In the above embodiment, the load resistance elements shown in FIG. 2 are used as the load resistance elements 14m and 14r, and the nonvolatile memory elements shown in FIG. 3 are used as the nonvolatile memory elements 11ma1, 11ma2, 11mb1, and 11mb2. In the present invention, a nonvolatile memory device having another structure may be used as the load resistance element and the nonvolatile memory device. For example, in FIGS. 2 and 3, the gate insulating film having a function of holding electric charge has a three-layer structure of silicon oxide, silicon nitride, and silicon oxide, but other materials may be used. In short, any element having a function of a nonvolatile memory by injecting electric charge may be used.

(Second Embodiment)
FIG. 6 is a circuit diagram of a semiconductor memory device according to the second embodiment of the present invention.

  This semiconductor memory device is also formed on an insulating substrate like the semiconductor memory device of the first embodiment.

  This semiconductor memory device includes a nonvolatile memory element 211, TFTs 213 and 214 having a nonvolatile memory function, TFTs 212, 221 to 225, 231 to 235, and a buffer circuit 26.

  The circuit characteristics of the semiconductor memory device of the second embodiment are tested as follows.

  First, as a first step, the TFTs 231 to 235 are turned off, the TFTs 221 to 225 are turned on, the TFT 213 is connected to the terminals 243, 252 and 253, and the TFT 214 is connected to the terminals 244, 254 and 255. Each device characteristic is tested by supplying a voltage to each.

  Specifically, in the case of the TFT 213, the threshold voltage of the TFT element 213 is detected by applying a voltage from the terminals 243, 252, and 253.

  For example, when detecting the threshold voltage of the TFT element 213, the voltage applied from the terminal 253 is swept while the voltage applied from the terminal 243 and the terminal 252 is fixed, and the current flowing through the terminal 252 is measured. The voltage applied to the terminal 253 when the current value previously given is defined as the threshold voltage of the TFT element 213.

  In the case of the TFT element 214, the voltage applied from the terminal 254 is swept while the voltage applied from the terminal 244 and the terminal 255 is fixed, the voltage flowing through the terminal 255 is measured, and the current given in advance is measured. When the value is exceeded, the voltage applied to the terminal 254 is defined as the threshold voltage of the TFT element 214.

  When the voltage difference between the threshold voltage of the TFT element 213 obtained in this way and the threshold voltage of the TFT element 214 is larger than a predetermined voltage, the TFT having the nonvolatile memory function By performing weak charge injection into the element 213 or the TFT element 214 (an example of electron injection will be described below, holes may be injected instead of electron injection), and adjusting the characteristics of the load resistance element, Adjustment is made so that the voltage difference between the threshold voltage of the TFT element 213 and the threshold voltage of the TFT element 214 falls within a predetermined voltage range.

  The TFT elements 213 and 214 have a nonvolatile memory function having the same structure as that of the nonvolatile memory element 211. The TFT elements 213 and 214 constitute the same memory function-containing element. Further, in the semiconductor memory device shown in FIG. 6, the portions other than the nonvolatile memory element 211 constitute a reading circuit.

  As for the electron injection into the TFT element, when electron injection into the TFT element 213 is performed, for example, a voltage of about 15 V is applied to the terminal 253 and a voltage of about 10 V to the terminal 252 is applied for about 100 milliseconds with the terminal 243 grounded. Thus, hot electrons are generated, and the hot electrons are injected into the storage area of the TFT element 213 having a nonvolatile memory function.

  When electrons are injected into the TFT element 214, for example, by applying a voltage of about 15 V to the terminal 255 and about 10 V to the terminal 254 for about 100 milliseconds with the terminal 244 grounded, hot electrons are generated, The hot electrons are injected into the storage area of the TFT element 214 having a nonvolatile memory function.

  In this way, when the element characteristics of the TFT elements 213 and 214 are not in a predetermined range, charge injection is performed and adjustment is made within the predetermined characteristic range.

  Next, as a second step, with respect to the TFTs 231 to 235 and the TFTs 221 to 225, voltages are applied to the gate electrode, the terminal 241 and the terminal 251 of the nonvolatile memory element 211 while maintaining the state of step 1. Information is stored in the nonvolatile memory element 211.

  Thereafter, as a third step, the TFTs 231 to 235 are turned on, while the TFTs 221 to 225 are turned off, the voltage corresponding to the read high level is applied to the terminals 241 and 242 and the read low level is applied to the terminals 243 and 244. Information stored in the nonvolatile memory element 211 is read from the output terminal 27 by applying a corresponding voltage.

  The TFT elements 213 and 214 play an important role when reading information stored in the nonvolatile memory element 211. If the element characteristics vary, the risk of erroneous reading increases.

  In this embodiment, the device characteristics of the TFT elements 213 and 214 are tested, and when the element characteristics are not in a predetermined range, charge is injected into the TFT element 213 or the TFT element 214 (note that In the invention, electrification injection may be performed on both the TFT element 213 or the TFT element 214), and since the adjustment is made within a predetermined circuit characteristic range, the establishment of erroneous reading due to variations in element characteristics is greatly increased. The reliability of the semiconductor memory device can be improved.

(Third embodiment)
FIG. 7 is a circuit diagram showing a semiconductor memory device according to the third embodiment of the present invention.

  This semiconductor memory device is formed on an insulating substrate. This semiconductor memory device includes nonvolatile memory elements 311 and 312, TFTs 313 and 314 having a nonvolatile memory function, TFTs 321 to 326 and 331 to 334, and a buffer circuit 36.

  First, as the first step, the TFTs 331 to 334 are turned off, while the TFTs 321 to 326 are turned on, the TFT 313 is connected to the terminals 343, 352, and 353, and the TFT 314 is connected to the terminals 344, 354, and 356, respectively. The device characteristics are tested by supplying a voltage.

  Specifically, first, the threshold voltage of the TFT element 313 is detected by applying a voltage from the terminal 343, the terminal 352, and the terminal 353, and the TFT element 314 is detected by applying a voltage from the terminal 344, the terminal 354, and the terminal 356. The threshold voltage of is detected.

  For example, when detecting the threshold voltage of the TFT element 313, the voltage applied from the terminal 353 is swept while the voltage applied from the terminal 343 and the terminal 352 is fixed, and the voltage flowing to the terminal 352 is measured. The voltage applied to the terminal 353 when the current value previously given is defined as the threshold voltage of the TFT element 313.

  Similarly, the voltage applied from the terminal 354 is swept while the voltage applied from the terminal 344 and the terminal 356 is fixed, the voltage flowing through the terminal 356 is measured, and when the current value exceeds a predetermined value, the terminal 354 A voltage applied to the TFT element 314 is defined as a threshold voltage.

  When the voltage difference between the threshold voltage of the TFT element 313 obtained in this way and the threshold voltage of the TFT element 314 is larger than a predetermined voltage, a nonvolatile memory function is provided. Element characteristics of the element in which electron injection is performed by weakly injecting charges into the TFT element 313 or the TFT element 314 (an example of electron injection will be described below, but holes may be injected instead of electron injection). Is adjusted so that the voltage difference between the threshold voltage of the TFT element 313 and the threshold voltage of the TFT element 314 falls within a predetermined voltage range.

  The TFT elements 313 and 314 have the same nonvolatile memory function as the nonvolatile memory element 313. The TFT elements 313 and 314 constitute the same memory function-containing element. In the semiconductor memory device illustrated in FIG. 7, a portion other than the volatile memory element 311 and the nonvolatile memory element 312 constitutes a reading circuit.

  As for electron injection into the TFT element, for example, when electrons are injected into the TFT element 313, a voltage of about 15 V is applied to the terminal 353 and about 10 V to the terminal 352 for about 100 milliseconds with the terminal 343 grounded. Thus, hot electrons may be generated and injected into the storage area of the TFT element 313 having a nonvolatile memory function.

  In addition, when electrons are injected into the TFT element 314, hot electrons are generated by applying a voltage of about 15 V to the terminal 354 and about 10 V to the terminal 356 for about 100 milliseconds with the terminal 344 grounded. Hot electrons are injected into the storage area of the TFT element 314 having a nonvolatile memory function.

  Next, as a second step, the TFTs 331 to 335 and the TFTs 321 to 326 are maintained in the state of step 1 and the nonvolatile memory element 313 is connected to the gate electrode, the terminal 341 and the terminal 351 with the nonvolatile memory element. As for 313, information is stored in the nonvolatile memory element 311 and the nonvolatile memory element 312 by applying voltages to the gate electrode, the terminal 342, and the terminal 355, respectively.

  At this time, for example, when it is desired to store information “0” in the semiconductor memory device, the nonvolatile memory element 311 is set in the program state and the nonvolatile memory element 312 is set in the erased state. When the information “1” is to be stored, the nonvolatile memory element 311 is in the erased state and the nonvolatile memory element 312 is in the programmed state.

  After that, as a third step, the TFTs 331 to 334 are turned on, while the TFTs 321 to 226 are turned off, the voltage corresponding to the read High level is applied to the terminals 341 and 342, and the readout Low is applied to the terminals 343 and 344. The stored information is read out from the output terminal 37 by applying a voltage corresponding to the level.

  The TFT elements 313 and 314 play an important role in reading information stored in the nonvolatile memory elements 311 and 312. If the characteristics of the elements vary, the risk of erroneous reading increases.

  According to this embodiment, the device characteristics of the TFTs 313 and 314 are tested in advance, and when the device characteristics are not in a predetermined range, charge injection is performed and adjusted within the predetermined circuit characteristics. Therefore, the probability of erroneous reading due to variations in element characteristics can be greatly reduced, and the reliability of the semiconductor memory device can be improved.

  In the second embodiment and the third embodiment, the element having the structure shown in FIG. 4 can be used as the element having the nonvolatile memory function, and an element having another structure can be used.

  A P-type TFT as a non-volatile memory element may constitute part of a circuit for reading information stored in the non-volatile memory element, and an N-type TFT may be used as an element having a non-volatile memory function. Further, an N-type TFT as a nonvolatile memory element forms part of a circuit for reading out information stored in the nonvolatile memory element, and a P-type TFT is used as an element having a nonvolatile memory function. good.

(Fourth embodiment)
FIG. 8 is a schematic configuration diagram of a display device according to the fourth embodiment of the present invention.

  This display device is a TFT (Thin Film Transistor) liquid crystal display.

  The display device 51 includes an insulating substrate and the memory unit 58 formed on the insulating substrate (that is, the memory of the semiconductor memory device of the first embodiment, the second embodiment, or the third embodiment). Including any one of the circuits).

  The display device 51 includes a pixel unit 55, a gate driver 54, a source driver 53, a D / A (analog / digital) converter 52, a control circuit 56, a power supply circuit 57, and a memory unit 58. .

  The pixel portion 55, the gate driver 54, the source driver 53, the D / A converter 52, the control circuit 56, and the power supply circuit 57 have switching elements formed by TFTs (thin film transistors).

  Hereinafter, the operation of the display device 51 will be described.

  The display device 51 is a digital signal input type liquid crystal display. First, a digital video signal is input to the D / A converter 52 from an external terminal, and a timing control signal is input to the control circuit 56 from the external terminal. The power supply voltage is input to the power supply circuit 57 from the external terminal.

  In the D / A converter 52, a signal input as a digital signal is converted into an analog voltage value and supplied to a pixel.

  On the other hand, the source driver 53 and the gate driver 54 supply a voltage to the TFT of the pixel portion 55 in accordance with the timing of the control signal output from the control circuit 56.

  The power supply circuit 57 performs step-up or / or step-down from a voltage input from the outside, so that the pixel unit 55, the D / A converter 52, the source driver 53, the gate driver 54, and the memory An appropriate power supply voltage is supplied to the unit 58.

  The pixel unit 55, the gate driver 54, the source driver 53, the D / A converter 52, the control circuit 56, and the power supply circuit 57 are composed of TFTs, but generally on an insulating substrate. Since the formed TFT has relatively low heat resistance of the insulating substrate, the characteristic variation between elements is large, and this is a major factor for increasing the display characteristic variation of the display device 51.

  For this reason, the display device of the present invention is provided with the memory portion 58 composed of a nonvolatile memory element formed on an insulating substrate, and an operation test is performed after the manufacture of the display device 51 is completed. On the basis of the result of this operation test, the parameter indicated by the digital value for correcting the variation in display characteristics between products of the display device 51 is stored in the memory unit 58.

  The target of the parameter stored in the memory unit 58 includes a parameter indicated by a digital value that corrects variation in display characteristics between products of the display device 51.

  Specific information stored in the memory unit 58 by testing the operation of the display device 51 includes information for finely adjusting the voltage applied to the counter substrate of the display device 51, and TFTs configured in the D / A converter 52. There is information for adjusting an offset voltage caused by variations in element characteristics and adjusting to a function close to a desired circuit characteristic.

  As for the optimization of the voltage applied to the voltage applied to the counter substrate, for example, the display device 51 is turned on and the voltage applied to the counter substrate is swept to detect the voltage with the least flicker and the voltage information. Is stored in the memory unit 58.

  As for the D / A converter, for example, it is measured whether or not a desired analog voltage is output with respect to a digital input value at the time of testing, the output voltage is adjusted as necessary, and the information is obtained. The data is stored in the memory unit 58.

  With the above structure, a highly reliable display device can be provided at low cost.

(Fifth embodiment)
FIG. 9 is a diagram showing a mobile phone as an example of a mobile electronic device in which the semiconductor memory device according to the fifth embodiment of the present invention is incorporated.

  This cellular phone includes a display unit 61, a ROM (read only memory) 62, a RAM (random access memory) 63, a control circuit 64, an antenna 65, a radio circuit 66, a power circuit 67, an audio circuit 68, a camera module 69, a memory card. 70.

  The ROM 62 is built in the mobile phone, has a non-volatile property, and information can be rewritten. The ROM 62 stores data such as program data for operating the control circuit, image data captured by the camera module 69, and audio data for reproduction by the audio circuit 68.

  The data may be stored in the memory card 70. Similar to the ROM 62, the memory card 70 is non-volatile, and information can be rewritten. The memory card 70 is further detachable, and plays a role such as backup of the data, data transfer to other devices, and storage of data that cannot be stored in the ROM 62.

  The ROM 62 and the memory card 70 are configured to send stored data to the control circuit 64 when requested by the control circuit 64.

  The data read from the ROM 62 and the memory card 70 is also transferred to the RAM 63 as necessary.

  In the mobile phone shown in FIG. 9, the display device 61 uses the display device of the fourth embodiment.

  With the above structure, a high-quality mobile phone can be provided at low cost.

  Note that the semiconductor memory device of the first embodiment, the second embodiment, or the third embodiment may be used for a part or all of the ROM 62 and the memory card 70.

  According to the above configuration, a highly reliable mobile phone can be provided at low cost.

1 is a circuit diagram showing a semiconductor memory device according to a first embodiment of the present invention. It is sectional drawing of the load resistive element which the semiconductor memory device of 1st Embodiment has. 3 is a circuit symbol of the load resistance element shown in FIG. 2. It is sectional drawing of the non-volatile memory element which the semiconductor memory device of 1st Embodiment has. It is a circuit symbol of the nonvolatile memory element. It is a circuit diagram of the semiconductor memory device of 2nd Embodiment of this invention. It is a circuit diagram which shows the semiconductor memory device of 3rd Embodiment of this invention. The schematic block diagram of the display apparatus of 4th Embodiment of this invention is shown. It is a figure which shows the mobile telephone with which the semiconductor memory device of 5th Embodiment of this invention was integrated. It is a figure which shows the conventional non-volatile memory element array.

Explanation of symbols

11 ma 1, 11 ma 2, 11 mb 1, 11 mb 2, 211, 311, 312 Non-volatile memory element 11 r Reference element 14 m, 14 r Load resistance element 17 Sense amplifier 213, 214, 313, 314 TFT having non-volatile memory
12ma, 12mb, 12r, 212,221,222,223,224,225,231,232,233,234,235,331,332,333,334,321,322,333,334,335,326,331, 332,333,334 TFT

Claims (10)

A plurality of non-volatile memory elements formed on an insulating substrate and having the same polarity;
A reading unit for reading information stored in the nonvolatile memory element,
The semiconductor memory device, wherein the reading unit includes an identical memory function-containing element having a nonvolatile memory function having the same structure as the nonvolatile memory element. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the same memory function-containing element has a polarity opposite to that of the nonvolatile memory element. The semiconductor memory device according to claim 1 or 2,
The semiconductor memory device, wherein the reading section is a reading circuit having a plurality of thin film transistor elements. The semiconductor memory device according to any one of claims 1 to 3,
The readout section is a readout circuit having a plurality of thin film transistor elements,
The readout circuit has at least two of the same memory function-containing elements,
One of the two identical memory function-containing elements and the other of the two identical memory function-containing elements have opposite polarities. The semiconductor memory device according to claim 1, wherein
The plurality of nonvolatile memory elements include a first nonvolatile memory element and a second nonvolatile memory element,
Each of the first nonvolatile memory element and the second nonvolatile memory element can take a first state or a second state,
When storing the first information, the first nonvolatile memory element is set to the first state, while the second nonvolatile memory element is set to the second state.
When storing the second information, the first nonvolatile memory element is set to the second state, while the second nonvolatile memory element is set to the first state.
Reading whether the first information is written or whether the second information is written by simultaneously referring to the first nonvolatile memory element and the second nonvolatile memory element A semiconductor memory device. The semiconductor memory device according to claim 1 or 2,
The same memory function-containing element is a load resistance element.   A display device comprising the semiconductor memory device according to claim 1.   An electronic apparatus comprising the semiconductor memory device according to claim 1. A plurality of nonvolatile memory elements formed on an insulating substrate and having the same polarity, and a reading unit for reading information stored in the nonvolatile memory element, wherein the reading unit includes the nonvolatile memory element Including one or more load resistance elements having a nonvolatile memory function of the same structure as the volatile memory element, each of the nonvolatile memory element and the load resistance element being a thin film transistor;
A method of manufacturing a semiconductor memory device, wherein a threshold voltage of the load resistance element is varied by injecting electric charge into the load resistance element. A plurality of nonvolatile memory elements formed on an insulating substrate and having the same polarity, and a readout circuit for reading out information stored in the nonvolatile memory element, the readout circuit including the nonvolatile memory element A semiconductor memory device having a nonvolatile memory function having the same structure as that of the volatile memory element and having a first thin film transistor and a second thin film transistor connected symmetrically in the readout circuit;
When the current flowing through the first node in the readout circuit is a predetermined current, a voltage applied to the first thin film transistor and a second symmetrically positioned at the first node in the readout circuit When the current flowing through the node is the predetermined current, the first thin film transistor or the second thin film transistor is charged so that the difference from the voltage applied to the second thin film transistor is equal to or lower than the predetermined voltage. For manufacturing a semiconductor memory device.

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