JP2009300898A - Driving circuit of plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To resolve the problem that a high supply voltage of a scan driver IC excessively rises to destroy the scan driver IC when a specific control signal abnormality occurs in the scan driver IC. <P>SOLUTION: In a driving circuit of a plasma display panel, a comparison circuit which separates an external supply voltage and an internal supply voltage and compares both of them is provided in the scan driver IC, so that it is possible to control an output-stage switch element to prevent destruction of the scan driver IC when an overvoltage is applied to an output terminal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a driving circuit for a plasma display panel.

  In recent years, a plasma display panel (hereinafter abbreviated as “PDP”) is a self-luminous display, has good visibility, is thin, can display large screens, and can be displayed at high speed. It has become. Although PDP has been rapidly spread and has begun to spread widely in general households, circuit blocks to which a high voltage is applied in order to control plasma occupy a very large proportion in the module.

  The PDP module is composed of circuits for driving scan electrodes / sustain electrodes and address electrodes of the PDP panel. The scan electrodes are driven by the scan driver IC, and the address electrodes are driven by the address driver IC. Since these driver ICs apply a high voltage for driving the PDP panel directly to the electrodes, a very high breakdown voltage is required, and a technique for preventing destruction by using a high voltage is also widely disclosed.

For example, Patent Document 1 discloses a technique for protecting an IC against a short circuit between adjacent terminals of a scan driver IC. The output stage circuit of the scan driver has a first transistor that connects the output terminal to the high-voltage power supply and a second transistor that connects to the scan driver reference potential.
When the scanning operation is performed with the adjacent output terminal short-circuited by conductive foreign matter such as metal scrap, the adjacent output that is short-circuited even though the output terminal to be scanned is connected to the scan driver reference potential Since the terminal is connected to the high-voltage power supply voltage, a short circuit between the high-voltage power supply and the ground occurs through the output transistor, and the driver IC is destroyed due to an overcurrent. In order to avoid this phenomenon, according to Patent Document 1, when a short circuit between adjacent terminals occurs, both the first and second transistors are turned off after a predetermined time has elapsed, and the output terminal is in a high impedance state (hereinafter referred to as HiZ). End up.
At this time, element destruction can be prevented by setting the control time to be equal to or less than the short-circuit withstand capability of the output element.

JP 2005-284242 A

  As described above, the scan driver IC is an IC to which a high voltage is applied among the PDP drive circuits, the destruction prevention technique is highly important, and it is essential to establish a technique corresponding to the drive specific to the PDP.

  The problem to be solved in the present invention focuses on this point. The driving sequence of the plasma display is roughly divided into each period called a reset period, an address period, and a sustain period. Patent Document 1 discloses a technique that is particularly effective for an abnormal operation during a scan period. There is no mention of the abnormal behavior inside. The present invention is proposed in view of the above points, and is a destruction prevention technique that is effective for abnormal operation during the sustain period.

  In each of the above-described periods, the scan driver IC performs all output L level output, scan operation, and all output L level output, and when switching between these periods, the panel electrode is temporarily disconnected from the sustain circuit. The stage circuit is set to the HiZ state. That is, the scan driver IC normally takes the three operation states of all output L level output, scan operation, and HiZ, and the operation is controlled by an output control signal. When this output control signal malfunctions, the scan driver IC is destroyed by a mechanism specific to the PDP described below, so that a protection technique is required.

  The scan driver IC is connected between the Y sustain circuit and the panel Y electrode in the PDP drive circuit, and the Y electrode is connected to the X electrode and the X sustain circuit via the panel capacitance. In the sustain period described above, the Y sustain circuit drives the Y electrode through the scan driver IC, and the normal output control of the scan driver IC at this time is all output L level output.

  If an L level output from the output terminal is not made during the sustain period and a situation occurs such that the charge cannot be sucked out from the electrode, for example in the HiZ state, the charge is not sucked out from the Y electrode. First, charge is injected by the X sustain circuit through the panel capacitance. As a result, the charge accumulated in the Y electrode passes through the protection diode and flows into the high-voltage power supply voltage of the scan driver IC, so that an overvoltage is applied to the high-voltage power supply.

  As described above, a plurality of scan driver ICs are used for assigning channels to all the scan lines of the panel. Since these scan driver ICs use a common high-voltage power supply voltage, even if a control abnormality occurs in one scan driver IC, the abnormal voltage is applied to all the scan driver ICs through the high-voltage power supply voltage. All correspondence is required.

In the present invention, a circuit for driving a plasma display, wherein a plurality of first switch elements for connecting an output terminal connected to the scan sustaining electrode to a high voltage power supply voltage and a second switch element for connecting to a reference potential are provided. In the scan circuit provided, the first switch element and the second switch element are controlled independently.
Specifically, the present invention is characterized by detecting an abnormal increase in the high-voltage power supply voltage and controlling the output stage circuit. In addition, a diode for separating the external power supply voltage and the internal power supply voltage is provided, and an abnormality of the high-voltage power supply voltage is detected by a circuit provided for comparing them. In addition, when an abnormality in the power supply voltage is detected, the output stage circuit is set to the full output L level in preference to other control signals, and charges are discharged from the output terminal to the reference potential to prevent overvoltage.

  In addition, it is assumed that the high-voltage power supply voltage has risen at the time of abnormality, and the comparison circuit needs to be configured with a low-voltage power supply voltage. For this reason, it is necessary to provide a voltage dividing resistor for using the internal and external high-voltage power supply voltages as input signals for the comparison circuit operating with the low-voltage power supply voltage.

  According to the present invention, when an overvoltage higher than the externally supplied high voltage power supply voltage that does not exceed the absolute maximum rating is applied to the output terminal due to an abnormality in the control signal of the scan driver IC, the output stage circuit is controlled and the output terminal is controlled. By connecting to the reference potential, it is possible to prevent the scan driver IC from being destroyed and to improve the safety.

  Hereinafter, the best mode of the present invention will be described in detail with reference to the drawings. In each figure, elements having common functions are denoted by the same reference numerals. The present invention is characterized in that when an excessive voltage is applied to the output terminal due to an abnormality in the control signal of the scan driver IC, the output terminal is temporarily short-circuited to the reference potential to avoid IC destruction. And Examples will be described in detail below.

  FIG. 1 is a schematic overall view of a plasma display device, FIG. 2 is a diagram showing a conventional example of a PDP drive circuit, and FIG. 3 is a diagram showing a PDP and a scan driver circuit according to a first embodiment of the present invention. First, a schematic configuration of the plasma display device will be described with reference to FIG.

  In FIG. 1, n Y electrodes 42 and n X electrodes 41 are alternately arranged adjacent to each other. The Y electrode and the X electrode are called display electrodes, but may be called a sustain electrode or a sustain electrode. The address electrode 43 is provided in a direction perpendicular to the display electrode, and a display cell (not shown) is formed at each intersection of each display line formed by the X electrode and the Y electrode and each address electrode.

  The Y electrode is connected to the scan driver 20. The scan driver 20 is provided with an output stage circuit 21 to drive one corresponding Y electrode. For this reason, for example, if the scan driver IC can drive 68 scan sustaining electrodes, in the case of an FHD panel, the number of pixels of the PDP 40 is 1920 × 1080, and 16 scan drivers are used. The scan driver IC is switched by a control signal from the drive control circuit 70 so that scan pulses are sequentially applied in the address period. In the sustain discharge (sustain discharge) period, the X electrode is driven by the X electrode drive circuit 10X, and the Y electrode is driven by the Y electrode drive circuit 10Y via the scan driver.

  The address electrode 43 is connected to the address drive circuit 50. The image signal processing circuit 80 converts the input image signal into a format suitable for operation inside the plasma display device, and then provides the converted signal to the address driving circuit 50.

  Based on the image data converted by the image signal processing circuit 80, the address driving circuit 50 outputs pixel data to be displayed to the address electrode in accordance with a scan pulse from the scan driver 20 during the address period. This causes an address discharge. The drive control circuit 70 generates and supplies a signal for controlling each part of the plasma display device.

The plasma display device is configured as described above, and plasma discharge is controlled by driving each component as follows.
Plasma display driving methods are roughly divided into a reset period, an address period, and a sustain period. In the reset period, regardless of the lighting state in the sustain period before the reset period, the wall charges in the discharge space are neutralized to make the charge state in each discharge space uniform. In the address period, corresponding pixel data is output from the address drive circuit 50 in response to a scan pulse from the scan driver 20, and a voltage write pulse is supplied from the address drive circuit only to the cells to be lit. As a result, a wall charge that does not self-discharge is induced in the X and Y electrodes (address discharge). In the sustain period, the switch SW2X is turned on to apply the low voltage VS1 to the X electrode, and the switch SW1Y is turned on to apply the high voltage VS2 to the Y electrode, so that the PDP 40 performs a sustain discharge. In the next cycle, the Y electrode is set to VS1, and VS2 is applied to the X electrode to maintain the discharge of the X electrode and the Y electrode. Prior to connection to VS1 and VS2, the switches SW3X and SW3Y are turned on to recover power using the resonance of the panel capacitance CP and the coils LX and LY. In other words, charges are stored in the recovery capacitors C1X and C1Y, and most of the power required for charging and discharging the panel capacitance is recovered by supplying the charges stored in the recovery capacitors.

  The outline of the driving method of the plasma display has been described above, but the voltage relationship in the description is VS1 <VS2.

  Next, a circuit configuration for realizing the overvoltage protection of the scan driver according to the present embodiment will be described with reference to FIG. The scan driver 20 drives the Y electrode 42 connected to the output terminal by an output stage circuit composed of first and second switch elements.

  During normal operation, in the sustain period, the first switch element 21 is always off, the second switch element 22 is always on, and the output terminal (Y electrode) is connected to the reference potential. When the low voltage VS1 is applied to the Y electrode 42, the electric charge is extracted from the panel capacitance via the second switch element 22, and when the high voltage VS2 is applied to the Y electrode 42, it is parallel to the second switch element 22. A charge is supplied to the panel capacitor CP through the provided diode 22D.

  The protection technology of the scan driver circuit according to the present invention is effective when the second switch element of the output stage circuit is turned off during the sustain period. At this time, the output stage circuit of the scan driver cannot extract charges from the electrodes and operates as follows.

  When VS1 is applied to the Y electrode, the second switch element 22 that is originally turned on is turned off, so that the charge is not extracted and the voltage VS2 that generated the previous sustain pulse is held. In this state, when the next cycle is reached and the Y sustain drive circuit output Y-SUS transitions to VS1, the reference potential of the scan driver becomes the VS1 voltage, and thus the (VS2-VS1) voltage is applied to the second switch element. . Since this (VS2-VS1) voltage is usually higher than the high-voltage power supply of the scan driver, there is a possibility that it exceeds the element withstand voltage used for the scan driver at this time. Further, since the X electrode is alternately pulsed with the Y electrode, it immediately rises from the VS1 potential to the VS2 potential. Thereby, the Y electrode in the HiZ state is (VS2-VS1) voltage pumped up. By repeating this, the output stage circuit of the scan driver exceeds the absolute maximum rating and is destroyed by the sustain pulse within several times. FIG. 4 shows the Y electrode waveform when a control abnormality occurs at time t0. The solid line is the waveform during normal operation, and the dotted line is the waveform when control abnormality occurs.

  In the present invention, the high-voltage power supply supplied from the outside of the scan driver and the internal high-voltage power supply are separated, and the difference between them is detected to prevent the scan driver from being destroyed when the control failure occurs. First, a separation diode 25 is provided. This is because the external high-voltage power supply voltage and the internal high-voltage power supply voltage are separated, and the difference is detected to switch to the control at the time of abnormality, and the overvoltage generated in the output stage circuit of one scan driver propagates to other scan drivers. Its purpose is to prevent chain destruction. The comparison circuit 26 for detecting a high-voltage power supply abnormality needs to be designed with a low-voltage circuit of a scan driver. In order to make the input signal a high-voltage power supply voltage, the voltage is divided into a voltage suitable for the input signal of the low-voltage circuit. There is a need. The voltage dividing resistors are 27R1, 27R2, 28R1, and 28R2. Needless to say, this resistor must have a certain resistance value or more in order to determine the leakage current of the high-voltage power supply.

  The output of the comparison circuit 26 is input to the output stage control circuit, and controls the output element in preference to other controls. That is, when an abnormality is detected, the first switch element 21 is turned off and the second switch element 22 is turned on, so that the output terminal is set to the full output L level output, and the overvoltage applied to the Y electrode is forcibly discharged to the reference potential.

  As described above, the sustain pulse uses the resonance due to the panel capacitance Cp and the inductance L of the recovery coil to recover power, and its time constant is usually several hundred ns. For this reason, the control can be sufficiently completed even by the method of detecting the overvoltage at the output terminal by the power supply voltage comparison circuit and controlling the output circuit as in the present invention. If the control abnormality is a temporary phenomenon, the scan driver high-voltage power supply voltage converges to a normal voltage after a predetermined time through the voltage dividing resistor and returns to normal operation. If the control abnormality is a permanent phenomenon, the scanning operation cannot be performed and a display abnormality occurs, but the scan driver is not destroyed.

  Here, the first and second switch elements have been described as IGBTs, but it goes without saying that there is no problem even if these are MOSFETs.

  The scan driver is exposed to large switch noise because the output of the sustain circuit is a reference potential. In the present invention, the threshold for abnormal voltage is set by a voltage dividing resistor, but the level of noise due to switching or the like varies from circuit to circuit, and the voltage dividing resistance value can be set uniformly and appropriately. It can be difficult.

  In view of this point, the second embodiment shown in FIG. 5 is characterized in that a plurality of resistance values of the voltage dividing resistors in the first embodiment are prepared and a fuse for selecting them is provided. It has one or more fuses and resistance elements. Here, fuses 28F, 29F, and 30F and trimming voltage dividing resistors 29R and 30R are shown as examples. The manufacturing and trimming methods of the fuse are not limited, but for example, a method of producing with a resistive element and supplying an overcurrent at the time of cutting, or producing with an upper wiring and cutting with a laser can be considered. Since both can be performed in the IC selection process, it is possible to manufacture the same product at the time of IC manufacture, and to adjust the threshold value of the abnormality detection voltage according to the installed model, which is effective for expanding adaptive products and improving mass productivity. .

  Although the configuration in which the trimming resistor and the fuse are arranged in parallel with 28R2 is shown, it goes without saying that there is no problem even if it is arranged in parallel with any other voltage dividing resistor.

  In the second embodiment, a trimming resistor including a fuse and a resistor is used to adjust the threshold value of the abnormality detection voltage with respect to the high-voltage power supply voltage. However, this resistance value needs to be at least several k ohms or more in order to determine the leakage current. Further, since it is necessary to suppress the resistance value fluctuation of the resistance element in the IC in order to ensure the comparison accuracy, it is desirable that the size is larger than a certain level. In this way, it is conceivable to provide a time margin by using the delay circuit 31 shown in FIG. 6 as an embodiment in the case where the voltage dividing resistor cannot be ignored as an area penalty. This prevents the abnormality detection circuit from operating due to ringing, overshoot or the like that may occur in normal operation.

  Specifically, when the abnormal voltage detected by the comparison circuit continues for a certain time or more, the control is switched to the output control at the time of abnormality. For example, the timer circuit delays the output signal of the comparison circuit by gate delay by connecting a plurality of inverters in series. The final stage detects whether or not the abnormal state continues by inputting the output signal delayed using the NAND circuit and the current output signal. This delay time needs to be within 100 ns of the collection period at the maximum.

It is a schematic whole block diagram of a plasma display apparatus. It is a figure which shows the drive circuit of PDP by 1st embodiment of this invention. It is a figure which shows the output stage circuit of the scan driver IC by 1st embodiment of this invention. It is a figure which shows the operation | movement waveform at the time of the normal time used as the object of this invention, and abnormality. It is a figure which shows the output stage circuit of the scan driver IC by 2nd embodiment of this invention. It is a figure which shows the output stage circuit of the scan driver IC by 3rd embodiment of this invention.

Explanation of symbols

SW1X, SW1Y, SW2X, SW2Y, SW3X, SW3Y switch,
10X X sustain circuit, 10Y Y sustain circuit, 20 scan driver,
21 1st switch element, 22 2nd switch element,
23P 23N 24P 24N level shift circuit MOSFET,
25 diode, 26 comparison circuit,
27R1 27R2 28R1 28R2 voltage dividing resistor element,
29F 29R 30F 30R Voltage dividing resistor trimming fuse and resistance element,
31 delay circuit, LX, LY coil,
50 address drive circuit, 40 PDP, 41 X electrode,
42 Y electrode, 43 address electrode, 70 drive control circuit, 80 image signal processing circuit,
C1X, C1Y recovery capacitor

Claims (6)

A circuit for driving a plasma display, comprising: a first switch element for connecting an output terminal connected to a scan sustain electrode to a high-voltage power supply voltage; and a plurality of second switch elements connected to a reference potential ,
A driving circuit for a plasma display panel, wherein the first switch element and the second switch element are independently controlled. A circuit for driving a plasma display, comprising: a first switch element for connecting an output terminal connected to a scan electrode to a power supply voltage; and a plurality of second switch elements connected to a reference potential;
A separation circuit that separates a voltage inside the scan circuit supplied from the power supply voltage and a voltage supplied from outside the scan circuit;
A comparison circuit for comparing the voltages separated by the separation circuit;
A control circuit for controlling the first switch element and the second switch element according to a comparison result by the comparison circuit;
A driving circuit for a plasma display panel, comprising: The scan circuit according to claim 2, wherein
A driving circuit for a plasma display panel, wherein a signal input to the comparison circuit is generated by dividing a voltage supplied from outside and the power supply voltage separated from the voltage by a plurality of resistors. The scan circuit according to claim 2,
A driving circuit for a plasma display panel, comprising a diode as a configuration for separating the voltage. The scan circuit according to claim 2,
A drive circuit for a plasma display panel, comprising a fuse capable of selecting a resistor for dividing a high-voltage power supply voltage. The scan circuit according to claim 2,
A driving circuit for a plasma display panel, comprising a delay circuit so that the control circuit performs control when the comparison circuit detects an abnormal voltage and the state continues for a predetermined time or more.

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