JP2009300651A - Display driver, display device and display driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driver capable of reducing a time required for outputting a useless signal and capable of reducing power consumption when driving a display cell. <P>SOLUTION: An input signal of a high level or a low level according to a display image is captured in a latch circuit 130 at a prescribed timing and the signal level is retained. Then, an output signal from the latch circuit 130 is converted into a signal of a larger amplitude by a delay/level shift circuit 150, thereby generating a driving signal for driving the display cell. Meanwhile, the driving signal in accordance with a signal level retained by the latch circuit 130 is output and, thereafter, in a period until the subsequent input signal is captured by the latch circuit 130 and a signal level of the subsequent input signal is retained, the signal level which is retained in the latch circuit 130 theretofore is cleared by a data clearing part 131 and the output signal from the latch circuit 130 is set into the low level. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display driving device for driving a display cell on a display panel by outputting a driving signal corresponding to a display image, a display device having a function corresponding to this device, and a display for driving the display cell. The present invention relates to a driving method.

  In many recent PDPs (Plasma Display Panels), each display cell (discharge cell) is driven by three electrodes: an address electrode, a scan electrode, and a sustain electrode. The address electrode is provided in the vertical direction of the screen, and the scan electrode and the sustain electrode are provided in the horizontal direction of the screen. The PDP displays an image by generating a plasma in the discharge cell with a high potential difference between these electrodes.

  Of these electrodes, the address electrode is driven by an address driver. An output terminal of the address driver is prepared for each of a large number of output bits, and the PDP is driven by setting the output of each bit to H (high) level or L (low) level. Here, the amplitude of the input data to the address driver is, for example, about 3.3V, while the amplitude of the output bit is, for example, about 60V to 70V. The output of each bit is determined by the value of input data.

  In the normal operation of the address driver, input data is taken in at the rising or falling timing of the clock signal, and the data of each bit is transferred to the corresponding circuit by the shift register circuit. The data of each bit is latched by a latch circuit and then output to an output circuit including a level shift circuit.

  Here, the transition time of the output level from the output circuit corresponding to the input data is, for example, about 100 ns to 300 ns. Since a large amount of switching noise is generated during this period, the influence on the logic unit including the shift register or the like is large, and a malfunction may occur in the logic unit. For this reason, in many logic units, data is input while avoiding the transition period of the output level in the output circuit. For example, after all input data is taken into the latch circuit, the data of each bit is transferred to the output circuit in accordance with a common latch signal.

  In addition, the driving state of the PDP is roughly divided into an address period, a sustain period, and a reset period. In the address period, the scan driver scans the PDP horizontal scanning lines in order, and the address driver determines the output level in accordance with the scanning timing. Then, after the last scan line is scanned, the sustain period is started, and a sustain operation for maintaining the discharge of the discharge cell is performed by the two horizontal electrodes (scan electrode and sustain electrode). Furthermore, a reset operation is performed to shift to the reset period and stop the discharge and erase the stored information of each discharge cell at once.

Here, the output from the address driver during the sustain period is often set to 0 V in common for all bits. For this reason, in many address drivers, a function for controlling all output bits in common is provided, and all output bits are fixed to the same value except during the address period (see, for example, Patent Document 1). . Such an output control circuit is provided at the next stage of the latch circuit, for example.
JP 2006-65316 A

  By the way, during the address period, the output of the address driver is at a different level for each output bit according to the input data. After that, when the sustain period is started, the output of the address driver is fixed to, for example, L level for all bits. Furthermore, when the reset period ends thereafter, the output level is no longer fixed by the output control circuit, and the address period starts.

  However, at the timing when the reset period ends, the previous output data is held in the latch circuit. For this reason, when the reset period ends and the output level is unfixed, the output data held in the latch circuit is output again. Since this output data is unnecessary, there is a problem that unnecessary power is consumed by performing an unnecessary switching operation in accordance with the output. In addition, in order to accurately fetch the next input data, it is necessary to fetch the next input data after waiting for about 200 ns to 300 ns from the end of the reset period, for example. Therefore, the address period becomes long, resulting in the sustain. There is also a problem that the brightness of the PDP is lowered due to the shortening of the period. Then, it has been demanded to solve such a problem by an operation as simple as possible.

  The present invention has been made in view of these points, and an object of the present invention is to provide a display drive device, a display device, and a display drive method that reduce the time required for useless signal output and reduce power consumption. .

  In the present invention, in order to solve the above-described problem, in a display driving device that drives a display cell on a display panel by outputting a driving signal corresponding to a display image, a high-level or low-level input signal corresponding to the display image is output. A latch unit that captures the signal level at a predetermined timing and holds the signal level, a level shift unit that converts the output signal from the latch unit into a signal having a larger amplitude and generates the drive signal, and the latch unit A data clear unit for clearing the signal level and setting the output signal to a low level, and after the drive signal corresponding to the signal level held in the latch unit is output from the level shift unit , Until the next input signal is taken in by the latch unit and the signal level is held by the data clear unit. Signal level is the output signal is cleared is set to the low level, the display driving apparatus, wherein provided that.

  In such a display driving apparatus, a high level or low level input signal corresponding to a display image is taken into the latch unit at a predetermined timing, and the signal level is held. The output signal from the latch unit is converted into a signal having a larger amplitude by the level shift unit, and a drive signal for driving the display cell is generated. In addition, after the drive signal corresponding to the signal level held by the latch unit is output from the level shift unit, the data is cleared in a period from when the next input signal is taken in by the latch unit and the signal level is held. The signal level held in the latch unit is cleared by the unit, and the output signal from the latch unit is set to the low level.

  In order to solve the above problems, the present invention provides a display device having the function of the display drive device and a display drive method for performing the same processing as the display drive device.

  According to the display drive device of the present invention, after the drive signal corresponding to the signal level held by the latch unit is output from the level shift unit, the next input signal is captured by the latch unit and the signal level is held. In this period, it is not necessary to output an unnecessary signal held in the latch unit through the level shift unit or the like, and power consumption for the signal output is not performed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a main configuration of a display device according to an embodiment.
The display device shown in FIG. 1 is a device using the PDP 11 as a display device, and includes an address driver 12, a scan driver 13, a sustain driver 14, and a control circuit 20 as functions for driving the PDP 11. The control circuit 20 includes a display information processing unit 21 and a timing control unit 22.

  An address electrode group (not shown) parallel to each other is provided on one surface of the PDP 11. Further, a scan electrode group and a sustain electrode group (both not shown) are provided on the facing surface in a direction orthogonal to the address electrode group. A discharge cell (not shown) is formed at a position where the address electrode group intersects with the scan electrode group and the sustain electrode group.

  The address driver 12 drives the address electrode group according to the input data from the display information processing unit 21 to discharge each discharge cell. The scan driver 13 scans the scan electrode group by sequentially applying a voltage. In the address period, the scan electrode group is sequentially scanned by the scan driver, and the output of the address driver is determined according to the scanning timing. The sustain driver 14 drives the sustain electrode and maintains the discharge of each discharge cell in the sustain period after the end of the address period.

  In the control circuit 20, the display information processing unit 21 converts display data input from the outside into data pulses for driving the PDP 11 and supplies the data pulses to the address driver 12. The timing control unit 22 outputs a clock signal and various control signals to the address driver 12, the scan driver 13, and the sustain driver 14 to control their operation timing.

  In the PDP 11 described above, the scan driver 13 controls the scan electrode group, and the address driver 12 controls the address electrode group, whereby the lighting / non-lighting operation of each discharge cell is controlled. Thereby, a desired image is displayed.

FIG. 2 is a diagram showing a schematic configuration of an address driver IC (Integrated Circuit) provided in the address driver.
The address driver 12 includes one or more address driver ICs 12a as shown in FIG. The address driver IC 12a includes an input buffer circuit 110, a shift register circuit 120, a latch circuit 130, a gate circuit 140, a delay / level shift circuit 150, and an output circuit 160. The address driver 12 includes 8-port input terminals IN1 to IN8 and 256-port output terminals OUT1 to OUT256.

  The input buffer circuit 110 receives the display data output from the display information processing unit 21 through the input terminals IN1 to IN8, temporarily accumulates them, and then outputs them to the shift register circuit 120.

  The shift register circuit 120 takes display data from the input buffer circuit 110 in synchronization with the clock signal and accumulates these values. In the present embodiment, the shift register circuit 120 parallelizes each input signal from the eight input ports as 32-bit data. The output terminals OUT1 to 256 correspond to one output bit of (32 × 8) bits output from the shift register circuit 120, respectively.

  The latch circuit 130 latches the data corresponding to each output bit stored in the shift register circuit 120 according to the latch signal supplied from the timing control unit 22 and outputs the latched data to the gate circuit 140. As will be described later, in the present embodiment, the latch circuit 130 is provided with a data clear unit 131 for clearing a value held in the circuit in accordance with an input control signal.

  The gate circuit 140 has a function of setting all the data of each bit from the latch circuit 130 to a predetermined value in accordance with the blank control signal output from the timing control unit 22.

  The above input buffer circuit 110, shift register circuit 120, latch circuit 130, and gate circuit 140 are driven by the power supply voltage VDD1. On the other hand, delay / level shift circuit 150 and output circuit 160 are driven by power supply voltage VDD2 higher than power supply voltage VDD1.

  The delay / level shift circuit 150 converts the voltage level of the data pulse of each output bit supplied through the gate circuit 140 into a higher predetermined voltage level. The delay / level shift circuit 150 is also provided with a delay circuit for adjusting the propagation timing of the data pulse.

  The output circuit 160 includes a high breakdown voltage buffer having a p-channel MOS (Metal-Oxide-Semiconductor) transistor Tr61 and an n-channel MOS transistor Tr62 for each output bit. The data pulse of each bit subjected to voltage conversion by the delay / level shift circuit 150 is output to the output terminals OUT1 to OUT256 through the corresponding high voltage buffer.

FIG. 3 is a timing chart showing the operation of the address driver IC in the address period.
In FIG. 3, data A1 to A8 are display data supplied from the input terminals IN1 to IN8 to the shift register circuit 120 via the input buffer circuit 110, respectively. The clock signal CLK is output from the timing control unit 22 of the control circuit 20.

  As described above, the shift register circuit 120 converts data from each input port into 32-bit data. In the present embodiment, the values of the data A1 to A8 are taken in at the rising timing and falling timing of the clock signal CLK as in the timings T1 and T2 in the figure. Accordingly, when the clock signal CLK for 16 pulses is input, values corresponding to all output bits are accumulated in the shift register circuit 120. In the figure, “On” (n is an integer) added to the data A1 to A8 indicates the value of the data at the nth bit in the output bits.

  The latch signal LAT is supplied from the timing control unit 22 to the latch circuit 130, and the latch circuit 130 latches input data at the falling timing of the latch signal LAT. After the data of all the output bits is taken in, the latch signal LAT is set from the H level to the L level at timing T3. At this time, the latch circuit 130 latches the value of each output bit from the shift register circuit 120. Thus, the output continues to the gate circuit 140 for a predetermined period.

  In the example of FIG. 3, as a result of the latch operation, the value of the bit corresponding to the output terminal OUT1 is “0” (L level), and the value of the bit corresponding to the output terminal OUT256 is “1” (H level). Yes. Then, the 256-bit value determined in this way is supplied to the PDP 11 via the corresponding address electrode.

  In FIG. 3, blank control signals HBLK and LBLK are both signals supplied from the timing control unit 22 to the gate circuit 140. The gate circuit 140 controls the value of each bit output to the delay / level shift circuit 150 in these blank control signals HBLK and LBLK.

  Here, the gate circuit 140 controls the output signal level according to the values of the blank control signals HBLK and LBLK as shown in the next truth table.

  In this truth table, DINn represents an n-bit value in input data, and DOUTn represents an n-bit output value. “H” indicates H level, “L” indicates L level, and “X” indicates either H level or L level.

  According to this truth table, the gate circuit 140 sets the output value of each bit to the same value as the input value when both the blank control signals HBLK and LBLK are at the H level. For example, as shown in FIG. 3, in the address period, the blank control signals HBLK and LBLK are both at the H level, and the value of each bit latched by the latch circuit 130 is output to the delay / level shift circuit 150 as it is. The

  In addition, when the blank control signal LBLK is at the L level, the gate circuit 140 has the same output value of each bit regardless of the input value regardless of whether the blank control signal HBLK is at the H level or the L level. Set to L level. For example, as will be described later, in the sustain period and the reset period after the address period, the blank control signal LBLK is set to the L level. Thereby, in these periods, all the outputs of the output terminals OUT1 to OUT256 are set to the L level.

  Furthermore, when the blank control signal HBLK is at the L level and the blank control signal LBLK is at the H level, the gate circuit 140 can also set the output values of the respective bits to the same H level regardless of their input values.

  Next, FIG. 4 is a diagram illustrating a circuit configuration example of the gate circuit and the delay / level shift circuit. FIG. 4 shows only the circuit configuration corresponding to one of the output bits.

  The gate circuit 140 has a configuration in which NAND gates G41 and G42 are connected in series. An output signal corresponding to each output bit from the latch circuit 130 and a blank control signal HBLK are input to each input terminal of the first-stage NAND gate G41. Further, the output signal of the NAND gate G41 and the blank control signal LBLK are input to each input terminal of the second-stage NAND gate G42. With such a configuration, the output level is controlled as shown in the truth table.

  The delay / level shift circuit 150 includes a level shifter unit 151, delay circuits 152 and 153, and the like. The level shifter 151 includes p-channel MOS transistors Tr51 and 52 and n-channel MOS transistors Tr53 and Tr54.

  An output signal from the gate circuit 140 is input to the gate terminal of the MOS transistor Tr53 via the inverters INV51 and INV52, the delay circuit 152, and the inverter INV53. The output signal from the delay circuit 152 is input to the gate terminal of the MOS transistor Tr54. That is, the same value as the output signal from the gate circuit 140 is input to the gate terminal of the MOS transistor Tr54, and its inverted value is input to the gate terminal of the MOS transistor Tr53.

  The MOS transistors Tr51 and Tr53 have their drain terminals connected to each other, and the MOS transistors Tr52 and Tr54 have their drain terminals connected to each other. Each gate terminal of the MOS transistors Tr51 and Tr52 is connected to the other drain terminal. The MOS transistors Tr51 and Tr52 hold the input signal values corresponding to the on / off states of the MOS transistors Tr53 and Tr54 while inverting each other.

  The drain terminal of the MOS transistor Tr54 is connected to the gate terminal of the MOS transistor Tr61 of the output circuit 160. The output signal from the gate circuit 140 is input to the gate terminal of the MOS transistor Tr62 of the output circuit 160 via the inverter INV54 and the delay circuit 153. Therefore, in this embodiment, the logic value output from the gate circuit 140 is configured to match the logic value output from the output terminal of the output circuit 160. Further, the signal level when the logical value is “1” is converted into the power supply voltage VDD2. Note that the delay amounts of the delay circuits 152 and 153 are determined so that the input signals to the gate terminals of the MOS transistors Tr61 and Tr62 are synchronized.

  Next, an operation including a period other than the address period in the address driver IC 12a will be described. Here, for reference, the configuration and operation in the case where the data clear unit 131 shown in FIG. 2 is not provided for the latch circuit 130 will be described first, and the problem will be described in detail. The configuration and operation of the embodiment of the invention will be described.

FIG. 5 is a diagram illustrating a configuration example of the latch circuit when the data clear unit is not provided.
The latch circuit 230 illustrated in FIG. 5 includes inverters INV31 to INV36 and switches SW31 to SW34. The latch circuit 230 has a configuration in which two stages of D latches 231 and 232 are connected in series.

  In the D latch 231, a switch SW31 is connected to the input stage thereof, and inverters INV32 and INV33 are connected in a loop through the switch SW32. In the D latch 232, the switch SW33 is connected to the input stage, and the inverters INV34 and INV35 are connected in a loop via the switch SW34.

  The switches SW31 to SW34 selectively conduct the input signal according to the latch signal LAT supplied from the timing control unit 22 of the control circuit 20. When the latch signal LAT is at the H level, the switches SW31 and SW34 are turned on, and the switches SW32 and SW33 are turned off. At this time, the output signal from the shift register circuit 120 is input to the D latch 231 via the inverter INV31 and passes through the switch SW31 and the inverter INV32.

  Next, when the latch signal LAT becomes L level, the switches SW31 and SW34 are cut off and the switches SW32 and SW33 are turned on. At this time, the value of the input signal at the fall of the latch signal LAT is held in the D latch 231 and the value is taken into the D latch 232. Further, when the latch signal LAT again becomes the H level, the fetched value is held in the D latch 232. On the other hand, the D latch 231 is in a state where an input signal can be captured.

  With the above configuration, the latch circuit 230 holds the value output from the shift register circuit 120 when the latch signal LAT falls, and then uses the value until the latch signal LAT becomes L level. Continue to output to 140. Therefore, when this latch circuit 230 is applied to the address driver IC 12a of FIG. 2, the operation of the address driver IC 12a in the address period is as shown in FIG.

FIG. 6 is a timing chart showing the operation of the address driver IC when the latch circuit of FIG. 5 is used.
The driving state of the PDP is roughly divided into an address period, a sustain period, and a reset period. In the address period of timings T11 to T12 in FIG. 6, as described with reference to FIG. 3, input data is taken in by the shift register circuit 120, and these data are latched by the latch circuit 230 at the falling timing of the latch signal LAT. .

  At the start of the address period, blank control signal LBLK is set to H level. At this time, the blank control signal HBLK is kept at the H level, whereby the output signal from the latch circuit 230 passes through the gate circuit 140 as it is.

  Further, the sustain period starts from the timing T12. At this time, the blank control signal LBLK is set to the L level. Thereby, in the sustain period (and the reset period), the values of all output bits are controlled to be “0” (L level). In the example of FIG. 6, the output signal from the output terminal OUT256 changes from the H level to the L level at the timing T12.

  Further, at timing T13, the reset period is ended and the next address period is started. At this time, the blank control signal LBLK is set to the H level again, so that the input data taken in can be output via the gate circuit 140.

  However, such an operation has the following problems. In the sustain / reset period, the output signals from all the output terminals OUT1 to OUT256 are fixed to the L level by the function of the gate circuit 140. However, during these periods, since the value corresponding to the input data is held in the D latch 232 of the latch circuit 230, the value of the input data is still output from the latch circuit 230. Therefore, when the next address period is started and the blank control signal LBLK is set to the H level, the data held in the latch circuit 230 is output from the output terminal via the gate circuit 140 or the like. In the example of FIG. 6, at the timing T13, the signal level of the output terminal OUT256 returns to the H level corresponding to the input data in the previous address period.

  Since the data held in the previous address period is unnecessary data, the switch circuit in the address driver IC 12a performs unnecessary switching operation in association with the output of such data, and is wasted. Power is consumed.

  Further, since it is necessary to perform a new input data fetching operation after outputting such unnecessary data, the address period becomes longer by an extra time, for example, 200 ns to 300 ns. For this reason, it is necessary to relatively shorten the sustain period, and as a result, there is a problem that the luminance of the PDP is lowered.

  As a method for avoiding such a problem, for example, before or after the reset period, dummy input data in which all the bits become L level are fetched into the address driver IC 12a, and this data is latched. A method of performing an operation in a normal address period after being held in the circuit 230 is also conceivable. However, even with this method, there remains a problem that an extra switching operation is performed for taking in dummy data and power is consumed. There is also a problem that the circuit configuration and control operation for such control become complicated.

  Therefore, in this embodiment, the latch circuit 130 is provided with a data clear unit 131 for clearing the held data, and the held data in the latch circuit 130 is cleared before the start of a new address period. To solve the above problem. Further, by controlling the operation of the data clear unit 131 according to the existing blank control signal LBLK, the control of the clear operation is simplified and the circuit scale is suppressed.

  FIG. 7 is a diagram illustrating a configuration example of the latch circuit according to the embodiment. In FIG. 7, the same reference numerals are given to the components corresponding to FIG. 5, and description thereof will be omitted as appropriate.

  The latch circuit 130 shown in FIG. 7 has a configuration in which the inverters INV33 and INV34 in the latch circuit 230 shown in FIG. 5 are replaced with NAND gates G31 and G32, respectively. These NAND gates G31 and G32 function as the data clear unit 131 described above.

  An output signal of the inverter INV32 is input to one input terminal of the NAND gate G31, and a blank control signal LBLK is input to the other input terminal. An output signal from the switch SW33 is input to one input terminal of the NAND gate G32, and a blank control signal LBLK is input to the other input terminal.

  When the blank control signal LBLK is at the H level, a D latch is configured by the loop circuit of the inverter INV32 and the NAND gate G31 and the loop circuit of the NAND gate G32 and the inverter INV35, respectively. Therefore, at this time, the latch circuit 130 performs exactly the same operation as the latch circuit 230 shown in FIG.

  On the other hand, when blank control signal LBLK is at the L level, the output signals of NAND gates G31 and G32 are both at the H level. At this time, the value held by the D latch is set so that the output of the latch circuit 130 becomes L level.

FIG. 8 is a timing chart showing the operation of the address driver IC when the latch circuit of FIG. 7 is used.
As shown in FIG. 8, each circuit in the address driver IC 12a performs exactly the same operation as in FIG. 6 in the address period from timing T21 to T22. When the address period ends at timing T22 and the blank control signal LBLK is set to the L level, the output signal of the gate circuit 140 is fixed to the L level, and accordingly, from all the output terminals OUT1 to OUT256. Are set to the L level.

  Here, immediately before the timing T <b> 22, the value of the output data from the shift register circuit 120 is held in the latch circuit 130. Specifically, a value corresponding to the output signal from the shift register circuit 120 is held in a loop circuit including the NAND gate G32 and the inverter INV35.

  However, when the blank control signal LBLK is set to the L level at the timing T22, the output signal of the NAND gate G32 is forcibly set to the H level, and the value held in the loop circuit of the NAND gate G32 and the inverter INV35. Is cleared. At this time, the output signal of the latch circuit 130 is fixed at the L level.

  Thus, at the timing T23, when the reset period ends and the blank control signal LBLK is set to the H level, the latch circuit 130 always outputs an L level signal. That is, at this time, as shown in FIG. 8, the output signals from all the output terminals OUT1 to OUT256 are maintained at the L level. Accordingly, input data from the shift register circuit 120 can be captured in this state.

  Note that in the sustain reset period, the output signal of the gate G31 is also fixed to the H level in accordance with the change of the blank control signal LBLK, so the values held by the inverter INV32 and the NAND gate G31 are also cleared, causing malfunction. Can be prevented. However, as a function of the data clear unit 131, such a function by the NAND gate G31 is not essential.

  As described above, by providing the data clear unit 131 that clears the value held in the latch circuit 130 according to the blank control signal LBLK in the sustain / reset period, the value is input as soon as the next address period starts. Data can be imported. Further, it is not necessary to take measures such as fetching input data for data clear. Therefore, the address period can be shortened and the sustain period can be relatively lengthened to increase the brightness of the PDP. Further, since it is not necessary to perform a switching operation for outputting extra data, power consumption is reduced.

  Furthermore, by performing the above clear operation in accordance with the existing blank control signal LBLK, the control procedure for the clear operation and the circuit configuration therefor can be simplified. Therefore, the circuit scale and manufacturing cost of the address driver IC 12a can be suppressed.

  The circuit configuration for realizing the function of the data clear unit 131 is not limited to the above example. However, with the configuration shown in FIG. 7, design changes from the existing address driver IC can be minimized.

  Further, the present invention can be applied not only to a display device using a PDP as a display device as in the above embodiment, but also to, for example, an organic EL (Electroluminescence) display. That is, the present invention is applicable to a display device having a function of generating a high voltage signal by level-shifting a pulse signal corresponding to a display image and fixing the output signal level to a predetermined value. .

It is a figure which shows the principal part structure of the display apparatus which concerns on embodiment. It is a figure which shows schematic structure of the address driver IC provided in an address driver. 6 is a timing chart showing the operation of the address driver IC in the address period. It is a figure which shows the circuit structural example of a gate circuit and a delay / level shift circuit. It is a figure which shows the structural example of a latch circuit in case the data clear part is not provided. 6 is a timing chart showing the operation of the address driver IC when the latch circuit of FIG. 5 is used. It is a figure which shows the structural example of the latch circuit which concerns on embodiment. 8 is a timing chart showing the operation of the address driver IC when the latch circuit of FIG. 7 is used.

Explanation of symbols

11 PDP
12 Address driver 12a Address driver IC
13 Scan Driver 14 Sustain Driver 20 Control Circuit 21 Display Information Processing Unit 22 Timing Control Unit 110 Input Buffer Circuit 120 Shift Register Circuit 130 Latch Circuit 131 Data Clear Unit 140 Gate Circuit 150 Delay / Level Shift Circuit 160 Output Circuit

Claims (8)

In a display driving device for driving a display cell on a display panel by outputting a driving signal corresponding to a display image,
A latch unit that captures a high-level or low-level input signal corresponding to a display image at a predetermined timing and holds the signal level;
A level shift unit that converts the output signal from the latch unit into a signal having a larger amplitude and generates the drive signal;
A data clear unit that clears the signal level held in the latch unit and sets the output signal to a low level;
Have
After the drive signal corresponding to the signal level held in the latch unit is output from the level shift unit, until the next input signal is captured by the latch unit and the signal level is held, The display driving apparatus, wherein the data clear unit clears the signal level held in the latch unit and sets the output signal to a low level. In response to the input level control signal, after the drive signal corresponding to the signal level held by the latch unit is output from the level shift unit, the latch unit captures the next input signal and sets the signal level. A signal converter that converts the level of the signal supplied from the latch unit to the level shift unit to a low level until the holding is started;
2. The display driving device according to claim 1, wherein the data clear unit clears the signal level held in the latch unit and sets the output signal to a low level in accordance with the level control signal. The display cell is a discharge cell constituting a plasma display panel,
In the sustain period for maintaining the discharge of the discharge cell in accordance with the drive signal and in the reset period in which stored information of the discharge cell is erased in accordance with the level control signal, the signal conversion unit The display driving device according to claim 2, wherein the level of the signal supplied from the to the level shift unit is converted to a low level. The latch unit includes a loop circuit in which an inverter circuit and a negative AND gate circuit are loop-connected,
Among the input terminals of the NAND gate circuit, the level control signal is input to the other input terminal not connected to the output terminal of the inverter circuit, and when the level control signal is high level, 3. The display driving device according to claim 2, wherein the signal level of the input signal is held by a loop circuit, and the held signal level is cleared when the level control signal is at a low level. A latch unit that captures a high-level or low-level input signal corresponding to a display image at a predetermined timing and holds the signal level;
A level shift unit that converts the output signal from the latch unit into a signal having a larger amplitude and generates a drive signal for driving a display cell on the display panel;
A data clear unit that clears the signal level held in the latch unit and sets the output signal to a low level;
After the drive signal corresponding to the signal level held by the latch unit is output from the level shift unit, until the next input signal is taken in by the latch unit and the signal level is held, A control unit that controls the data clear unit to clear the signal level held in the latch unit and set the output signal level to a low level;
A display device comprising: In accordance with an input level control signal, further comprising a signal conversion unit that converts the level of the signal supplied from the latch unit to the level shift unit to a low level,
The control unit outputs the level control signal, and after the drive signal corresponding to the signal level held by the latch unit is output from the level shift unit, the latch unit captures the next input signal. And until the signal level starts to be held, the signal converter converts the output signal to a low level,
In response to the level control signal, the data clear unit clears the signal level held in the latch unit and sets the output signal to a low level.
The display device according to claim 5. A plurality of display drive units including at least the latch unit, the level shift unit, the data clear unit, and the signal conversion unit;
The display device according to claim 6, wherein the control unit outputs the common level control signal to the display driving units. In a display driving method for driving display cells on a display panel,
The latch unit captures a high-level or low-level input signal corresponding to the display image at a predetermined timing and holds the signal level,
The level shift unit converts the output signal from the latch unit into a signal having a larger amplitude, and generates a drive signal for driving the display cell,
After the drive signal corresponding to the signal level held by the latch unit is output from the level shift unit, until the next input signal is taken in by the latch unit and the signal level is held, The data clear unit clears the signal level held in the latch unit and sets the output signal to a low level.
A display driving method characterized by the above.

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