JP2009296318A - Precoder circuit, and receiving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a precoder which can suppress cost without taking measures against the bit deviation of an I/Q channel input in a transmitting side and performs processing with only the digital circuit in a receiving side by arranging a differential encoding processing circuit in the receiving side. <P>SOLUTION: There are provided a differential encoding operation portion 41 which calculates the optical signal absolute phase of a next symbol by adding a phase difference to the optical signal absolute phase preceeded by one symbol; a feedback register 42 which delays the output of the differential encoding operation portion 41 as long as one clock by symbol rate; and a phase assigning circuit 43 which outputs the output of the feedback register 42 to the differential encoding operation portion 41 as it is, or according to the phase instruction signal from outside, outputs the output of the feedback register 42 the differential encoding operation portion 41 through phase rotation. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a precoder circuit in which a precoder circuit required in a differential phase communication system is arranged on the rear stage side so that a phase state held therein can be rotated and a receiving apparatus including the precoder circuit.

  Conventionally, in the field of optical communication, a binary simple modulation method called light intensity modulation-direct detection method (IM-DD: Intensity Modulation-Direct Detection) has been used for a long time. However, from the viewpoint of improving frequency utilization efficiency and narrowing the spectrum, there is an active movement to adopt multi-level phase modulation technology. In phase modulation in optical communication, the device is high-speed, so that coherent detection used in wireless communication or the like is difficult, and differential phase modulation using delay detection, which is easy to design a receiver, has become the mainstream. For example, a method using four phases is called differential quadrature phase shift keying (DQPSK), and research and development are actively performed.

  In delay detection, an information sequence is assigned to the phase difference between the front and rear symbols of an optical signal on the transmission side. On the receiving side, the original phase difference is extracted by multiplying the signal delayed by one symbol and the original signal. On the transmission side, a process of assigning an information sequence to a phase difference between symbols is performed using a precoder.

  A conventional optical transmitter to which the DQPSK system is applied will be described with reference to FIG. FIG. 11 is a diagram illustrating a configuration of a conventional optical transmitter to which the DQPSK system is applied (see, for example, Patent Document 1).

In the DQPSK system, as shown in FIG. 11, first, transmission information I _k and Q _k are converted by a precoder 95 and output as η _k and ρ _k . This is converted into a four-phase state of light using an optical DQPSK encoder (ENCODER) and transmitted. Specifically, the optical signal output from the DFB laser 91 is converted into a phase of light using optical modulators PM (Phase Modulator) 92 and PM 93 based on η _k (I channel) and ρ _k (Q channel). Modulate and transmit as a state.

  By configuring the transmitter as shown in FIG. 11, it becomes possible to apply the DQPSK system to optical communication, enhance resistance to various signal deterioration factors, increase frequency utilization efficiency, and increase communication speed. Can be planned.

JP 2006-245647 A (page 3, FIG. 3)

  In the precoder in DQPSK, the processed I channel and Q channel signals are combined to make sense, so the phases of both signals must be matched and output to the optical encoder. However, in optical communication, since the symbol rate of a signal is very high, such as several tens of gigabits, an extremely small error of about several tens of picoseconds can be allowed between input signals.

  Usually, a digital circuit inside an LSI that performs electrical processing such as a framer operates at a speed of several hundred MHz or less, and a time division multiplexing (MUX) circuit is used to increase the speed to a symbol rate. In DQPSK, the I channel and the Q channel are multiplexed by different MUXs. However, in such a configuration, the bit multiplexing position cannot be synchronized between the two MUXs, and a difference of 1 bit or more may occur. .

  As described above, in the DQPSK system in optical communication, in order to apply a precoder on the transmission side, a device must be designed to accurately match the phase difference between the I channel and the Q channel, and the production cost is high. There was a problem of becoming.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to arrange a differential encoding processing circuit on the receiving side to prevent bit shift of the I / Q channel input on the transmitting side. A precoder circuit and a receiving apparatus that can deal with only the digital circuit on the receiving side and suppress the cost without taking any measures are obtained.

  The precoder circuit according to the present invention includes: a differential encoding operation unit that calculates an optical signal absolute phase of the next symbol by adding a phase difference to the optical signal absolute phase of the previous symbol; and the differential encoding operation unit A feedback register that delays the output by one clock at a symbol rate, and outputs the output of the feedback register as it is to the differential encoding operation unit, or rotates the phase of the output of the feedback register according to an external phase designation signal And a phase designation circuit for outputting to the differential encoding operation section.

  The precoder circuit according to the present invention is arranged on the receiving side so that the phase state held therein can be rotated without taking measures against the bit shift of the I / Q channel input on the transmitting side, thereby reducing the cost. There exists an effect that it can control.

Embodiment 1 FIG.
A precoder circuit according to Embodiment 1 of the present invention will be described with reference to FIGS. 1 is a block diagram showing a configuration of an optical DQPSK communication system including a precoder circuit and a receiving apparatus according to Embodiment 1 of the present invention. In addition, in each figure, the same code | symbol shows the same or equivalent part.

  In FIG. 1, the optical DQPSK communication system includes an optical DQPSK encoder 1, an optical fiber transmission line 2, an optical DQPSK decoder 3, a subsequent-stage differential precoder circuit 4, and a frame synchronization circuit 5. The optical DQPSK decoder 3, the precoder circuit 4, and the frame synchronization circuit 5 constitute a receiving device.

  FIG. 2 is a block diagram showing a configuration of the precoder circuit according to the first embodiment of the present invention.

  In FIG. 2, the precoder circuit 4 adds a phase difference to the optical signal absolute phase of the previous symbol to calculate the optical signal absolute phase of the next symbol, and this differential encoding operation. The feedback register 42 that delays the output of the unit 41 by one clock at the symbol rate, and the output of the feedback register 42 is output to the differential encoding calculation unit 41 as it is, or according to the phase designation signal from the outside, A phase designation circuit 43 that rotates the phase of the output and outputs it to the differential encoding operation unit 41 is provided.

  FIG. 3 is a diagram showing the configuration of the phase designation circuit in the precoder circuit according to the first embodiment of the present invention.

  In FIG. 3, the phase specifying circuit 43 is provided with a selector 431, an inverter 432, and a selector 433.

  Next, the operation of the precoder circuit according to the first embodiment will be described with reference to the drawings.

  In the precoder circuit 4 shown in FIG. 2, the differential encoding operation unit 41 inputs the input 2-bit difference data series and the 2-bit output of the phase specifying circuit 43 and performs differential encoding. The feedback register 42 delays the 2-bit output from the differential encoding calculation unit 41 by one clock at the symbol rate and outputs the delayed signal to the phase designation circuit 43. The phase designation circuit 43 passes the output from the feedback register 42 as it is, or outputs a 2-bit restored data series in accordance with an external phase designation signal.

Here, b _I (n) and b _Q (n) are input 2-bit differential data sequences, and d _I (n) and d _Q (n) are restored data sequences that are the output of the differential encoding operation unit 41. Assuming that the output of the feedback register 42 corresponding to the signal phase data one symbol before the data series is d _I (n−1) and d _Q (n−1), the differential encoding operation unit 41, for example, This is a circuit for performing the operations shown in (1) and (2). This corresponds to the operation of adding the phase difference to the optical signal absolute phase one symbol before and calculating the optical signal absolute phase of the next symbol.

  Next, the operation of the optical DQPSK communication system shown in FIG. 1 will be described. FIG. 4 is a diagram showing the mapping of the input data series to the optical signal phase by the optical DQPSK encoder. The optical DQPSK encoder 1 maps the 2-bit input data series Iin and Qin, which are electrical signals, into four states of the optical signal absolute phase Φ (n) to be transmitted. For example, this mapping is assigned as shown in FIG.

The optical signal generated by the optical DQPSK encoder 1 is transmitted through the optical fiber transmission line 2. The optical DQPSK decoder 3 on the receiving apparatus side first converts the received optical signal into a phase difference Θ (n) around one symbol, restores it to an electrical signal, and stores the difference data series b _I (n), b _Q ( n). In this optical DQPSK decoder 3, the optical signal absolute phase φ (n), the optical signal absolute phase φ (n−1) one symbol before, and the obtained phase difference Θ (n) (= φ (n) −φ (n− FIG. 5 shows the correspondence between 1)) and the difference data series b _I and b _Q.

  In a normal optical DQPSK communication system, when an optical signal generated by using a precoder circuit arranged on the transmission side is processed by an optical DQPSK decoder, the original input data series is restored by the processing for obtaining the above phase difference. On the other hand, even when the precoder circuit 4 is arranged at the subsequent stage of the optical DQPSK decoder 3 as in the configuration of FIG. 1, the difference data series corresponding to the phase difference and 1 held in the feedback register 42 in the precoder circuit 4. By adding the absolute phase of the optical signal before the symbol, the absolute phase of the optical signal, that is, the input data series is restored.

  However, in practice, the restored data series output from the precoder circuit 4 does not necessarily match the original input data series. This is because the optical DQPSK decoder 3 outputs only the phase difference, cannot detect the absolute phase of the optical signal, and the initial value of the feedback register 42 in the precoder circuit 4 matches the initial value of the optical signal absolute phase. Because there is no limit. Since there are four symbols (1 / 4π, 3 / 4π, 5 / 4π, 7 / 4π) in DQPSK, when the relationship between the initial values is uncertain, four patterns of restored data from the same differential data sequence There is a possibility of taking a series.

FIG. 6 shows an example of four restored data sequences resulting from the uncertainty of the initial value of the optical signal phase. The feedback register corresponding to the differential data series b _I (n), b _Q (n) and the optical signal absolute phase one symbol before in accordance with the processing of the differential encoding calculation unit 41 shown in Expression (1) and Expression (2) The next symbols d _I (n) and d _Q (n) are calculated from the outputs d _I (n−1) and d _Q (n−1) of 42.

Usually, a frame synchronization pattern for finding a frame delimiter is added to a frame format of a data sequence used in optical communication. The frame synchronization circuit 5 detects a frame synchronization pattern from the restored data series d _I (n), d _Q (n).

The frame synchronization circuit 5 searches the frame synchronization pattern for a certain period of time, and if it cannot detect it, notifies the precoder circuit 4 of the phase designation signal. As shown in FIG. 3, the phase designation circuit 43 in the precoder circuit 4 rotates the phases of the outputs d _I (n−1) and d _Q (n−1) of the feedback register 42 to obtain d _I ′ (n− 1) and output as d _Q ′ (n−1) to the differential encoding operation unit 41.

In FIG. 3, the phase specifying circuit 43 normally uses the outputs d _I (n−1) and d _Q (n−1) of the feedback register 42 as they are, d _I ′ (n−1), d _Q ′ (n− Output as 1). When the phase designation signal is notified, the selectors 431 and 433 receive the logic inversion signal of d _I (n−1) by d _Q (n−1) and the inverter 432, respectively, d _I ′ (n−1), d Select to output as _Q ′ (n−1).

  FIG. 7 shows outputs and corresponding optical signal absolute phases when the inputs dI (n−1) and dQ (n−1) and the phase designation signal are notified to the phase designation circuit 43. The operation of the phase specifying circuit 43 corresponds to an operation of rotating the optical signal absolute phase by −1 / 2π.

  When the initial value of the feedback register 42 does not match the initial value of the optical signal absolute phase, the frame synchronization pattern 5 cannot find the frame synchronization pattern. At this time, the above-described four restoration patterns can be reproduced by rotating the phase by the phase designation circuit 43. When the data sequence is in the correct initial value, the frame synchronization circuit 5 detects the frame synchronization pattern. Therefore, the data sequence identical to the input data sequence can be obtained as the restored data sequence by stopping the phase designation signal. it can.

  As described above, by combining the precoder circuit 4 and the frame synchronization circuit 5 arranged in the subsequent stage so that the transmitted information sequence can be restored, in a system having a plurality of channel inputs on the transmission side such as a DQPSK communication system, Since there is no need to design the bit shift accurately with a transmission side device such as MUX, there is an effect that the DPQSK communication system can be configured at low cost.

Embodiment 2. FIG.
A receiving apparatus according to Embodiment 2 of the present invention will be described with reference to FIG. FIG. 8 is a diagram showing a configuration of a receiving apparatus according to Embodiment 2 of the present invention.

  In the first embodiment described above, the receiving apparatus has been described in which the precoder circuit 4 and the frame synchronization circuit 5 arranged in the subsequent stage are combined so that the transmitted information sequence can be restored. In the second embodiment, FIG. As shown in FIG. 4, a plurality of precoder circuits 4-1, 4-2, 4-3, and 4-4 that can specify different phases are provided, and the selector 6 outputs the output of the precoder circuit that is correctly frame-synchronized by the frame synchronization circuit 5 A. Even if it is selected, the same effect can be obtained.

  That is, the receiving apparatus according to the second embodiment of the present invention can specify a different phase from the optical DQPSK decoder 3, and a plurality of precoder circuits 4-1, 4-2, 4-3, 4-4 connected in parallel. And a frame synchronization circuit 5A for detecting the output of the precoder circuit in which frame synchronization is correctly achieved among a plurality of outputs of the plurality of precoder circuits 4-1 to 4-4, and a phase designation signal from the frame synchronization circuit 5A, A selector 6 is provided for selecting the output of the precoder circuit in which frame synchronization is correctly achieved.

  Note that, as the plurality of precoder circuits 4-1, 4-2, 4-3, and 4-4, the precoder circuit 4 illustrated in FIG. 2 and the precoder circuit 4A illustrated in FIG.

Embodiment 3 FIG.
A receiving apparatus according to Embodiment 3 of the present invention will be described with reference to FIG. FIG. 9 is a block diagram showing a configuration of an optical DQPSK communication system including a receiving apparatus according to Embodiment 3 of the present invention.

In the first embodiment described above, the receiving apparatus has been described in which the precoder circuit 4 and the frame synchronization circuit 5 arranged in the subsequent stage are combined so that the transmitted information series can be restored. In the third embodiment, FIG. The variable delay circuit 7 is added to the positive phase signal (b _I ) and the direct phase signal (b _Q ) between the optical DQPSK decoder 3 and the precoder circuit 4 as shown in FIG. With this configuration, the same effect as in the first embodiment can be obtained, and there is also an effect that correction can be made when the normal phase signal and the direct phase signal are shifted in the optical DQPSK communication system.

  That is, the receiving apparatus according to the third embodiment of the present invention is a four-phase differential encoding method, and corrects a deviation between a normal phase signal and an orthogonal phase signal input to the optical DQPSK decoder 3 and a precoder circuit described later. A variable delay circuit 7, a precoder circuit 4, and a frame synchronization circuit 5 are provided.

Embodiment 4 FIG.
A precoder circuit according to Embodiment 4 of the present invention will be described with reference to FIG. FIG. 10 is a diagram showing the configuration of the precoder circuit according to the fourth embodiment of the present invention.

  In the first embodiment described above, the receiving apparatus has been described in which the precoder circuit 4 and the frame synchronization circuit 5 arranged in the subsequent stage are combined so that the transmitted information sequence can be restored. As shown in FIG. 10, the precoder circuit 4A , The n-bit parallel differential encoding operation unit 41A is made to correspond to the parallel reception input after time division separation, and 1 bit of the parallel output is input to the feedback register 42, and the output is input to the phase designation circuit 43. The same effect can be obtained by inputting.

  In other words, the precoder circuit according to the fourth embodiment of the present invention adds an optical signal absolute phase of the next symbol by adding a phase difference to the optical signal absolute phase of the previous symbol, and performs n-bit parallel differential encoding calculation. 41A, a feedback register 42 that delays one bit of the parallel output of the differential encoding operation unit 41A by one clock at the symbol rate, and an output of the feedback register 42 is output to the differential encoding operation unit 41A as it is. Alternatively, a phase designation circuit 43 that rotates the phase of the output of the feedback register 42 in accordance with a phase designation signal from the outside and outputs it to the differential encoding operation unit 41A is provided.

It is a block diagram which shows the structure of the optical DQPSK communication system containing the precoder circuit and receiver which concern on Embodiment 1 of this invention. It is a block diagram which shows the structure of the precoder circuit which concerns on Embodiment 1 of this invention. It is a figure which shows the structure of the phase designation circuit in the precoder circuit which concerns on Embodiment 1 of this invention. It is a figure which shows the mapping to the optical signal phase of the input data series by the optical DQPSK encoder. It is a figure which shows the relationship of the optical signal absolute phase, phase difference, and difference data series before and behind 1 symbol in an optical DQPSK decoder. It is a figure which shows the example of four types of data series resulting from the uncertainty of the initial value of an optical signal phase. It is a figure which shows the input / output relationship of a phase designation circuit. It is a figure which shows the structure of the receiver which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the optical DQPSK communication system containing the receiver which concerns on Embodiment 3 of this invention. It is a figure which shows the structure of the precoder circuit which concerns on Embodiment 4 of this invention. It is a figure which shows the structure of the conventional optical transmitter to which DQPSK system is applied.

Explanation of symbols

  1 optical DQPSK encoder, 2 optical fiber transmission line, 3 optical DQPSK decoder, 4 precoder circuit, 4A precoder circuit, 5 frame synchronization circuit, 5A frame synchronization circuit, 6 selector, 7 variable delay circuit, 41 differential encoding operation unit, 41A n-bit parallel differential encoding operation unit, 42 feedback register, 43 phase designation circuit, 431 selector, 432 inverter, 433 selector.

Claims (6)

A differential encoding calculation unit that calculates the optical signal absolute phase of the next symbol by adding the phase difference to the optical signal absolute phase of the previous symbol;
A feedback register that delays the output of the differential encoding operation unit by one clock at a symbol rate;
Output the feedback register as it is to the differential encoding operation unit, or according to an external phase specification signal, rotate the output phase of the feedback register and output to the differential encoding operation unit A precoder circuit characterized by comprising a circuit. An n-bit parallel differential encoding operation unit that calculates the optical signal absolute phase of the next symbol by adding the phase difference to the optical signal absolute phase of the previous symbol;
A feedback register that delays one bit of the parallel output of the differential encoding operation unit by one clock at a symbol rate;
Output the feedback register as it is to the differential encoding operation unit, or according to an external phase specification signal, rotate the output phase of the feedback register and output to the differential encoding operation unit A precoder circuit characterized by comprising a circuit. The precoder circuit according to claim 1, wherein the phase designation circuit has two inputs, outputs one input as it is, and inverts the other input for output. The precoder circuit according to claim 1, 2, or 3,
And a frame synchronization circuit that notifies a phase designation signal to the precoder circuit when a frame synchronization pattern cannot be detected from the output of the precoder circuit. The precoder circuit according to claim 1, 2, or 3, wherein different phases can be specified, and a plurality of precoder circuits connected in parallel;
A frame synchronization circuit that detects an output of a precoder circuit that is correctly frame-synchronized among a plurality of outputs of the plurality of precoder circuits;
A receiving device comprising: a selector that selects an output of a precoder circuit in which frame synchronization is correctly achieved in accordance with a phase designation signal from the frame synchronization circuit. 4 phase differential encoding system,
The receiving apparatus according to claim 4, further comprising a variable delay circuit that is arranged in a preceding stage of the precoder circuit and corrects a deviation between a normal phase signal and an orthogonal phase signal input to the precoder circuit.

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