JP2009295649A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow a constant film thickness distribution of an insulating film formed on a main surface of a semiconductor wafer. <P>SOLUTION: A gate electrode 6 is formed on a main surface of a semiconductor wafer 1 via a gate insulating film 4, and an insulating film 12 is formed as an interlayer insulating film to cover the gate electrode 6. Since an concave and convex shapes are formed on the insulating film 12 resulting from the gate electrode 6, the surface is flattened by CMP treatment. In the CMP treatment, the peripheral part 1A of the main surface of the semiconductor wafer 1 tends to be polished more when compared with a central portion 1B of the main surface. Therefore, on the main surface of the wafer 1, the film thickness distribution of the insulating film 12 is corrected by wet etching so that the thickness of the insulating film 12 is increased in a region where it is polished more than in a region where it is polished in small amount during CMP treatment. Then, the insulating film 12 is flattened by the CMP treatment. The film thickness at the peripheral part 1A of the insulating film 12 after CMP treatment is substantially similar to that of the central part 1B. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device manufacturing technique having a step of planarizing a film formed on a semiconductor wafer by CMP.

  A gate electrode is formed on a semiconductor substrate through a gate insulating film, a semiconductor region for source / drain is formed, an interlayer insulating film is formed so as to cover them, and this interlayer insulating film is then subjected to CMP processing. A plurality of wiring layers and interlayer insulating films are laminated on the interlayer insulating film to form a multilayer structure.

Japanese Unexamined Patent Application Publication No. 2007-189162 (Patent Document 1) describes a technique related to a process for uniformizing the film thickness distribution of an insulating film in a semiconductor wafer.
JP 2007-189162 A

  According to the study of the present inventor, the following has been found.

  When a lower layer pattern such as a gate electrode or a wiring pattern is formed on a semiconductor substrate and an interlayer insulating film is formed so as to cover the lower layer pattern, the upper surface of the interlayer insulating film is also uneven, reflecting the unevenness of the lower layer pattern. It will occur. If irregularities remain on the upper surface of the interlayer insulating film, the wiring layer formed on the interlayer insulating film may be adversely affected. For this reason, after flattening the upper surface of the interlayer insulating film reflecting the lower layer pattern by CMP, a contact hole is formed in the planarized interlayer insulating film, or on the planarized interlayer insulating film. Or forming a wiring layer.

  However, the polishing pressure during the CMP process depends on the lower layer pattern. Therefore, the peripheral portion of the main surface of the semiconductor wafer has a smaller pattern density of the gate electrode and the wiring pattern than the central portion of the main surface of the semiconductor wafer. Tend to be larger. When wafer edge rinsing and peripheral exposure are performed in order to avoid dust generation in the exposure apparatus, this tendency is further increased because there are no gate electrodes or wiring patterns in the peripheral portion of the main surface of the semiconductor wafer.

  With the miniaturization of gate electrodes and wiring patterns due to miniaturization and high integration of semiconductor devices, the film thickness of interlayer insulating films has also been reduced. However, as described above, if the polishing amount of the CMP process increases in the peripheral portion of the main surface of the semiconductor wafer, the lower layer pattern (gate electrode or wiring pattern) may be exposed from the interlayer insulating film, thereby causing a short circuit failure. May cause. This reduces the manufacturing yield of the semiconductor device. Since the peripheral portion of the main surface of the semiconductor wafer has a large number of chip acquisitions, the occurrence of defects in the peripheral portion of the main surface of the semiconductor wafer is caused by the defect rate in the entire semiconductor wafer (the semiconductor chip acquired from the entire semiconductor wafer). The ratio of defective chips to the total number) is greatly affected, and the manufacturing yield of the semiconductor device is greatly reduced.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, a pattern layer is formed on the main surface of a semiconductor wafer, an insulating film is formed so as to cover the pattern layer, and the insulating film is planarized by CMP processing. At this time, according to the distribution of the polishing amount of the insulating film in the semiconductor wafer during the CMP process, the insulating film is etched before the CMP process to correct the thickness distribution of the insulating film on the main surface of the semiconductor wafer, After the correction of the film thickness distribution, the upper surface of the insulating film is planarized by CMP.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The thickness distribution of the insulating film on the main surface of the semiconductor wafer can be made uniform.

  In addition, the manufacturing yield of the semiconductor device can be improved.

  Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.

  1. When referring to the name of a substance such as silicon, unless otherwise specified, it does not indicate only the indicated substance, but the indicated substance (element, atomic group, molecule, polymer, copolymer, compound, etc.) Including the main component and composition component.

  In other words, a silicon region or the like is a pure silicon region, a region containing silicon doped with impurities as a main component, or a mixture containing silicon as a main component such as GeSi, unless otherwise specified. Crystal region and the like. Further, “M” in the case of MIS is not limited to a pure metal unless explicitly stated otherwise, but is not limited to a pure metal, but includes a polysilicon (including amorphous) electrode, a silicide layer, and other metal-like properties. It shall include the member which shows. Further, “I” in the case of MIS is not limited to an oxide film such as a silicon oxide film unless otherwise specified, and is not limited to a nitride film, an oxynitride film, an alumina film, or other ordinary dielectrics, high dielectrics. Body, ferroelectric film and the like.

  2. A wafer is a silicon or other semiconductor single crystal substrate (generally a substantially disk shape, a semiconductor wafer, or other semiconductor chips or pellets obtained by dividing them into unit integrated circuit regions and a base region thereof) used in the manufacture of semiconductor integrated circuits, and a sapphire substrate. , Glass substrates, other insulating, anti-insulating or semiconductor substrates and the like and composite substrates thereof.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view or a perspective view may be hatched to make the drawing easy to see.

(Embodiment 1)
A manufacturing process of the semiconductor device of the present embodiment will be described with reference to the drawings.

  FIGS. 1 to 11 are cross-sectional views of a main part during a manufacturing process of a semiconductor device according to an embodiment of the present invention, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor).

  First, as shown in FIG. 1, a semiconductor wafer (wafer, semiconductor substrate) 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is prepared, and an element is formed on the main surface of the semiconductor wafer 1. An isolation region 2 is formed. The element isolation region 2 is made of an insulator such as silicon oxide, and can be formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method. By forming the element isolation region 2, an active region whose periphery is defined by the element isolation region 2 is formed on the main surface of the semiconductor wafer 1, and a MISFET QN described later is formed in this active region.

  Next, the p-type well 3 is formed from the main surface of the semiconductor wafer 1 to a predetermined depth. The p-type well 3 can be formed by ion-implanting a p-type impurity such as boron (B).

  Next, after cleaning the surface of the p-type well 3, a gate insulating film 4 is formed on the surface of the p-type well 3. The gate insulating film 4 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method. Alternatively, the gate insulating film 4 can be formed of a silicon oxynitride film. The gate insulating film 4 can also be formed of a so-called high-k insulating film (high dielectric constant film).

  Next, a conductive film (conductor film, conductive film) 5 is formed on the main surface of the semiconductor wafer 1 (that is, on the gate insulating film 4). The conductive film 5 is a conductive film for forming a gate electrode. The conductive film 5 can be formed of, for example, a low resistance polycrystalline silicon film (polycrystalline silicon film doped with impurities, doped polysilicon film). Then, the conductive film 5 is etched (dry etching) and patterned using a photoresist pattern (not shown) formed on the conductive film 5 as an etching mask. Thereby, as shown in FIG. 2, the gate electrode 6 made of the patterned conductive film 5 is formed on the gate insulating film 4 on the p-type well 3. Since the gate electrode 6 is composed of the patterned conductor film 5 (that is, a conductor film pattern), it can be regarded as a pattern layer formed on the main surface of the semiconductor wafer 1.

Next, as shown in FIG. 3, an n-type impurity such as phosphorus (P) or arsenic (As) is ion-implanted into the regions on both sides of the gate electrode 6 of the p-type well 3, thereby 3, an n ⁻ type semiconductor region 7 is formed. The n ⁻ type semiconductor region 7 is formed in self-alignment with the gate electrode 6.

  Next, sidewall spacers (sidewall spacers, sidewalls, sidewall insulating films) 8 made of, for example, silicon oxide or silicon nitride or a laminated film of these insulating films are formed on the sidewalls of the gate electrode 6. For example, the sidewall spacer 8 is formed by depositing a silicon oxide film, a silicon nitride film, or a laminated film thereof on the semiconductor substrate 1, and depositing the silicon oxide film, the silicon nitride film, or the laminated film by an RIE (Reactive Ion Etching) method. It can be formed by anisotropic etching (etchback) by, for example.

Next, using the sidewall spacer 8 as an ion implantation blocking mask, n-type impurities such as phosphorus (P) or arsenic (As) are formed in the regions on both sides of the gate electrode 6 and the sidewall spacer 8 of the p-type well 3. An n ⁺ type semiconductor region 9 (source, drain) is formed in the p-type well 3 by self-alignment with the sidewall spacer 8 by ion implantation or the like. The n ⁺ type semiconductor region 9 has a higher impurity concentration than the n ⁻ type semiconductor region 7. After ion implantation, annealing treatment (heat treatment) for activating the introduced impurities can be performed.

As a result, an n-type semiconductor region (impurity diffusion layer) that functions as a source or drain of the n-channel MISFET is formed by the n ⁺ -type semiconductor region (impurity diffusion layer) 9 and the n ⁻ -type semiconductor region 7. Therefore, the source / drain regions of the n-channel MISFET have an LDD (Lightly doped Drain) structure.

  In this manner, an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor) QN is formed in the p-type well 3, and the structure shown in FIG. 3 is obtained. Note that although the case where an n-channel MISFET is formed has been described in this embodiment, a p-channel MISFET can also be formed by reversing the n-type and p-type conductivity types. In addition, a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) can be formed by forming both an n-channel MISFET and a p-channel MISFET.

Next, as shown in FIG. 4, the surfaces of the gate electrode 6 and the n ⁺ type semiconductor region 9 are exposed, and a metal film such as a cobalt (Co) film or a nickel (Ni) film is deposited and heat-treated. As a result, metal silicide layers 10 (for example, a cobalt silicide layer or a nickel silicide layer) are formed on the surfaces of the gate electrode 6 and the n ⁺ type semiconductor region 9, respectively. Thereby, the diffusion resistance, contact resistance and the like of the n ⁺ type semiconductor region 9 can be reduced. Thereafter, the unreacted metal film (cobalt film or nickel film) is removed. FIG. 4 shows a state where the unreacted metal film is removed.

  Next, as shown in FIG. 5, an insulating film 11 and an insulating film (interlayer insulating film) 12 are sequentially formed (deposited) on the main surface of the semiconductor wafer 1 so as to cover the gate electrode 6 and the sidewall spacer 8. ) The insulating film 12 is an insulating film that is thicker than the insulating film 11 and functions as an interlayer insulating film. The insulating film 11 is an insulating film that is thinner than the insulating film 12 and functions as an etching stopper film when a contact hole 13 described later is formed in the insulating film 12. The insulating film 11 is made of, for example, a silicon nitride film, and the insulating film 12 on the insulating film 11 is made of, for example, a silicon oxide film, and can be formed by a CVD method or the like.

  The film thickness (deposited film thickness) of the insulating film 11 can be about 40 nm, for example, and the film thickness (deposited film thickness) t1 of the insulating film 12 can be about 800 to 900 nm, for example. After the insulating film 12 is deposited (formed), step S2, which will be described later, which is a process for correcting the film thickness distribution of the insulating film 12 deposited on the main surface of the semiconductor wafer 1, is performed. Step S3 described later is performed to planarize the upper surface of the insulating film 12 by a chemical mechanical polishing method. Thus, at the stage where the insulating film 12 is deposited, as shown in FIG. 5, the surface (upper surface) of the insulating film 12 is uneven due to the base step (here, the step due to the gate electrode 6 and the sidewall spacer 8). Although the shape is formed, as shown in FIG. 6, the surface (upper surface) of the insulating film 12 is polished and planarized by the CMP method. FIG. 5 shows a state after depositing the insulating film 12 and before performing a correction process of the film thickness distribution of the insulating film 12 in step S2 to be described later, and FIG. 6 shows a state in step S3 to be described later. A state in which the upper surface of the insulating film 12 is planarized by CMP processing is shown.

Next, as shown in FIG. 7, the insulating films 12 and 11 are dry-etched using a photoresist pattern (not shown) formed on the insulating film 12 by photolithography as an etching mask. Contact holes (openings, through holes) 13 are formed in the ⁺ type semiconductor region 9 (source, drain), the upper portion of the gate electrode 6 and the like. At this time, first, the insulating film 12 is dry-etched using the insulating film 11 as an etching stopper film to form a contact hole 13 in the insulating film 12, and then the insulating film 11 is dry-etched at the bottom of the contact hole 13. A contact hole 13 penetrating the insulating films 11 and 12 can be formed. Thereby, it is possible to prevent the substrate region (n ⁺ -type semiconductor region 9) from being damaged in the dry etching process for forming the contact hole 13. At the bottom of the contact hole 13 formed in the insulating films 12, 11, a part of the main surface of the semiconductor wafer 1, for example, a part of the n ⁺ type semiconductor region 9 (the metal silicide layer 10 on the surface thereof) or the gate electrode 6. A part of (the metal silicide layer 10 on the surface) is exposed.

  Next, a plug 14 is formed in the contact hole 13. In order to form the plug 14, for example, a conductive barrier film (for example, a laminated film of a titanium film and a titanium nitride film) 14 a is formed on the insulating film 12 including the inside of the contact hole 13, and then led by a tungsten film or the like. The body film 14b is formed by the CVD method or the like so as to fill the contact hole 13 on the conductive barrier film 14a. Then, the unnecessary main conductor film 14b and the conductive barrier film 14a on the insulating film 12 are removed by a CMP method or an etch back method, and the conductive barrier film 14a and the main conductor film 14b are left in the contact hole 13. Thereby, the plug 14 made of the conductive barrier film 14a and the main conductor film 14b remaining and buried in the contact hole 13 can be formed.

  Next, as shown in FIG. 8, a wiring 15 is formed on the insulating film 12 in which the plug 14 is embedded. For example, the wiring 15 is formed by sequentially forming a titanium film 15a, a titanium nitride film 15b, an aluminum film 15c, and a titanium nitride film 15d by sputtering and patterning using a photolithography method and a dry etching method. Can do. Since the wiring 15 is made of a patterned conductor film (here, a laminated film of a titanium film 15a, a titanium nitride film 15b, an aluminum film 15c, and a titanium nitride film 15d), a pattern layer formed on the main surface of the semiconductor wafer 1 Can be considered.

  Next, as shown in FIG. 9, an insulating film (interlayer insulating film) 16 is formed (deposited) on the main surface of the semiconductor wafer 1 (that is, on the insulating film 12) so as to cover the wiring 15. The insulating film 16 is an insulating film that functions as an interlayer insulating film, and is made of, for example, a silicon oxide film, and can be formed by a CVD method or the like. The film thickness (deposited film thickness) of the insulating film 16 can be about 800 nm, for example. 9 to 11 are cross-sectional views of the main part in the manufacturing process of the semiconductor device subsequent to FIG. Illustrations of structures below 12 are omitted.

  After the insulating film 16 is deposited (formed), step S2, which will be described later, which is a process for correcting the film thickness distribution of the insulating film 16 deposited on the main surface of the semiconductor wafer 1, will be described later. Step S3 to be described later for flattening the upper surface of the insulating film 16 is performed. As a result, at the stage where the insulating film 16 is deposited, as shown in FIG. 9, an uneven shape is formed on the surface (upper surface) of the insulating film 16 due to a base step (here, a step due to the wiring 15). However, as shown in FIG. 10, the surface (upper surface) of the insulating film 16 is polished and planarized by the CMP method. 9 shows a state after depositing the insulating film 16 and before performing a correction process for the film thickness distribution of the insulating film 16 in step S2 described later. FIG. 10 shows a state in step S3 described later. A state in which the upper surface of the insulating film 16 is planarized by CMP processing is shown.

  Next, as shown in FIG. 11, by using the photoresist pattern (not shown) formed on the insulating film 16 by photolithography as an etching mask, the insulating film 16 is dry-etched, so that the wiring 15 A through hole (opening, through hole) 17 is formed in the upper part. A part of the wiring 15 is exposed at the bottom of the through hole 17 formed in the insulating film 16.

  Next, the plug 18 is formed in the through hole 17. The plug 18 can be formed in the same manner as the plug 14.

  Thereafter, a wiring, an interlayer insulating film, and the like are further formed on the insulating film 16, but the description thereof is omitted here.

12 and 13 are cross-sectional views of the main part during the manufacturing process of the semiconductor device of the comparative example in which the process of step S2 described later is not performed unlike the present embodiment, and the peripheral part of the main surface of the semiconductor wafer 1 A cross-sectional view of the main part of (outer peripheral part) 1A and the central part 1B of the main surface of the semiconductor wafer 1 is shown. That is, the comparative example corresponds to a case where step S3 described later is performed after step S1 described later without performing step S2 described later. 12 is a cross-sectional view of the main part immediately after depositing the insulating film 12 (that is, the process step corresponding to FIG. 5 above), and FIG. 13 is just after the CMP process of the insulating film 12 (that is, in FIG. 6 above). It is principal part sectional drawing of the corresponding process step. 12 and 13, for simplification of the drawing, the p-type well 3, the n ⁻ -type semiconductor region 7 and the n ⁺ -type semiconductor region 9 are included in the semiconductor wafer 1 and are illustrated as sidewalls. The spacer 8, the metal silicide layer 10, and the insulating film 11 are not shown.

  FIG. 14 is a graph showing the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 in the manufacturing process of the semiconductor device of the comparative example. The horizontal axis of the graph in FIG. 14 corresponds to the distance from the center of the main surface of the semiconductor wafer 1 (the center of the main surface). Here, a case where a semiconductor wafer having a diameter of 300 mm is used as the semiconductor wafer 1 is described. For this reason, the position where the horizontal axis of the graph of FIG. 14 is 0 mm corresponds to the exact center of the main surface of the semiconductor wafer 1, and the position of the horizontal axis of the graph of FIG. , Outer peripheral edge, outermost periphery). In FIG. 24 described later, the position indicated by reference numeral 38 corresponds to the center of the main surface of the semiconductor wafer 1. Further, the peripheral portion (outer peripheral portion) 1A of the main surface of the semiconductor wafer 1 shown in FIGS. 12 and 13 is the end portion (wafer end, outer peripheral end, outermost periphery) of the semiconductor wafer 1 on the main surface of the semiconductor wafer 1. Corresponds to a region within approximately 5 mm (region where the horizontal axis of the graph of FIG. 14 is approximately 145 to 150 mm). A central portion 1B of the main surface of the semiconductor wafer 1 shown in FIGS. 12 and 13 is a region on the inner surface (side closer to the center of the semiconductor wafer 1) of the main surface of the semiconductor wafer 1 than the peripheral portion 1A (FIG. 14). The horizontal axis of the graph corresponds to a region of approximately 0 to 145 mm). Further, the vertical axis of the graph of FIG. 14 corresponds to the film thickness of the insulating film 12. In the graph of FIG. 14, the film thickness distribution of the insulating film 12 immediately after the insulating film 12 is deposited (that is, the process step corresponding to FIG. 12) is “just after deposition (FIG. 12)” in the graph of FIG. 14. And the film thickness distribution of the insulating film 12 immediately after the CMP process of the insulating film 12 (that is, the process stage corresponding to FIG. 13) (after the CMP process (FIG. 13) in the graph of FIG. 14). Are shown).

  As shown in FIG. 12, when the insulating film 12 is deposited on the main surface of the semiconductor wafer 1, an uneven shape is formed on the upper surface of the insulating film 12. In order to eliminate the uneven shape, the upper surface of the insulating film 12 is polished and planarized by CMP after the insulating film 12 is deposited. FIG. 13 shows a state in which the upper surface of the insulating film 12 is planarized by the CMP method.

  However, in the main surface of the semiconductor wafer 1, the peripheral portion 1A of the main surface of the semiconductor wafer 1 has a region (region where the gate electrode 6 is not formed) that is not used as a semiconductor chip. Compared with 1B), the pattern density of the gate electrode 6 is smaller. For this reason, in the peripheral portion 1A of the main surface of the semiconductor wafer 1, the polishing rate of the CMP process is rapidly increased and the polishing amount tends to be larger than the region other than the peripheral portion (central portion 1B). That is, there is a difference in the polishing amount during the CMP process between the peripheral portion 1A and the central portion 1B of the main surface of the semiconductor wafer 1.

  For this reason, unlike the present embodiment, in the case of the comparative example in which the process of step S2 described later is not performed, the thickness of the insulating film 12 after the CMP process of the insulating film 12 is as shown in FIG. The peripheral portion 1A of the main surface of the semiconductor wafer 1 is considerably thinner than the region other than the peripheral portion (central portion 1B). That is, as shown in the graph of FIG. 14, when the insulating film 12 is deposited, even if the thickness distribution of the deposited film thickness of the insulating film 12 on the main surface of the semiconductor wafer 1 is uniform, Since the distribution of the polishing amount during the CMP process is non-uniform on the surface, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 after the CMP process of the insulating film 12 becomes non-uniform.

If the film thickness distribution of the insulating film 12 after the CMP processing becomes non-uniform, here, the film thickness of the insulating film 12 after the CMP processing in the peripheral portion 1A of the main surface of the semiconductor wafer 1 is a region other than the peripheral portion (center If it is thinner than part 1B), the following problems may occur. That is, the gate electrode 6 may be exposed from the insulating film 12 subjected to the CMP process in the peripheral portion 1A of the main surface of the semiconductor wafer 1. This reduces the manufacturing yield of the semiconductor device. Etching at the time of forming the contact hole 13 is performed so that the contact hole 13 can be opened even at the thickest part of the insulating film 12, so that the peripheral portion 1 </ b> A of the main surface of the semiconductor wafer 1 with the thin insulating film 12 is formed. In this case, when the contact hole 13 is formed, over-etching occurs at the bottom of the contact hole 13 and the substrate region (n ⁺ type semiconductor region 9) is damaged, which may affect the gate characteristics of the MISFET QN. Even if the insulating film 11 is used as an etching stopper film when the contact hole 13 is opened, if the non-uniformity of the film thickness distribution of the insulating film 12 is high (the maximum film thickness portion and the minimum film thickness portion of the insulating film 12). In the region where the insulating film 12 is thin (peripheral portion 1A), the substrate region cannot be prevented from being damaged by over-etching at the bottom of the contact hole 13. This lowers the reliability of the semiconductor device and reduces the manufacturing yield of the semiconductor device.

  On the other hand, in the present embodiment, as shown in FIG. 15, after depositing (forming) the insulating film 12 on the main surface of the semiconductor wafer 1 in step S <b> 1, on the main surface of the semiconductor wafer 1 in step S <b> 2. In step S3, the insulating film 12 is subjected to CMP processing. After the step of depositing the insulating film 12 in step S1 and before the CMP process of the insulating film 12 in step S3, the film thickness distribution of the insulating film 12 is corrected in step S2, so that the insulating film 12 in step S3 is corrected. Even if the polishing amount distribution during the CMP process is not uniform, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 at the stage where the CMP process of the insulating film 12 in step S3 is performed is made uniform. be able to. FIG. 15 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of the present embodiment. The correction of the film thickness distribution of the insulating film 12 in step S2 will be described.

16 to 18 are main part cross-sectional views of the semiconductor device according to the present embodiment during the manufacturing process. The principal part sectional view of central part 1B is shown. FIG. 16 is a cross-sectional view of the main part immediately after depositing the insulating film 12 in step S1 (that is, the process stage corresponding to FIG. 5 above). FIG. 17 is a cross-sectional view of the main part immediately after the film thickness distribution of the insulating film 12 in step S2 is corrected after depositing the insulating film 12 (before the CMP process in step S3). FIG. 18 is a cross-sectional view of an essential part immediately after performing the CMP process on the insulating film 12 in step S3 after performing step S2 (that is, the process step corresponding to FIG. 6). 16 to 18, for the sake of simplification, the p-type well 3, the n ⁻ -type semiconductor region 7 and the n ⁺ -type semiconductor region 9 are included in the semiconductor wafer 1 and are illustrated as sidewalls. The spacer 8, the metal silicide layer 10, and the insulating film 11 are not shown.

  FIG. 19 is a graph showing the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 in the manufacturing process of the semiconductor device of the present embodiment. The horizontal axis of the graph of FIG. 19 corresponds to the distance from the center of the main surface of the semiconductor wafer 1 (the center of the main surface). In the present embodiment and the second embodiment to be described later, the case where a semiconductor wafer having a diameter of 300 mm is used as the semiconductor wafer 1 is graphed. For this reason, the position where the horizontal axis of the graph of FIG. 19 is 0 mm corresponds to the exact center of the main surface of the semiconductor wafer 1, and the position where the horizontal axis of the graph of FIG. , Outer peripheral edge, outermost periphery), which are other graphs of the present embodiment (FIGS. 20 to 22, FIG. 25, FIG. 26) and graphs of the second embodiment described later (FIGS. 30, 33). The same applies to. A peripheral portion (outer peripheral portion) 1 </ b> A of the main surface of the semiconductor wafer 1 shown in FIGS. 16 to 18 is approximately from the end portion (wafer end, outer peripheral end, outermost periphery) of the semiconductor wafer 1 on the main surface of the semiconductor wafer 1. It corresponds to an area within 5 mm (area where the horizontal axis of the graph of FIG. 19 is approximately 145 to 150 mm), and this is the same in the second embodiment. Further, the central portion 1B of the main surface of the semiconductor wafer 1 shown in FIGS. 16 to 18 is a region on the inner surface (side closer to the center of the semiconductor wafer 1) than the peripheral portion 1A on the main surface of the semiconductor wafer 1 ( The horizontal axis of the graph of FIG. 19 corresponds to a region of approximately 0 to 145 mm, and this is the same in the second embodiment below. Further, the vertical axis of the graph of FIG. 19 corresponds to the film thickness of the insulating film 12.

  In the graph of FIG. 19, the film thickness (thickness) t1 of the insulating film 12 immediately after depositing the insulating film 12 in step S1 (the process stage corresponding to FIGS. 5 and 16), and the insulating film 12 in step S2. The film thickness (thickness) t2 of the insulating film 12 immediately after the correction of the film thickness distribution (process step corresponding to FIG. 17) and immediately after the CMP process of the insulating film 12 in step S3 (FIGS. 6 and 18). The film thickness (thickness) t3 of the insulating film 12 in the corresponding process step) is shown. Here, the film thickness t1 shown in FIG. 5, FIG. 16 and FIG. 19 is the film thickness (that is, the deposited film thickness) immediately after depositing the insulating film 12 in step S1, that is, after step S1 and before step S2. ). 17 and 19 corresponds to the film thickness of the insulating film 12 immediately after the correction of the film thickness distribution of the insulating film 12 in step S2, that is, after step S2 and before step S3. . Further, the film thickness t3 shown in FIGS. 6, 18 and 19 corresponds to the film thickness of the insulating film 12 immediately after the insulating film 12 is subjected to the CMP process in step S3. Here, the insulating film 12 is formed on the main surface of the semiconductor wafer 1 so as to cover the pattern layer such as the gate electrode 6, but the film thicknesses t1, t2, and t3 (and in the second embodiment to be described later). The film thickness t4) is not the thickness on the pattern layer, but there is no pattern layer as can be seen from FIGS. 5, 6, 16 to 18 and FIGS. 28, 29, 31 and 32 described later. This corresponds to the thickness of the insulating film 12 at a portion (thickness in the direction perpendicular to the main surface of the semiconductor wafer 1).

  20 and 21 are graphs showing the etching amount of the insulating film 12 in step S2, and the distribution of the etching amount on the main surface of the semiconductor wafer 1 is shown. 20 and FIG. 21 corresponds to the distance from the center of the main surface of the semiconductor wafer 1 (the center of the main surface), and the vertical axis of the graphs of FIGS. 20 and 21 represents the insulating film in step S2. This corresponds to an etching amount of 12 (etching thickness, thickness removed by etching). 21 corresponds to an enlarged view of the region whose distance from the center of the semiconductor wafer 1 is 130 to 150 mm in the graph of FIG. Here, the etching amount of the insulating film 12 in step S2 is the difference between the film thickness t1 of the insulating film 12 before the etching process in step S2 and the film thickness t2 of the insulating film 12 after the etching process in step S2 (that is, corresponds to t2-t1). Therefore, for example, if the film thickness t1 of the insulating film 12 before step S2 is 850 nm and the film thickness t2 of the insulating film 12 after step S2 is 700 nm, the etching amount of the insulating film 12 in step S2 is 150 nm. If the thickness t1 of the insulating film 12 before step S2 is 850 nm and the thickness t2 of the insulating film 12 after step S2 is 830 nm, the etching amount of the insulating film 12 in step S2 is 20 nm.

  FIG. 22 is a graph showing the polishing amount of the insulating film 12 in step S <b> 3, and shows the distribution of the polishing amount on the main surface of the semiconductor wafer 1. The horizontal axis of the graph of FIG. 22 corresponds to the distance from the center (center of the main surface) of the main surface of the semiconductor wafer 1, and the vertical axis of the graph of FIG. 22 represents the polishing amount (polishing) of the insulating film 12 in step S3. Thickness, thickness polished by CMP treatment). Here, the polishing amount of the insulating film 12 in step S3 is the difference between the film thickness t2 of the insulating film 12 before the CMP process in step S3 and the film thickness t3 of the insulating film 12 after the CMP process in step S3 (that is, t2). -T3). Therefore, for example, if the thickness t2 of the insulating film 12 before step S3 is 700 nm and the thickness t3 of the insulating film 12 after step S3 is 400 nm, the polishing amount of the insulating film 12 in step S3 is 300 nm. If the thickness t2 of the insulating film 12 before step S3 is 850 nm and the thickness t3 of the insulating film 12 after step S3 is 400 nm, the polishing amount of the insulating film 12 in step S3 is 450 nm.

  As shown in FIG. 5 and FIG. 16, at the stage where the insulating film 12 is deposited on the main surface of the semiconductor wafer 1 in step S <b> 1, the insulating film 12 is caused by the step due to the gate electrode 6 and the sidewall spacer 8. Although an uneven shape is formed on the upper surface, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 is substantially uniform. That is, as shown in FIG. 16, the deposited film thickness (that is, the film thickness t1) of the insulating film 12 in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region (central portion 1B) other than the peripheral portion is It is almost the same. Therefore, the film thickness distribution of the insulating film 12 immediately after depositing the insulating film 12 in step S1 is substantially constant regardless of the position of the main surface of the semiconductor wafer 1, and in the graph of FIG. The film thickness t1 which is the film thickness is substantially constant regardless of the distance from the center of the main surface of the semiconductor wafer 1.

  However, as shown in the graph of FIG. 22, the distribution of the polishing amount of the insulating film 12 in step S3 (distribution on the main surface of the semiconductor wafer 1) is not uniform, and the peripheral portion 1A of the main surface of the semiconductor wafer 1 is The amount of polishing of the insulating film 12 during the CMP process in step S3 is larger (larger) than in the region other than the peripheral portion (the central portion 1B of the main surface of the semiconductor wafer 1). The reason is the same as that described with reference to FIGS. For this reason, when the CMP process of the insulating film 12 is performed in a state where the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 is uniform as in the comparative example described with reference to FIGS. The film thickness distribution of the insulating film 12 after the CMP process becomes non-uniform as shown in FIGS.

  For this reason, in the present embodiment, during the CMP process in step S3, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 after the CMP process of the insulating film 12 in step S3 is made uniform. In consideration of the non-uniform distribution of the polishing amount, the film thickness distribution of the insulating film 12 is corrected in advance in step S2. Specifically, as can be seen by comparing the graph of FIG. 19 and the graph of FIG. 22, the region of the main surface of the semiconductor wafer 1 where the polishing amount of the insulating film 12 in step S3 is small (the main surface of the semiconductor wafer 1). In a region where the polishing amount of the insulating film 12 in step S3 is larger (peripheral portion 1A on the main surface of the semiconductor wafer 1) than in the region other than the peripheral portion 1A, the central portion 1B), the film thickness t2 of the insulating film 12 is In step S2, the film thickness distribution of the insulating film 12 is corrected so as to increase the thickness.

  In order to realize this, as can be seen by comparing the graph of FIG. 22 with the graphs of FIG. 20 and FIG. 21, the polishing amount of the insulating film 12 during the CMP process of step S3 is small on the main surface of the semiconductor wafer 1. The region (peripheral portion 1A) in which the polishing amount of the insulating film 12 during the CMP process in step S3 is larger than the region (region other than the peripheral portion 1A, the central portion 1B) is reduced in the etching amount in step S2. In step S2, the insulating film 12 is etched. For this purpose, the etching amount is substantially proportional to the etching time. Therefore, in the main surface of the semiconductor wafer 1, a region where the polishing amount of the insulating film 12 during the CMP process in step S3 is small (a region other than the peripheral portion 1A, the central portion 1B). ), The insulating film 12 may be etched in step S2 so that the etching time in step S2 is shortened in the region (peripheral portion 1A) where the polishing amount of the insulating film 12 during the CMP process in step S3 is large. . As a result, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 is corrected in step S2, and the corrected film thickness distribution of the insulating film 12 (distribution of the film thickness t2) is corrected on the main surface of the semiconductor wafer 1. A region (peripheral area) in which the polishing amount of the insulating film 12 during the CMP process in step S3 is larger than a region where the polishing amount of the insulating film 12 during the CMP process in step S3 is small (a region other than the peripheral portion 1A, the central portion 1B). In part 1A), the thickness t2 of the insulating film 12 is increased.

  Further, as described above, the peripheral portion 1A of the main surface of the semiconductor wafer 1 has a larger amount of polishing of the insulating film 12 during the CMP process in step S3 than the region other than the peripheral portion (central portion 1B). Step S2 is performed so that the film thickness t2 of the insulating film 12 in the peripheral portion 1A of the main surface of the semiconductor wafer 1 is thicker than the film thickness t2 of the insulating film 12 in the region other than the peripheral portion 1A (central portion 1B). Thus, the film thickness distribution of the insulating film 12 is corrected. That is, in step S2, the etching amount of the insulating film 12 in the peripheral portion 1A of the main surface of the semiconductor wafer 1 is such that the insulating film 12 in the region other than the peripheral portion 1A of the main surface of the semiconductor wafer 1 (central portion 1B). The insulating film 12 is etched so as to be smaller than the etching amount. For this purpose, in step S2, the etching time of the insulating film 12 in the peripheral portion 1A of the main surface of the semiconductor wafer 1 is the insulating film in the region other than the peripheral portion 1A of the main surface of the semiconductor wafer 1 (central portion 1B). The insulating film 12 may be etched so as to be shorter than the etching time of 12.

  Step S2 is performed by wet etching as will be described later. By performing step S2, as can be seen from the graph of FIG. 19 and the cross-sectional view of FIG. 17, the film thickness t2 of the insulating film 12 in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 is a region other than the peripheral portion ( It becomes thicker than the film thickness t2 of the insulating film 12 in the central part 1B). That is, the difference (film thickness difference) between the film thickness t2 of the insulating film 12 in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the film thickness t2 of the insulating film 12 in the region other than the peripheral portion (central portion 1B). If td1, td1> 0. The film thickness difference td1 can be set to, for example, about 30 to 250 nm.

  After step S2, when the upper surface of the insulating film 12 is polished by CMP in step S3, the peripheral portion 1A of the main surface of the semiconductor wafer 1 is compared with the region other than the peripheral portion (central portion 1B) as shown in FIG. However, in this embodiment, the thickness distribution of the insulating film 12 immediately before the CMP process is larger in the polishing amount in the CMP process than in the case where the polishing amount in the CMP process is small. As the number increases, the correction is made in step S2 so that the insulating film 12 becomes thicker. For this reason, in the CMP process in step S3, a large amount of polishing is performed in a region where the film thickness t2 of the insulating film 12 is thick, and a small amount of polishing is performed in a region where the film thickness t2 of the insulating film 12 is thin. The film thickness t3 (the film thickness distribution) of the subsequent insulating film 12 is uniform on the main surface 1a of the semiconductor wafer 1. That is, the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 is thicker than the region (central portion 1B) other than the peripheral portion, and the thickness t2 of the insulating film 12 is larger. Since the polishing amount is large, the film thickness t3 of the insulating film 12 after the CMP process is substantially the same in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region other than the peripheral portion (central portion 1B). Note that the thickness t3 of the insulating film 12 after the CMP process in step S3 is thicker than the height of the gate electrode 6, and the gate electrode 6 is not exposed from the insulating film 12 subjected to the CMP process in step S3.

Therefore, as shown in the cross-sectional view of FIG. 18, the insulating film 12 after the CMP process in step S3 is performed between the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the central portion 1B of the main surface 1a of the semiconductor wafer 1. As shown in the graph of FIG. 19, the film thickness t3 of the insulating film 12 after the CMP process in step S3 depends on the distance from the center of the main surface 1a of the semiconductor wafer 1. However, it can be set to a substantially constant value. That is, the film thickness distribution of the insulating film 12 after the CMP process in step S3 is uniform on the main surface 1a of the semiconductor wafer 1, and the film thickness t3 of the insulating film 12 after the CMP process is equal to that of the main surface 1a of the semiconductor wafer 1. It can be made almost constant regardless of the position. Thereby, even if the insulating film 12 is subjected to the CMP process, the gate electrode 6 can be prevented from being exposed from the insulating film 12 in the peripheral portion 1A of the main surface of the semiconductor wafer 1. For this reason, the manufacturing yield of the semiconductor device can be improved. Further, it is possible to prevent the substrate region (n ⁺ type semiconductor region 9) from being damaged due to over-etching at the bottom of the contact hole 13 when the contact hole 13 is formed. Therefore, the reliability of the semiconductor device can be improved. In addition, the manufacturing yield of the semiconductor device can be improved.

  As can be seen from the graph of FIG. 19, step S2 is a process for making the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 non-uniform, and the film thickness t2 of the insulating film 12 after step S2. Is non-uniform compared to the film thickness distribution (distribution of film thickness t1) of the insulating film 12 when the insulating film 12 is deposited. That is, by performing step S2, the film thickness of the insulating film 12 in the peripheral portion 1A of the main surface of the semiconductor wafer 1 and the portions other than the peripheral portion 1A of the main surface of the semiconductor wafer 1 are compared with those before performing step S2. The difference from the film thickness of the insulating film 12 in the region (central portion 1B) increases. In other words, the film thickness difference (corresponding to the film thickness difference td1) between the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region (central portion 1B) other than the peripheral portion is the step S2. This is larger after step S2 than before.

  In the present embodiment, considering the non-uniformity of the polishing amount distribution during the CMP process, the process of step S2 for making the film thickness distribution of the insulating film 12 non-uniform is performed before the CMP process. Thus, the film thickness distribution (distribution of the film thickness t3) of the insulating film 12 after the CMP process is made uniform. That is, by performing the CMP process in step S3, the film thickness t3 of the insulating film in the peripheral portion 1A of the main surface of the semiconductor wafer 1 compared to before the CMP process in step S3 (but after step S2), The difference from the film thickness t3 of the insulating film 12 in the region (central portion 1B) other than the peripheral portion 1A of the main surface of the semiconductor wafer 1 becomes small. In other words, the film thickness difference (corresponding to the film thickness difference td1) between the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region (central portion 1B) other than the peripheral portion is the step S3. This is smaller after performing step S3 than before performing (but after step S2).

  Specifically, step S2 can be performed as follows.

  FIG. 23 and FIG. 24 are explanatory diagrams of the processing in step S2 (processing for correcting the film thickness distribution of the insulating film 12 deposited on the main surface of the semiconductor wafer 1) performed in the present embodiment. Is a cross-sectional view, and FIG. 24 is a plan view (top view).

  In the present embodiment, as shown in FIG. 23, a part (upper layer part) of the insulating film 12 is wet-etched using a single-wafer type wet etching apparatus 31, whereby the film of the insulating film 12 in step S2. Processing to correct the thickness distribution is performed. In step S2, as described above, the amount of polishing during the CMP process is made uniform so that the film thickness distribution of the insulating film 12 on the main surface 1a of the semiconductor wafer 1 after the CMP process of the insulating film 12 is made uniform. This is processing for correcting the film thickness distribution of the insulating film 12 in advance in consideration of non-uniform distribution. That is, in step S2, the amount of wet etching of the insulating film 12 is reduced where the amount of polishing during the CMP process in step S3 is large compared to where the amount of polishing during the CMP process in step S3 is small (ie, In this process, the insulating film 12 is wet etched so that the wet etching time is shortened, and the film thickness distribution of the insulating film 12 on the main surface 1a of the semiconductor wafer 1 is corrected. By correcting the film thickness distribution of the insulating film 12 on the main surface 1a of the semiconductor wafer 1 in step S2, the insulating film 12 on the main surface 1a of the semiconductor wafer 1 at the stage where the insulating film 12 is subjected to CMP processing in step S3. The film thickness distribution becomes uniform.

  As shown in FIG. 23, the wet etching apparatus 31 includes a rotary stage (wafer rotary stage, spin base) 32 and a wafer chuck 33 fixed and coupled to the outer peripheral portion of the rotary stage 32. The rotating stage 32 is a rotating plate configured to be rotated at a high speed by a rotating mechanism (for example, a motor) (not shown), and has a larger diameter than the semiconductor wafer 1, for example. The wafer chuck 33 is configured to be capable of holding the semiconductor wafer 1, and a main surface (surface, main surface on the semiconductor element formation side) 1 a that is a surface on which the insulating film 12 of the semiconductor wafer 1 is formed is upward. The semiconductor wafer 1 is held so that the back surface, which is the surface opposite to the main surface 1a, faces downward. By rotating the rotary stage 32 by a rotation mechanism (not shown), the wafer chuck 33 and the semiconductor wafer 1 held by the wafer chuck 33 can also be rotated.

  Above the rotary stage 32, here, above the central portion of the main surface 1a of the semiconductor wafer 1 fixed to the rotary stage 32 by the wafer chuck 33, a nozzle (etching liquid and rinsing liquid) that is used for both the etching liquid and the rinsing liquid. (Supplying part, etching liquid and rinsing liquid supply means) 34 are arranged. Then, the etching liquid 37 or the rinsing liquid 35 is discharged (spouted) from the nozzle 34 toward the main surface 1 a of the semiconductor wafer 1, and the etching liquid 37 or the rinsing liquid 35 can be supplied to the main surface 1 a of the semiconductor wafer 1. Has been.

As the etching solution 37, an etching solution capable of etching the insulating film 12 formed on the main surface 1a of the semiconductor wafer 1 is used. For example, an aqueous solution of hydrofluoric acid (HF) can be used. The concentration of hydrofluoric acid in the etching solution 37 may be set so that a target etching amount can be secured within an etching time that does not hinder productivity in a single-wafer wet etching apparatus. The concentration of hydrofluoric acid in the etching solution 37 is, for example, about 50% HF: H ₂ O = 1: 100, for example, 20 seconds if an etching amount of about 1.5 nm in terms of a thermal oxide film is aimed for 30 seconds. If an etching amount of about 5 nm in terms of a thermal oxide film is aimed, it can be thinned to about 50% HF: H ₂ O = 1: 20. For example, the temperature of the etching solution 37 discharged from the nozzle 34 can be set to about 24 ° C. in the case of hydrofluoric acid. Further, the flow rate of the etching solution 37 discharged from the nozzle 34 can be set to, for example, about 2 L / min as a flow rate that quickly spreads over the entire surface of the wafer. As the rinse liquid 35 supplied from the nozzle 34, for example, pure water can be used. In addition, the configuration is such that the supply of the etching solution 37 or the rinsing solution 35 from the nozzle 34 can be started, stopped, and switched (or the supply (discharge) amount can be adjusted) by a valve (not shown). Has been.

  Further, a rinsing liquid nozzle (rinsing liquid supply unit, rinsing liquid supply means) 36 is disposed above the rotary stage 32, and the rinsing liquid (cleaning liquid, rinsing liquid) 35 is supplied from the rinsing liquid nozzle 36 to the main part of the semiconductor wafer 1. The rinsing liquid 35 can be supplied to the main surface 1a of the semiconductor wafer 1 by discharging (spouting and supplying) toward the surface 1a. As the rinse liquid 35 discharged from the rinse liquid nozzle 36, for example, pure water can be used. The flow rate of the rinsing liquid 35 that is discharged from the rinsing liquid nozzle 36 and supplied onto the main surface 1a of the semiconductor wafer 1 is, for example, about 0.2 L / min as a flow rate that can suppress rebound from the wafer chuck 33. Can do. Further, the supply (discharge) amount of the rinsing liquid 35 can be switched (or the supply (discharge) amount of the rinsing liquid 35 can be adjusted) by using a valve (not shown) or the like. Has been.

  The nozzle 34 and the rinsing liquid nozzle 36 and the piping (not shown) for supplying the etching liquid 37 and the rinsing liquid 35 to them are not fixed to the rotary stage 32, and even if the rotary stage 32 rotates, the nozzle 34. The rinsing liquid nozzle 36 is configured not to rotate.

  The rinsing liquid nozzle 36 extends horizontally above the rotary stage 32 from a position above the peripheral portion (outer peripheral portion) of the main surface 1 a of the semiconductor wafer 1 to a position above the center portion of the main surface 1 a of the semiconductor wafer 1. It is configured to be movable in the direction parallel to the main surface 1a of the rotary stage 32 and the semiconductor wafer 1 held there. The moving speed of the rinsing liquid nozzle 36 can be controlled to a desired speed.

  Next, the specific procedure of step S2 will be described.

  First, the semiconductor wafer 1 having the insulating film 12 deposited on the main surface 1a is held on the rotary stage 32 of the etching apparatus 31 by the wafer chuck 33 as shown in FIG. Then, by rotating the rotary stage 32, the semiconductor wafer 1 held on the rotary stage 32 is rotated. At this time, the center of rotation of the rotary stage 32 substantially coincides with the center position of the main surface 1a of the semiconductor wafer 1, so that the semiconductor wafer 1 rotates with the center position of the main surface 1a as the center of rotation. The rotation speed of the semiconductor wafer 1 can be set to, for example, about 500 rpm (500 rotations / minute).

  In a state where the semiconductor wafer 1 is rotated, an etching solution 37 for etching the insulating film 12 is supplied from the nozzle 34 to the main surface 1 a of the rotating semiconductor wafer 1, and then the main surface of the semiconductor wafer 1 from the rinse solution nozzle 36. While supplying a rinsing liquid 35 for stopping the etching of the insulating film 12 to 1a, the rinsing liquid nozzle 36 is placed above the main surface 1a of the rotating semiconductor wafer 1 and the peripheral portion (outer periphery) of the main surface 1a of the semiconductor wafer 1 is rotated. Part) from the side to the center side. That is, the rinsing liquid nozzle 36 that discharges the rinsing liquid 35 toward the main surface 1a of the semiconductor wafer 1 is moved in the direction indicated by the arrow 39 in FIGS. 23 and 24 (from the peripheral portion side of the main surface 1a of the semiconductor wafer 1). In the direction toward the center side). Here, FIG. 24 shows the upper surface (main surface 1 a) of the rotating semiconductor wafer 1, and the position indicated by reference numeral 38 in FIG. 24 corresponds to the center of the main surface 1 a of the semiconductor wafer 1. .

  More specifically, first, in a state where the semiconductor wafer 1 is rotated, an etching solution is applied from the nozzle 34 located above the central portion of the main surface 1a of the semiconductor wafer 1 to the central portion of the main surface 1a of the rotating semiconductor wafer 1. 37 is supplied. Since the semiconductor wafer 1 is rotating, the etching solution 37 supplied from the nozzle 34 to the central portion of the main surface 1a of the semiconductor wafer 1 is from the central portion of the main surface 1a of the semiconductor wafer 1 to the peripheral portion (outer peripheral portion) side. Then, the etching solution 37 spreads over the entire main surface 1a of the semiconductor wafer 1, and the etching of the insulating film 12 with the etching solution 37 is started over the entire main surface 1a of the semiconductor wafer 1.

  After supplying the etching solution 37 from the nozzle 34 to the central portion of the main surface 1a of the rotating semiconductor wafer 1 for a predetermined time, the supply of the etching solution 37 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is stopped. Then, the rotation speed of the semiconductor wafer 1 is reduced to, for example, about 100 rpm (100 rotations / minute). Then, in a state where the semiconductor wafer 1 is rotated, discharge of the rinse liquid 35 from the rinse liquid nozzle 36 is started, and the rinse liquid nozzle 36 for discharging the rinse liquid 35 is moved to the main surface 1 a of the rotating semiconductor wafer 1. It is moved in a horizontal direction (a direction parallel to the main surface 1a of the semiconductor wafer 1 held on the rotary stage 32) from a position above the peripheral portion to a position above the central portion of the main surface 1a of the semiconductor wafer 1. Thus, the rinsing liquid 35 is supplied from the rinsing liquid nozzle 36 to the main surface 1 a of the semiconductor wafer 1, and the rinsing process of the main surface 1 a of the semiconductor wafer 1 is performed by the rinsing liquid 35 supplied to the main surface 1 a of the semiconductor wafer 1. (Rinse processing) is performed, the etching solution 37 is removed from the main surface 1a of the semiconductor wafer 1 together with the rinsing solution 35, and the etching of the insulating film 12 on the main surface 1a of the semiconductor wafer 1 is stopped. Since the rinsing liquid nozzle 36 moves while supplying the rinsing liquid 35 to the main surface 1 a of the semiconductor wafer 1, the position where the rinsing liquid 35 is supplied to the main surface 1 a of the semiconductor wafer 1 is located on the semiconductor wafer 1. It moves from the peripheral part of the main surface 1a to the central part of the main surface 1a of the semiconductor wafer 1.

  The position where the rinsing liquid nozzle 36 reaches a position above the central portion of the main surface 1 a of the rotating semiconductor wafer 1 and the rinsing liquid 35 is supplied from the rinsing liquid nozzle 36 to the main surface 1 a of the semiconductor wafer 1. After moving from the peripheral portion (outer peripheral portion) of the main surface 1a of the semiconductor wafer 1 to the center portion of the main surface 1a of the semiconductor wafer 1, the rinse liquid 35 from the rinse liquid nozzle 36 to the main surface 1a of the semiconductor wafer 1 is transferred. Stop supplying. Then, a rinsing liquid 35 is supplied from the nozzle 34 located above the central portion of the main surface 1 a of the semiconductor wafer 1 to the central portion of the main surface 1 a of the rotating semiconductor wafer 1.

  When supplying the rinsing liquid 35 from the nozzle 34 to the main surface 1 a of the semiconductor wafer 1, the rinsing liquid nozzle 36 is positioned above the center of the main surface 1 a of the rotating semiconductor wafer 1. The liquid nozzle 36 may get in the way. For this reason, after the supply of the rinsing liquid 35 from the rinsing liquid nozzle 36 is stopped, the rinsing liquid nozzle 36 is quickly moved from the position above the central portion of the main surface 1a of the rotating semiconductor wafer 1 to the peripheral portion side. It is more preferable that the supply of the rinsing liquid 35 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is started after the movement.

  Further, when the rinsing liquid nozzle 36 reaches a position above the central portion of the main surface 1a of the rotating semiconductor wafer 1 (the supply position of the rinsing liquid 35 from the rinsing liquid nozzle 36 is the main surface of the semiconductor wafer 1). Since the etching of the insulating film 12 is stopped on the entire main surface 1a of the semiconductor wafer 1 at the stage of moving to the center of 1a), as another form, the nozzle 34 is connected to the main surface 1a of the semiconductor wafer 1. The supply of the rinsing liquid 35 can be omitted. However, the rinsing liquid 35 may be supplied from the nozzle 34 to the central portion of the main surface 1a of the rotating semiconductor wafer 1 so that the rinsing process is more reliably performed on the entire main surface 1a of the semiconductor wafer 1. More preferable.

  After the rinsing process, the discharge of the rinsing liquid 35 from the nozzle 34 is stopped, and the supply of the rinsing liquid 35 to the main surface 1a of the semiconductor wafer 1 is completed. Then, by increasing the rotation speed of the rotary stage 32, the rotation speed of the semiconductor wafer 1 is increased, the semiconductor wafer 1 is rotated at a high speed, and the centrifugal force generated by the high-speed rotation is used on the main surface 1a of the semiconductor wafer 1. The remaining liquid or moisture (rinse liquid) is shaken off, and the semiconductor wafer 1 is dried. After the semiconductor wafer 1 is dried at a high speed for a predetermined time, the rotation of the semiconductor wafer 1 is stopped (the rotation of the rotary stage 32 is stopped).

  Thereafter, the semiconductor wafer 1 is sent to the next process (CMP process of the insulating film 12 in step S3) or is temporarily stored in a storage case or the like before that.

  As described above, the etching solution 37 is supplied to the central portion of the main surface 1a of the semiconductor wafer 1 from the nozzle 34 located above the central portion of the main surface 1a of the semiconductor wafer 1 while the semiconductor wafer 1 is rotated. Thus, the etching solution 37 is spread over the entire main surface 1 a of the semiconductor wafer 1, and the etching of the insulating film 12 formed on the main surface 1 a of the semiconductor wafer 1 can be started by this etching solution 37. Since the semiconductor wafer 1 is rotating, the etching solution 37 supplied to the central portion of the main surface 1 a of the semiconductor wafer 1 quickly reaches the entire main surface 1 a of the semiconductor wafer 1, and therefore the main surface 1 a of the semiconductor wafer 1. At each of these positions, etching of the insulating film 12 with the etching solution 37 is started almost simultaneously.

  If the rotation speed of the semiconductor wafer 1 is too high, the etching solution 37 is shaken off from the main surface 1a of the semiconductor wafer 1 by the centrifugal force caused by the high-speed rotation and is completely removed, but the etching solution is removed from the main surface 1a of the semiconductor wafer 1. The rotational speed of the semiconductor wafer 1 is controlled so that a predetermined amount of the etching solution 37 can remain on the entire main surface 1a of the semiconductor wafer 1 without being completely removed. Thereby, even after the supply of the etching solution 37 from the nozzle 34 to the main surface 1 a of the semiconductor wafer 1 is stopped, the etching solution 37 remaining on the main surface 1 a of the semiconductor wafer 1 is formed on the main surface 1 a of the semiconductor wafer 1. Etching of the insulating film 12 that has been performed proceeds.

  After the supply of the etching liquid 37 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is stopped, the rinsing liquid 35 is discharged from the rinsing liquid nozzle 36 while the semiconductor wafer 1 is rotated as described above. The rinsing liquid nozzle 36 is moved in the horizontal direction from a position above the periphery of the main surface 1 a of the rotating semiconductor wafer 1 to a position above the center of the main surface 1 a of the semiconductor wafer 1. Since the semiconductor wafer 1 is rotating, the rinsing liquid 35 supplied from the rinsing liquid nozzle 36 onto the main surface 1 a of the semiconductor wafer 1 moves on the main surface 1 a of the semiconductor wafer 1 to the peripheral side. For this reason, on the main surface 1 a of the semiconductor wafer 1, the rinsing liquid 35 is spread (existing) from the position where the rinsing liquid 35 is supplied from the rinsing liquid nozzle 36 to the outer side (outer peripheral side). The rinsing process) is performed, the etching solution 37 is removed together with the rinsing solution 35, and the etching (wet etching) of the insulating film 12 is stopped.

  At each position of the main surface 1 a of the semiconductor wafer 1, the etching of the insulating film 12 is started almost simultaneously by the etching liquid 37 supplied from the nozzle 34, but the rinsing liquid nozzle 36 that discharges the rinsing liquid 35 is rotated. Since the semiconductor wafer 1 moves in the horizontal direction from the position above the peripheral portion of the main surface 1a of the semiconductor wafer 1 to the position above the central portion of the main surface 1a of the semiconductor wafer 1, the start time of the rinsing process with the rinsing liquid 35 is It differs at each position on the main surface 1 a of the wafer 1. At each position of the main surface 1 a of the semiconductor wafer 1, the etching solution 37 supplied from the nozzle 34 touches (wettes), and then the rinsing solution 35 supplied from the rinsing solution nozzle 36 touches (wettes). ) Until the etching of the insulating film 12 proceeds. For this reason, the rinsing liquid nozzle 36 has only to be moved once from the peripheral side to the central side on the main surface 1a of the semiconductor wafer 1, and the processing operation of step S2 can be simplified. The time required can be shortened. The etching time at each position on the main surface of the semiconductor wafer 1 in step S2 is the time from the start of the supply of the etching solution 37 from the nozzle 34 until the rinsing solution nozzle 36 passes over each position. Will respond.

  In the present embodiment, in step S2, where the polishing amount during the CMP process in step S3 increases (peripheral portion 1A), the polishing amount during the CMP process in step S3 decreases (regions other than the peripheral portion, The movement (movement speed) of the rinsing liquid nozzle 36 is controlled so that the etching amount of the insulating film 12 is smaller than that of the central portion 1B) (that is, the etching time of the insulating film 12 is shortened). The control of the movement (movement speed) of the rinsing liquid nozzle 36 will be described in more detail.

  FIG. 25 is a graph showing the moving position of the rinsing liquid nozzle 36 in step S2, that is, the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 comes into contact with the main surface 1a of the semiconductor wafer 1. In step S2, the position of the rinsing liquid nozzle 36 (that is, the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 comes into contact with the main surface 1a of the semiconductor wafer 1) is moved to the position shown in FIG. Control to be. The horizontal axis of the graph of FIG. 25 shows the position (the center of the liquid contact) where the rinsing liquid 35 supplied from the rinsing liquid nozzle 36 contacts the main surface 1 a of the semiconductor wafer 1 and the main surface 1 a of the semiconductor wafer 1. Corresponds to the distance to the center. The vertical axis of the graph in FIG. 25 corresponds to time (time), but the direction toward the upper side of the vertical axis is the direction in which time elapses, and is indicated in arbitrary units (arb. Unit: arbitrary unit). FIG. 26 is a graph showing the etching time of the insulating film 12 at each position on the main surface 1a of the semiconductor wafer 1 in step S2. The horizontal axis of the graph in FIG. 26 corresponds to the distance from the center (center of the main surface) of the main surface 1a of the semiconductor wafer 1, and the vertical axis of the graph in FIG. 26 corresponds to the etching time.

  In step S2, the etching amount (etching thickness) of the insulating film 12 at each position on the main surface 1a of the semiconductor wafer 1 is proportional to the etching time at each position. As described above, the amount of polishing during the CMP process is larger in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 than in the region other than the peripheral portion (central portion 1B). Regarding the amount, it is necessary to reduce the etching amount in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 as compared with the etching amount in the region other than the peripheral portion (central portion 1B). That is, with respect to the etching time in step S2, the etching time in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 needs to be shorter than the etching time in the region other than the peripheral portion (central portion 1B). .

  For this reason, in step S2, after supplying the etching solution 37 from the nozzle 34 to the central portion of the main surface 1a of the rotating semiconductor wafer 1 for a predetermined time, the supply of the etching solution 37 from the nozzle 34 is stopped, and then With the rinsing liquid nozzle 36 stopped, the rinsing liquid 35 is moved from the rinsing liquid nozzle 36 to the periphery of the main surface 1a of the rotating semiconductor wafer 1 for a predetermined time (from time Tm2 to Tm3 in the graph of FIG. 25). Supply. After the rinsing liquid 35 is continuously supplied from the rinsing liquid nozzle 36 to the periphery of the main surface 1a of the semiconductor wafer 1 for a predetermined time (from time Tm2 to Tm3), the rinsing liquid nozzle 36 discharges the rinsing liquid 35. From the position above the peripheral part (outer peripheral part) of the main surface 1a of the rotating semiconductor wafer 1 to the position above the central part of the main surface 1a of the semiconductor wafer 1 (held on the rotary stage 32 and there) It is moved in a direction parallel to the main surface 1a of the semiconductor wafer 1. That is, the rinsing liquid nozzle 36 is moved from the peripheral portion (outer peripheral portion) side of the main surface of the semiconductor wafer 1 to the central portion side in the direction of the arrow 39 in FIGS. 23 and 24 above the rotating semiconductor wafer 1. is there.

  Here, the time when the supply of the etching solution 37 from the nozzle 34 to the central portion of the main surface 1a of the semiconductor wafer 1 starts corresponds to the time Tm1 in the graph of FIG. 25, the supply time of the rinsing liquid 35 from the rinsing liquid nozzle 36 to the peripheral portion of the main surface 1a of the semiconductor wafer 1 after the supply of the etching liquid 37 from the nozzle 34 is stopped is shown in the graph of FIG. This corresponds to time Tm2. Further, the movement of the rinsing liquid nozzle 36 for discharging the rinsing liquid 35 (movement from a position above the peripheral portion of the main surface 1a of the semiconductor wafer 1 to a position above the central portion of the main surface 1a of the semiconductor wafer 1). The start time corresponds to time Tm3 in the graph of FIG. 25, and the time at which the rinsing liquid nozzle 36 that discharges the rinsing liquid 35 reaches a position above the center of the main surface 1a of the semiconductor wafer 1 is shown in FIG. Corresponds to time Tm4 in the graph. Accordingly, the rinsing liquid nozzle 36 discharges the rinsing liquid 35 from time Tm2 to time Tm4 (or until a predetermined time elapses after time Tm4), but from time Tm2 to time Tm3, The rinse liquid nozzle 36 is stopped at a position above the peripheral portion of the main surface 1 a of the semiconductor wafer 1. In FIG. 25, the change over time of the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 comes into contact with the main surface 1a of the semiconductor wafer 1 is plotted in a solid line, but in order to simplify the understanding, Time Tm1 is indicated by a dotted line. In the graph of FIG. 25, the time from the dotted line (time Tm1) to the solid line (the time of contact with the rinsing liquid 35 from the rinsing liquid nozzle 36) at each position of the main surface 1a of the semiconductor wafer 1 is etched. It will correspond to time.

  By controlling the movement of the rinsing liquid nozzle 36 in this way, the etching time in the peripheral portion 1A of the main surface of the semiconductor wafer 1 is approximately Tm11, and etching is performed in a region other than the peripheral portion 1A (central portion 1B). The time is between Tm11 + Tm12 and Tm11 + Tm12 + Tm13. Here, Tm11 corresponds to the time (elapsed time) from time Tm1 to time Tm2, time Tm12 corresponds to the time (elapsed time) from time Tm2 to time Tm3, and time Tm13 corresponds to the time from time Tm3 to time Tm3. This corresponds to the time (elapsed time) up to Tm4. That is, in the peripheral portion 1A of the main surface of the semiconductor wafer 1, the etching of the insulating film 12 is stopped by supplying the rinsing liquid 35 from the rinsing liquid nozzle 36 at time Tm2, but the region other than the peripheral portion 1A ( In the central portion 1B), the etching of the insulating film 12 proceeds after time Tm2, and the rinsing liquid 35 is supplied from the rinsing liquid nozzle 36 between time Tm3 and time Tm4. The etching of the insulating film 12 stops at the central part 1B). Thereby, as shown in FIG. 26, the etching time in the peripheral portion 1A of the main surface of the semiconductor wafer 1 can be made shorter than the etching time in the region other than the peripheral portion 1A (central portion 1B). Accordingly, in the case where the polishing amount in the CMP process in step S3 is larger (peripheral portion 1A) than in the case where the polishing amount in the CMP processing in step S3 is small (region other than the peripheral portion 1A, the central portion 1B), FIG. As shown in FIG. 20, the etching time in step S2 can be shortened (that is, the etching amount in step S2 is reduced as shown in FIG. 20).

  Further, while the rinse liquid nozzle 36 is stopped from time Tm2 to time Tm3, the rinse liquid 35 is supplied from the rinse liquid nozzle 36 to the peripheral portion of the main surface 1a of the semiconductor wafer 1. The center of the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 comes into contact with the main surface 1a of the wafer 1 slightly from the end (wafer end, outer peripheral end, outermost periphery) of the main surface 1a of the semiconductor wafer 1, for example, The inner side (side closer to the center of the semiconductor wafer 1) is about 3 mm. On the main surface 1 a of the semiconductor wafer 1, rinsing is performed by centrifugal force due to the rotation of the semiconductor wafer 1 outside the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 comes into contact with the main surface 1 a. As the liquid 35 flows toward the wafer edge, the rinse liquid 35 is supplied.

  Here, the rinsing liquid 35 discharged from the rinsing liquid nozzle 36 is a liquid column having substantially the same diameter as the diameter of the rinsing liquid discharge hole in the rinsing liquid nozzle 36, and this liquid column (the rinsing liquid 35 The liquid column contacts the main surface 1 a of the semiconductor wafer 1. Therefore, the position where the center of the liquid column of the rinsing liquid 35 discharged from the rinsing liquid nozzle 36 hits the center of the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 contacts the main surface 1 a of the semiconductor wafer 1. Shall be referred to as Between the time Tm2 and the time Tm3, the center of the position where the rinsing liquid 35 from the rinsing liquid nozzle 36 comes into contact with the main surface 1a of the semiconductor wafer 1 slightly from the end of the main surface 1a of the semiconductor wafer 1 (for example, Depending on the diameter of the liquid column of the rinsing liquid 35, the rinsing liquid 35 is supplied to the peripheral portion of the main surface 1a of the semiconductor wafer 1 (a region within about 5 mm from the wafer edge). Thus, the etching of the insulating film 12 can be stopped.

  If the polishing amount of the insulating film 12 during the CMP process in step S3 is uniform in the region (central portion 1B) other than the peripheral portion 1A on the main surface 1a of the semiconductor wafer 1, the rinsing from time Tm3 to time Tm4 is performed. The moving speed of the liquid nozzle 36 is increased as much as possible, and the rinsing liquid nozzle 36 is quickly moved from a position above the peripheral portion of the main surface 1a of the rotating semiconductor wafer 1 to a position above the central portion. It is preferable to shorten Tm13 sufficiently. As a result, in the main surface 1a of the semiconductor wafer 1 in the region other than the peripheral portion 1A (central portion 1B), the etching of the insulating film 12 is stopped almost simultaneously, and the etching time is substantially the same (that is, the etching amount is substantially the same). Therefore, the film thickness distribution of the insulating film 12 after the CMP process in step S3 can be made more uniform.

  On the other hand, the polishing amount of the insulating film 12 during the CMP process in step S3 is not uniform even in the region (central portion 1B) other than the peripheral portion 1A on the main surface 1a of the semiconductor wafer 1, and the semiconductor wafer 1 as shown in FIG. In the main surface 1a, the polishing amount during the CMP process may gradually increase as the distance from the center increases. In general, this tendency often occurs in the CMP process. In this case, the rinsing liquid from time Tm3 to time Tm4 according to the change rate of the polishing amount (change rate in the radial direction of the semiconductor wafer 1) during the CMP process in step S3 on the main surface 1a of the semiconductor wafer 1. The moving speed of the nozzle 36 is controlled (adjusted). That is, if the change rate of the polishing amount during the CMP process in step S3 on the main surface 1a of the semiconductor wafer 1 is small (change rate in the radial direction of the semiconductor wafer 1), the moving speed of the rinsing liquid nozzle 36 is increased, Conversely, if the rate of change is large, the moving speed of the rinsing liquid nozzle 36 is decreased. Further, if the change rate of the polishing amount (change rate in the radial direction of the semiconductor wafer 1) during the CMP process in step S3 on the main surface 1a of the semiconductor wafer 1 is not constant, the rinsing liquid is used in a region where the change rate is large. The moving speed of the rinsing liquid nozzle 36 is increased in a region where the moving speed of the rinsing liquid nozzle 36 is decreased and the rate of change is small. The moving speed of the rinsing liquid nozzle 36 is controlled (adjusted) in accordance with the change rate of the polishing amount (change rate in the radial direction of the semiconductor wafer 1) during the CMP process in step S3 on the main surface 1a of the semiconductor wafer 1. Thus, the film thickness distribution of the insulating film 12 after the CMP process in step S3 can be made more uniform.

  Here, the rate of change of the polishing amount during the CMP process in step S3 on the main surface 1a of the semiconductor wafer 1 is the unit length in the direction from the center of the main surface 1a of the semiconductor wafer 1 toward the peripheral portion (outer peripheral portion). This corresponds to the increase (increase rate) of the polishing amount of the insulating film 12 during the CMP process in step S3, and corresponds to the slope (differential value) of the graph of FIG. For this reason, the small change rate of the polishing amount during the CMP process in step S3 corresponds to the small slope in the graph of FIG. 22, and the large change rate of the polishing amount during the CMP process in step S3 is This corresponds to a large inclination in the graph of FIG.

  Further, unlike the present embodiment, the order of step S2 and step S3 may be interchanged. In this case, after forming the insulating film 12 in step S1, the CMP process of the insulating film 12 in step S3 is performed without performing step S2 (at this stage, the film thickness distribution of the insulating film 12 becomes non-uniform), Thereafter, the wet etching process of step S2 is performed so that the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 becomes uniform. In this case, it is possible to make the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 uniform by performing a wet etching process that makes the film thickness distribution of the insulating film 12 uniform after the CMP process. The following problems will occur. That is, when the insulating film 12 is formed in step S1 and the CMP process of step S3 is performed without performing step S2, scratches are generated on the upper surface of the insulating film 12 due to the CMP process. Then, when the wet etching process in step S2 is performed, the etching isotropically spread from the scratch (that is, the scratch grows into a recess), and a recess is generated on the upper surface of the insulating film 12. there is a possibility. This may reduce the flatness of the upper surface of the insulating film 12 flattened by the CMP process, and may reduce the reliability and manufacturing yield of the semiconductor device.

  In contrast, in this embodiment, after the insulating film 12 is formed in step S1, the wet etching process in step S2 is performed before the CMP process, and then the CMP process is performed on the insulating film 12 in step S3. Yes. For this reason, not only can the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 be made uniform, but also the wet etching process in step S2 is performed before the CMP process, so that scratches due to the CMP process are performed during the wet etching. Since the etching does not expand isotropically as a starting point, the flatness of the upper surface of the final insulating film 12 can be further improved. Further, since the wet etching process of step S2 is performed before the CMP process of step S3, the surface of the insulating film 12 is not contaminated with foreign matters (the surface of the insulating film 12 is cleaned). CMP processing can be performed, and generation of scratches during CMP processing can be suppressed or prevented. Accordingly, the reliability and manufacturing yield of the semiconductor device can be further improved.

  In the present embodiment, after the processing of steps S1, S2, and S3 is performed on a certain semiconductor wafer 1, the film thickness distribution (distribution of film thickness t3) of the insulating film 12 is measured, and the film thickness distribution If the non-uniformity (that is, the film thickness difference between the maximum thickness portion and the minimum thickness portion of the insulating film 12) exceeds a predetermined threshold value, the result is fed back to the next semiconductor wafer. 1 can be reviewed (the distribution of the etching amount in FIG. 20). Here, the next semiconductor wafer 1 is a different semiconductor wafer 1 from which the film thickness distribution was measured. As a result, the film thickness distribution (distribution of the film thickness t3) of the insulating film 12 after step S3 of the next semiconductor wafer 1 can be made uniform, and the film thickness t3 of the insulating film 12 is maximized and minimized. The film thickness difference with the portion can be made equal to or less than the predetermined threshold value.

  For example, after the processing of steps S1, S2, and S3 is performed on a certain semiconductor wafer 1, the film thickness distribution (distribution of film thickness t3) of the insulating film 12 on the main surface of the semiconductor wafer 1 is measured, and the result Assume that the film thickness t3 of the insulating film 12 in the peripheral portion 1A is about 20 nm thinner than the film thickness t3 in the central portion 1B. In this case, the moving condition of the rinsing liquid nozzle 36 when performing step S2 on the next semiconductor wafer 1 (semiconductor wafer 1 different from the film thickness distribution measured) is reviewed, and the time Tm12 is lengthened. In this case (in this case, the film thickness difference td1 is increased by 20 nm by an amount corresponding to the etching amount of 20 nm). That is, the film thickness difference td1 in the next semiconductor wafer 1 is set to be larger by 20 nm than the film thickness difference td1 in the semiconductor wafer 1 in which the film thickness distribution is measured. As a result, when step S3 is performed on the next semiconductor wafer 1, the film thickness t3 of the insulating film 12 in the peripheral portion 1A and the film thickness t3 in the central portion 1B can be made substantially the same. .

  Further, for example, after the processing of steps S1, S2, and S3 is performed on a certain semiconductor wafer 1, the film thickness distribution (distribution of film thickness t3) of the insulating film 12 on the main surface of the semiconductor wafer 1 is measured. As a result, it is assumed that the film thickness t3 of the insulating film 12 in the peripheral portion 1A is about 30 nm thicker than the film thickness t3 in the central portion 1B. In this case, the movement condition of the rinsing liquid nozzle 36 when performing step S2 on the next semiconductor wafer 1 (semiconductor wafer 1 different from the film thickness distribution measured) is reviewed, and the time Tm12 is shortened. By doing so (here, shortening by an amount corresponding to the etching amount of 30 nm), the film thickness difference td1 is reduced by 30 nm. That is, the film thickness difference td1 in the next semiconductor wafer 1 is made smaller by 30 nm than the film thickness difference td1 in the semiconductor wafer 1 whose film thickness distribution is measured. As a result, the film thickness t3 of the insulating film 12 in the peripheral portion 1A and the film thickness t3 in the central portion 1B can be made substantially the same after the step S3 of the next semiconductor wafer 1.

  Measuring the film thickness distribution (distribution of film thickness t3) of the insulating film 12 after the processes of steps S1, S2, and S3 are performed on the semiconductor wafer 1 are all performed in steps S1, S2, and S3. Even if it does not carry out about this semiconductor wafer 1, it can also carry out regularly etc. by extracting every certain number of semiconductor wafers.

  In the present embodiment, the case where steps S1, S2, and S3 are performed on the insulating film 12 has been described. However, similar steps S1, S2, and S3 can be performed on the insulating film 16, and The same applies to the following second embodiment.

  That is, when steps S1, S2, and S3 are performed on the insulating film 12, first, the gate electrode 6 is formed as a pattern layer on the main surface of the semiconductor wafer 1, and the pattern layer (gate electrode 6) is covered. In step S1, the insulating film 12 is formed. Since the top surface of the insulating film 12 is uneven due to the pattern layer (gate electrode 6), the insulating film 12 needs to be flattened, but the insulating film 12 is etched (wet etching) in step S2. After correcting the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1, the upper surface of the insulating film 12 is planarized by CMP in step S3.

  On the other hand, when steps S1, S2, and S3 are performed on the insulating film 16, first, the wiring 15 is formed as a pattern layer on the main surface of the semiconductor wafer 1, and the pattern layer (wiring 15) is covered. In step S1, an insulating film 16 is formed. Since an uneven shape due to the pattern layer (wiring 15) is generated on the upper surface of the insulating film 16, the insulating film 16 needs to be flattened. In step S2, the insulating film 16 is etched (wet etching) to obtain a semiconductor After correcting the film thickness distribution of the insulating film 16 on the main surface of the wafer 1, the upper surface of the insulating film 16 is planarized by CMP in step S3. In this case, the processes of steps S2 and S3 performed on the insulating film 16 are the same as the processes of steps S2 and S3 performed on the insulating film 12, respectively (steps S1, S2, S3 with reference to FIGS. 15 to 26 described above). In this description, the gate electrode 6 is replaced with the wiring 15 and the insulating film 12 is replaced with the insulating film 16). Therefore, the repeated description is omitted here.

  For this reason, in the present embodiment, a pattern layer (gate electrode 6 or wiring 15) is formed on the main surface of the semiconductor wafer 1, and this pattern layer (gate electrode 6 or wiring 15 is formed on the main surface of the semiconductor wafer 1. In step S1, an insulating film (insulating film 12 or insulating film 16) is formed so as to cover. This insulating film (insulating film 12 or insulating film 16) needs to be flattened because it has an uneven shape reflecting the pattern layer (gate electrode 6 or wiring 15) on its upper surface, but it is insulated in step S2. After etching the film (insulating film 12 or insulating film 16) to correct the film thickness distribution of the insulating film (insulating film 12 or insulating film 16) on the main surface of the semiconductor wafer 1, the insulating film (insulating film (insulating film) in step S3) is corrected. 12 or the insulating film 16) is planarized by CMP. At this time, depending on the distribution of the polishing amount of the insulating film (insulating film 12 or insulating film 16) on the semiconductor wafer 1 in step S3, the insulating film (insulating film 12 or insulating film 16) on the semiconductor wafer 1 is determined in step S2. Correct the film thickness distribution. Specifically, in the main surface of the semiconductor wafer 1, the insulating film (insulating film 12 or insulating film in step S3) is smaller than the region where the polishing amount of the insulating film (insulating film 12 or insulating film 16) in step S3 is small. 16) In step S2, the film thickness distribution of the insulating film (insulating film 12 or insulating film 16) is increased so that the film thickness t2 of the insulating film (insulating film 12 or insulating film 16) increases in the region where the polishing amount is large. to correct. Thereby, the film thickness distribution of the insulating film (insulating film 12 or insulating film 16) after the CMP process in step S3 can be made uniform. Note that the film thickness of the insulating film (insulating film 12 or insulating film 16) after the CMP process in step S3 is larger than the height of the pattern layer (gate electrode 6 or wiring 15), and the insulating film subjected to the CMP process in step S3. The pattern layer (gate electrode 6 or wiring 15) is not exposed from (insulating film 12 or insulating film 16).

  Therefore, in the present embodiment (the processes in steps S1, S2, and S3) and the following second embodiment (the processes in steps S1, S2, S3, and S4), the gate electrode or the It is effective when applied to an insulating film in which a concavo-convex shape reflecting the pattern layer is formed because a pattern layer such as wiring is formed and the pattern layer is covered. However, the present embodiment (the processing in steps S1, S2, and S3) and the following second embodiment (in steps S1, S2, and S2) are applied to the insulating film 12 that is an interlayer insulating film formed so as to cover the gate electrode. If the processing of S3 and S4) is applied, the effect is the greatest, and the reason is as follows.

  When a pattern layer (for example, a gate electrode or a wiring) is formed on the main surface of the semiconductor wafer 1 and the insulating film formed so as to cover the pattern layer is planarized by CMP processing, the film thickness distribution of the insulating film is not uniform. If, for example, as shown in FIG. 13, the insulating film becomes thinner in the peripheral portion 1A than in the region other than the peripheral portion (central portion 1B) of the main surface of the semiconductor wafer 1, the insulating film becomes thin. The underlying pattern layer may be exposed in the region. If the pattern layer is a conductor pattern, the exposed pattern layer may cause an electrical short. In this embodiment and the following second embodiment, since the film thickness distribution of the insulating film can be made uniform, it is possible to prevent the pattern layer from being exposed from the insulating film, and the exposed pattern layer causes an electrical short circuit. Can be prevented. For this reason, the manufacturing yield of the semiconductor device can be improved. This effect can be obtained regardless of whether the pattern layer is a wiring or a gate electrode.

On the other hand, when the gate electrode 6 is formed on the main surface of the semiconductor wafer 1 and the insulating film 12 formed so as to cover the gate electrode 6 is flattened by CMP, the film thickness distribution of the insulating film 12 is not uniform. For example, as shown in FIG. 13, when the insulating film 12 becomes thinner in the peripheral portion 1 </ b> A than the region (central portion 1 </ b> B) other than the peripheral portion of the main surface of the semiconductor wafer 1, the contact hole 13 is formed in the insulating film 12. When forming, there is a possibility that damage due to over-etching occurs. That is, if the film thickness distribution of the insulating film 12 is not uniform, it is necessary to perform etching for forming the contact hole 13 so that the contact hole 13 can be opened even in a region where the insulating film 12 is thick. In the thin region 12 (peripheral portion 1A), over-etching may occur at the bottom of the contact hole 13 when the contact hole 13 is formed, and the substrate region (n ⁺ type semiconductor region 9) may be damaged. This may affect the gate characteristics of the MISFET QN. Even if the insulating film 11 is used as an etching stopper film when the contact hole 13 is opened, if the non-uniformity of the film thickness distribution of the insulating film 12 is high (the maximum film thickness portion and the minimum film thickness portion of the insulating film 12). In the region where the thickness of the insulating film 12 is thin (peripheral portion 1A), the substrate region cannot be sufficiently prevented from being damaged by overetching at the bottom of the contact hole 13. In the present embodiment and the following second embodiment, since the film thickness distribution of the insulating film 12 can be made uniform, overetching when forming the contact hole 13 in the insulating film 12 can be suppressed, and the performance and reliability of the semiconductor device can be suppressed. Can be improved. This effect is obtained by forming a gate electrode as a pattern layer on the main surface of the semiconductor wafer 1 and applying this embodiment (steps S1 and S2) to an interlayer insulating film (here, the insulating film 12) formed so as to cover the gate electrode. , S3) and the following second embodiment (processing of steps S1, S2, S3, S4) can be obtained. Therefore, the present embodiment (steps S1, S2, and S3) and the following second embodiment (steps S1, S2, and S3) are applied to the interlayer insulating film (here, the insulating film 12) formed to cover the gate electrode. If the processing of S3 and S4) is applied, the effect is the greatest.

(Embodiment 2)
FIG. 27 is a process flow diagram showing a part of the manufacturing process of the semiconductor device of the present embodiment, and corresponds to FIG. 15 of the first embodiment.

  In the manufacturing process of the semiconductor device of the present embodiment, after performing steps S1, S2, and S3 as in the first embodiment, in step S4, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 is performed. To correct the above (wet etching process). After step S4, the contact hole 13 is formed. In the present embodiment, the film thickness distribution of the insulating film 12 is corrected in step S4 after step S3, so that the film thickness distribution of the insulating film 12 is non-uniform when the CMP process of the insulating film 12 in step S3 is performed. Even if the thickness remains, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 can be made uniform.

  Also in the present embodiment, steps S1, S2, and S3 are the same as those in the first embodiment, and thus description thereof is omitted here, and step S4 performed after step S3 will be described.

FIGS. 28 and 29 are cross-sectional views of the main part during the manufacturing process of the semiconductor device of the present embodiment, and show the peripheral part (outer peripheral part) 1A of the main surface 1a of the semiconductor wafer 1 and the main surface 1a of the semiconductor wafer 1. The principal part sectional view of central part 1B is shown. FIG. 28 is a main-portion cross-sectional view immediately after the insulating film 12 is subjected to the CMP process in step S3 (that is, the process step corresponding to FIG. 6), and corresponds to FIG. 18 of the first embodiment. . FIG. 29 is a cross-sectional view of the main part immediately after the correction of the film thickness distribution of the insulating film 12 in step S4 after the CMP process in step S3 (before the contact hole 13 is formed). 28 and 29, as in FIGS. 16 to 18, the p-type well 3, the n ⁻ -type semiconductor region 7 and the n ⁺ -type semiconductor region 9 are formed on the semiconductor wafer 1 in order to simplify the drawing. In addition, illustration of the sidewall spacer 8, the metal silicide layer 10, and the insulating film 11 is omitted.

  FIG. 30 is a graph showing the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 in the manufacturing process of the semiconductor device of the present embodiment, and corresponds to FIG. 19 of the first embodiment. It is. The horizontal axis of the graph of FIG. 30 corresponds to the distance from the center (the center of the main surface) on the main surface of the semiconductor wafer 1, and the vertical axis of the graph of FIG. In the graph of FIG. 30, the film thickness t1 of the insulating film 12 immediately after depositing the insulating film 12 in step S1 and the film thickness of the insulating film 12 immediately after correcting the film thickness distribution of the insulating film 12 in step S2. The film thickness t2, the film thickness t3 of the insulating film 12 immediately after the CMP process of the insulating film 12 in step S3 (stage of FIG. 28), and the film thickness distribution of the insulating film 12 immediately after the correction in step S4 (FIG. 28). 29 shows the film thickness t4 of the insulating film 12. Here, as described in the first embodiment, the film thickness t1 is the film thickness (that is, the deposited film) of the insulating film 12 immediately after the insulating film 12 is deposited in Step S1 (that is, after Step S1 and before Step S2). Thickness). The film thickness t2 corresponds to the film thickness of the insulating film 12 immediately after the correction of the film thickness distribution of the insulating film 12 in step S2 (that is, after step S2 and before step S3). The film thickness t3 corresponds to the film thickness of the insulating film 12 immediately after the CMP process of the insulating film 12 in step S3 (that is, after step S3 and before step S4). The film thickness t4 corresponds to the film thickness of the insulating film 12 immediately after the correction of the film thickness distribution of the insulating film 12 in step S4 (that is, after step S4).

  In the first embodiment, after the insulating film 12 is formed in step S1, the thickness distribution of the insulating film 12 is corrected in advance in step S2 in consideration of the non-uniformity of the polishing amount in the CMP process in step S3. Then, the CMP process in step S3 is performed. For this reason, compared with the case where step S2 is not performed, the film thickness distribution (film thickness distribution on the main surface of the semiconductor wafer 1) of the insulating film 12 after the CMP process of step S3 can be made uniform.

  However, the film thickness distribution of the insulating film 12 (distribution of the film thickness t3) is measured by measuring the film thickness distribution (distribution of the film thickness t3) of the insulating film 12 on the main surface of the semiconductor wafer 1 after the CMP process in step S3. If it is determined that the uniformity is still not sufficient, the film thickness distribution of the insulating film 12 is further corrected in step S4, so that the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 is uniform. The property can be further improved.

  That is, as shown in FIGS. 28 and 30, the insulating film 12 after the CMP process in step S3 is performed in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region other than the peripheral portion (central portion 1B). The film thickness t3 may be different. Of course, compared with the case where step S2 is not performed (in the case of FIG. 13 of the above comparative example), the step S2 is performed when the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region other than the peripheral portion ( The difference in the film thickness t3 of the insulating film 12 from the central part 1B) is small. Still, as shown in FIGS. 28 and 30, due to variations in manufacturing process conditions, the CMP in step S3 takes place in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region other than the peripheral portion (central portion 1B). There may be a difference in the film thickness t3 of the insulating film 12 after processing.

  Therefore, in the present embodiment, considering the non-uniformity of the film thickness distribution of the insulating film 12 after the CMP process in step S3, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 is etched in step S4. Thus, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 after step S4 is made more uniform.

  That is, by performing Step S4, the film thickness of the insulating film 12 in the peripheral portion 1A of the main surface of the semiconductor wafer 1 and the main surface of the semiconductor wafer 1 are compared with those before performing Step S4 (but after Step S3). Thus, the difference from the thickness of the insulating film 12 in the region other than the peripheral portion 1A (central portion 1B) becomes small. In other words, the film thickness difference (corresponding to the film thickness difference td1) between the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 and the region (central portion 1B) other than the peripheral portion is the step S4. This is smaller after step S4 than before.

  In order to realize this, as can be seen from the graph of FIG. 30, the CMP in step S3 is performed on the main surface of the semiconductor wafer 1 in comparison with the region where the film thickness t3 of the insulating film 12 after the CMP process in step S3 is smaller. In step S4, the insulating film 12 is etched (wet etching) so that the etching amount of the insulating film 12 in step S4 is increased in the region where the film thickness t3 of the insulating film 12 after processing is thick. For this purpose, in the main surface of the semiconductor wafer 1, in a region where the film thickness t3 of the insulating film 12 after the CMP process in step S3 is thicker than the area where the film thickness t3 of the insulating film 12 after the CMP process in step S3 is thin. The insulating film 12 may be etched (wet etching) in step S4 so that the etching time of the insulating film 12 in step S4 becomes longer.

  For example, in FIG. 28, after the CMP process in step S3 (before step S4), the thickness t3 of the insulating film 12 is thin in the peripheral portion 1A of the main surface of the semiconductor wafer 1, and the region other than the peripheral portion (the central portion) In 1B), the film thickness t3 of the insulating film 12 is thicker than that. In this case, the semiconductor wafer 1 where the film thickness t3 of the insulating film 12 is thicker than the etching amount at the peripheral portion 1A of the main surface of the semiconductor wafer 1 where the film thickness t3 of the insulating film 12 is thin. In step S4, the insulating film 12 is etched (wet etching) so that the etching amount at the central portion 1B of the main surface is increased. Thereby, as shown in FIG. 29, the film thickness t4 of the insulating film 12 can be made substantially the same in the peripheral portion 1A of the main surface of the semiconductor wafer 1 and the region other than the peripheral portion (central portion 1B). .

  As described above, in step S2, the non-uniformity in the polishing amount of the CMP process in step S3 is taken into consideration, and the thickness distribution (distribution of the thickness t2) after etching of the insulating film 12 is intentionally made nonuniform. In contrast, step S4 is a process for making the film thickness distribution (distribution of the film thickness t4) after the etching of the insulating film 12 uniform.

  In the present embodiment, by performing step S4 after the CMP process in step S3, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 can be made more uniform.

  28 and 30, the peripheral portion 1A of the main surface of the semiconductor wafer 1 is thicker than the region (central portion 1B) other than the peripheral portion, and the film thickness t3 of the insulating film 12 after the CMP process in step S3. If the thickness is thin, step S4 can be performed using the wet etching apparatus 31 of the first embodiment. A specific procedure of step S4 in this case will be described.

  28 and 30, the peripheral portion 1A of the main surface of the semiconductor wafer 1 is thicker than the region (central portion 1B) other than the peripheral portion, and the film thickness t3 of the insulating film 12 after the CMP process in step S3. Is thinner, the etching amount in step S4 is smaller in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 than in the region other than the peripheral portion (central portion 1B) (the insulating film 12). It is necessary to reduce the etching amount). That is, the etching time of step S4 is such that the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 is shorter (the etching time of the insulating film 12 is shorter) than the region other than the peripheral portion (center portion 1B). It is necessary to.

  For this reason, in step S4, after supplying the etching solution 37 from the nozzle 34 to the central portion of the main surface 1a of the rotating semiconductor wafer 1 for a predetermined time, the supply of the etching solution 37 from the nozzle 34 is stopped, and then In a state where the rinsing liquid nozzle 36 is stopped, the rinsing liquid 35 is supplied from the rinsing liquid nozzle 36 to the peripheral portion of the main surface 1a of the rotating semiconductor wafer 1 for a predetermined time. When the rinse liquid 35 is supplied from the stopped rinsing liquid nozzle 36 to the peripheral portion of the main surface 1a of the semiconductor wafer 1, the etching of the insulating film 12 is stopped in the peripheral portion 1A of the main surface of the semiconductor wafer 1. However, the etching of the insulating film 12 proceeds in a region other than the peripheral portion 1A (central portion 1B). After the supply of the rinsing liquid 35 from the rinsing liquid nozzle 36 to the peripheral portion of the main surface 1a of the semiconductor wafer 1 is continued for a predetermined time, the rinsing liquid nozzle 36 that discharges the rinsing liquid 35 is rotated. From the position above the peripheral portion (outer peripheral portion) of the main surface 1a to the position above the central portion of the main surface 1a of the semiconductor wafer 1 in the horizontal direction (the rotary stage 32 and the main surface 1a of the semiconductor wafer 1 held there) (In a direction parallel to). That is, the rinsing liquid nozzle 36 is moved in the direction of the arrow 39 in FIGS. In the central portion 1B of the main surface 1a of the semiconductor wafer 1, the etching of the insulating film 12 is stopped when the rinsing liquid 35 is supplied from the moving rinsing liquid nozzle 36. Thereafter, a rinsing liquid 35 is supplied from the nozzle 34 located above the central portion of the main surface 1 a of the semiconductor wafer 1 to the central portion of the main surface 1 a of the rotating semiconductor wafer 1. After the rinsing process, the supply of the rinsing liquid 35 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is completed, the semiconductor wafer 1 is rotated at high speed to dry the semiconductor wafer 1, and then the rotation of the semiconductor wafer 1 is stopped. Then, the semiconductor wafer 1 is sent to the next process (contact hole 13 forming process) or is temporarily accommodated in an accommodating case or the like before that.

  In this way, the etching time in the peripheral portion 1A of the main surface of the semiconductor wafer 1 can be made shorter than the etching time in the region (central portion 1B) other than the peripheral portion 1A. Therefore, as shown in the graph of FIG. 30, in step S4, the etching amount in the peripheral portion 1A of the main surface of the semiconductor wafer 1 in which the film thickness t3 of the insulating film 12 is thin (etching amount of the insulating film 12). The etching amount (etching amount of the insulating film 12) at the central portion 1B of the main surface of the semiconductor wafer 1, which is a region where the film thickness t3 of the insulating film 12 is thick, can be increased. Thereby, as shown in FIGS. 29 and 30, the film thickness t4 of the insulating film 12 is made substantially the same in the peripheral portion 1A of the main surface of the semiconductor wafer 1 and the region other than the peripheral portion (central portion 1B). The film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 can be made more uniform.

  28 to 30, in the peripheral portion 1A of the main surface of the semiconductor wafer 1, the thickness t3 of the insulating film 12 after the CMP process in step S3 is thinner than the region other than the peripheral portion (central portion 1B). Showed the case. On the other hand, FIGS. 31 to 33 correspond to FIGS. 28 to 30, respectively. In FIGS. 31 to 33, the peripheral portion 1A of the main surface of the semiconductor wafer 1 is a region other than the peripheral portion. The case where the film thickness t3 of the insulating film 12 after the CMP process of step S3 is thicker than (center part 1B) is shown.

  FIG. 31 and FIG. 32 are cross-sectional views of the main part during the manufacturing process of the semiconductor device of the present embodiment, the peripheral portion (outer peripheral portion) 1A of the main surface 1a of the semiconductor wafer 1 and the center of the main surface 1a of the semiconductor wafer. The principal part sectional drawing of the part 1B is shown. FIG. 31 is a cross-sectional view of the main part immediately after the CMP process of the insulating film 12 in step S3 (that is, the process step corresponding to FIG. 6), as in FIG. 28. FIG. 32 is the same as FIG. Similarly, it is a cross-sectional view of the main part immediately after the correction of the film thickness distribution of the insulating film 12 in step S4 (before the formation of the contact hole 13) after the CMP process in step S3. FIG. 33 is a graph showing the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 in the manufacturing process of the semiconductor device of the present embodiment. The horizontal axis of the graph of FIG. 33 corresponds to the distance from the center of the main surface (center of the main surface), and the vertical axis of the graph of FIG. 33 corresponds to the film thickness of the insulating film 12. In the graph of FIG. 33, as in the graph of FIG. 30, the film thickness t1 of the insulating film 12 immediately after deposition in step S1 and the insulating film immediately after correcting the film thickness distribution of the insulating film 12 in step S2. The film thickness t2 of the film 12, the film thickness t3 of the insulating film 12 immediately after the CMP process of the insulating film 12 in step S3 (stage of FIG. 31), and the film thickness distribution of the insulating film 12 were corrected in step S4. The film thickness t4 of the insulating film 12 immediately after (step of FIG. 32) is shown.

  As shown in FIGS. 31 and 33, the peripheral portion 1A of the main surface of the semiconductor wafer 1 is thicker than the region (central portion 1B) other than the peripheral portion, and the film thickness t3 of the insulating film 12 after the CMP process in step S3. A specific procedure in step S4 when the thickness is increased will be described with reference to FIG. FIG. 34 is an explanatory diagram of the processing in step S4 (processing for correcting the film thickness distribution of the insulating film 12 deposited on the main surface of the semiconductor wafer 1), and corresponds to FIG.

  When the thickness t3 of the insulating film 12 after the CMP process in step S3 is thicker in the peripheral portion 1A of the main surface of the semiconductor wafer 1 than in the region other than the peripheral portion (central portion 1B), FIG. A process of correcting the film thickness distribution of the insulating film 12 in step S4 is performed by wet etching a part (upper layer part) of the insulating film 12 using a single wafer type wet etching apparatus 31a as shown in FIG. Can do.

  Regarding the configuration of the wet etching apparatus 31a, differences from the wet etching apparatus 31 will be described. In the wet etching apparatus 31, the nozzle 34 is a nozzle that serves both as an etching solution and a rinsing solution, so that the etching solution 37 or the rinsing solution 35 can be discharged from the nozzle 34 toward the main surface 1 a of the semiconductor wafer 1. Was configured. On the other hand, in the wet etching apparatus 31 a, the nozzle 34 is a nozzle for rinsing liquid, and the rinsing liquid 35 is discharged (spouted) from the nozzle 34 toward the main surface 1 a of the semiconductor wafer 1, and the main surface 1 a of the semiconductor wafer 1. It is comprised so that the rinse liquid 35 can be supplied.

  In the wet etching apparatus 31a, instead of the rinsing liquid nozzle 36, an etching liquid nozzle (etching liquid supply unit, etching liquid supply means) 36a is arranged above the rotary stage 32, and the etching liquid nozzle 36a. Then, the etching solution 37 is discharged (sprayed and supplied) toward the main surface 1a of the semiconductor wafer 1 so that the etching solution 37 can be supplied to the main surface 1a of the semiconductor wafer 1. The configuration of the etching liquid nozzle 36a is substantially the same as the configuration of the rinsing liquid nozzle 36, except that the etching liquid 37 is discharged instead of the rinsing liquid 35. Since the other structure of the wet etching apparatus 31a is substantially the same as the wet etching apparatus 31, the description thereof is omitted here.

  As shown in FIGS. 31 and 33, the peripheral portion 1A of the main surface of the semiconductor wafer 1 is thicker than the region (central portion 1B) other than the peripheral portion. Is thicker, the etching amount in step S4 is larger in the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 than in the region other than the peripheral portion (central portion 1B) (the insulating film 12 It is necessary to increase the etching amount). That is, the etching time of step S4 is such that the peripheral portion 1A of the main surface 1a of the semiconductor wafer 1 is longer (the etching time of the insulating film 12 is longer) than the region other than the peripheral portion (central portion 1B). It is necessary to.

  For this reason, in step S4, as shown in FIG. 33, the etching solution nozzle 36a is stopped and the etching solution nozzle 36a is moved from the etching solution nozzle 36a to the periphery of the main surface 1a of the rotating semiconductor wafer 1 for a predetermined time. An etching solution 37 is supplied. The etching of the insulating film 12 is started in the peripheral portion 1A of the main surface of the semiconductor wafer 1 when the etching solution 37 is supplied from the stopped etching solution nozzle 36a to the peripheral portion of the main surface 1a of the semiconductor wafer 1. However, in the region other than the peripheral portion 1A (central portion 1B), the insulating film 12 is not etched because the etching solution 37 is not touched. After the supply of the etching solution 37 from the etching solution nozzle 36a to the peripheral portion of the main surface 1a of the semiconductor wafer 1 is continued for a predetermined time, the semiconductor wafer 1 rotating the etching solution nozzle 36a for discharging the etching solution 37 is used. From the position above the peripheral portion (outer peripheral portion) of the main surface 1a to the position above the central portion of the main surface 1a of the semiconductor wafer 1 in the horizontal direction (the rotary stage 32 and the main surface 1a of the semiconductor wafer 1 held there) (In a direction parallel to). That is, the etching solution nozzle 36a is moved in the direction of the arrow 39 in FIG. In the central portion 1B of the main surface 1a of the semiconductor wafer 1, the etching of the insulating film 12 is started when the etching solution 37 is supplied from the moving etching solution nozzle 36a.

  The position where the etching liquid nozzle 36a reaches a position above the central portion of the main surface 1a of the rotating semiconductor wafer 1 and the etching liquid 37 is supplied from the etching liquid nozzle 36a to the main surface 1a of the semiconductor wafer 1 is located. After moving from the periphery of the main surface 1a of the semiconductor wafer 1 to the center of the main surface 1a of the semiconductor wafer 1, the supply of the etching solution 37 from the etching solution nozzle 36a to the main surface 1a of the semiconductor wafer 1 is stopped. . Thereafter, a rinsing liquid 35 is supplied from the nozzle 34 located above the central portion of the main surface 1 a of the semiconductor wafer 1 to the central portion of the main surface 1 a of the rotating semiconductor wafer 1. The rinse liquid 35 supplied from the nozzle 34 spreads over the entire main surface 1 a of the semiconductor wafer 1 by the rotation of the semiconductor wafer 1, and the etching of the insulating film 12 stops on the entire main surface 1 a of the semiconductor wafer 1. When supplying the rinsing liquid 35 from the nozzle 34 to the main surface 1 a of the semiconductor wafer 1, the etching liquid nozzle 36 a is etched above the central portion of the main surface 1 a of the rotating semiconductor wafer 1. The liquid nozzle 36a may get in the way. Therefore, after the supply of the etching solution 37 from the etching solution nozzle 36a is stopped, the etching solution nozzle 36a is moved from the position above the central portion of the main surface 1a of the rotating semiconductor wafer 1 to the peripheral portion (outer peripheral portion). It is more preferable if the supply of the rinsing liquid 35 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is started after being quickly moved to the side.

  After the rinsing process, the supply of the rinsing liquid 35 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is completed, the semiconductor wafer 1 is rotated at high speed to dry the semiconductor wafer 1, and then the rotation of the semiconductor wafer 1 is stopped. Then, the semiconductor wafer 1 is sent to the next process (contact hole 13 forming process) or is temporarily accommodated in an accommodating case or the like before that.

  In this way, the etching time in the peripheral portion 1A of the main surface of the semiconductor wafer 1 can be made longer than the etching time in the region (central portion 1B) other than the peripheral portion 1A. Therefore, as shown in the graph of FIG. 33, in step S4, the etching amount (the etching amount of the insulating film 12) in the peripheral portion 1A of the main surface of the semiconductor wafer 1 which is the region where the film thickness t3 of the insulating film 12 is thick is It can be made larger than the etching amount (the etching amount of the insulating film 12) at the central portion 1B of the main surface of the semiconductor wafer 1 where the film thickness t3 of the insulating film 12 is thin. Thereby, as shown in FIGS. 32 and 33, the film thickness t4 of the insulating film 12 is made substantially the same in the peripheral portion 1A of the main surface of the semiconductor wafer 1 and the region other than the peripheral portion (central portion 1B). Thus, the film thickness distribution of the insulating film 12 on the main surface of the semiconductor wafer 1 can be made more uniform.

  In addition, when wet etching is performed after the CMP process, there is a possibility that the etching expands isotropically starting from scratches generated by the CMP process and a dent is generated. However, in this embodiment, the film thickness distribution (film thickness) of the insulating film 12 immediately after the CMP process in step S3 is corrected by correcting the film thickness distribution of the insulating film 12 in step S2 before the CMP process in step S3. The distribution of t3) is made uniform compared to the case where step S2 is not performed. For this reason, compared with the case where step S2 is not performed, when step S2 is performed as in the present embodiment, the film thickness distribution (distribution of film thickness t3) immediately after the CMP process of step S3. The amount of etching in step S4 can be reduced because of the higher uniformity of. This is because, in order to make the thickness distribution of the non-uniform insulating film uniform by etching, an etching amount greater than the difference in thickness between the maximum thickness portion and the minimum thickness portion of the insulating film is required. Therefore, if the uniformity of the film thickness distribution (distribution of film thickness t3) of the insulating film 12 immediately after the CMP process in step S3 is high, the etching amount of the insulating film 12 in step S4 can be reduced. . For example, in the case of FIG. 14 of the comparative example, an etching amount of about 150 nm or more is required to make the film thickness distribution of the insulating film 12 uniform by wet etching after the CMP process. In the case of FIGS. 30 and 33 of the embodiment, an etching amount of about 50 nm or less is required in order to make the film thickness distribution of the insulating film 12 uniform by the wet etching in step S4.

  For this reason, in this embodiment, the amount of etching necessary to make the film thickness distribution of the insulating film 12 uniform by wet etching in step S4 is reduced by performing step S2 before the CMP process in step S3. Therefore, in the wet etching after the CMP process (here, step S4), it is possible to suppress the isotropic expansion from the scratch generated in the CMP process (here, step S3). Therefore, it is possible to suppress or prevent the scratches from expanding and the depressions from being generated on the upper surface of the insulating film 12.

  In addition, in order to perform the step S2 in the first embodiment, a wet etching apparatus 31b as shown in FIG. 35 can be used instead of the wet etching apparatus 31. In order to perform step S4, a wet etching apparatus 31b as shown in FIG. 35 can be used instead of the wet etching apparatuses 31 and 31a. FIG. 35 is an explanatory diagram of another wet etching apparatus 31b that can be used in step S2 and step S4, and corresponds to FIG. 23 and FIG.

  A wet etching apparatus 31b shown in FIG. 35 includes a rotary stage 32 and a wafer chuck 33. The configurations and functions of the rotary stage 32 and the wafer chuck 33 are the same as those of the wet etching apparatuses 31 and 31a. Therefore, the description is omitted here.

  Similarly to the wet etching apparatus 31a, also in the wet etching apparatus 31b, the nozzle 34 is a nozzle for rinsing liquid, and the rinsing liquid 35 is discharged (spouted) from the nozzle 34 toward the main surface 1a of the semiconductor wafer 1, The rinse liquid 35 can be supplied to the main surface 1 a of the semiconductor wafer 1. Further, in the wet etching apparatus 31b, an etching solution nozzle 36a similar to the wet etching apparatus 31a is disposed above the rotary stage 32, and the etching solution 37 is transferred from the etching solution nozzle 36a to the main surface 1a of the semiconductor wafer 1. The etching liquid 37 can be supplied to the main surface 1a of the semiconductor wafer 1 by being discharged toward the surface. Further, in the wet etching apparatus 31 b, a rinsing liquid nozzle 36 similar to the wet etching apparatus 31 is disposed above the rotary stage 32, and the rinsing liquid 35 is transferred from the rinsing liquid nozzle 36 to the main surface of the semiconductor wafer 1. The rinsing liquid 35 can be supplied to the main surface 1a of the semiconductor wafer 1 by discharging toward the main surface 1a. The etching liquid nozzle 36 a and the rinsing liquid nozzle 36 are respectively located above the rotary stage 32 and above the peripheral portion (outer peripheral portion) of the main surface 1 a of the semiconductor wafer 1 from the center of the main surface 1 a of the semiconductor wafer 1. It is configured to be independently movable in a horizontal direction (a direction parallel to the main surface 1a of the semiconductor wafer 1 held on the rotary stage 32) to a position above the unit. Further, the etching solution nozzle 36a and the rinsing solution nozzle 36 are both configured to move from the peripheral portion to the central portion on the main surface 1a of the semiconductor wafer 1, but as shown in FIG. It is preferable to move from the peripheral part to the central part in different directions.

  The steps S2 and S4 can be performed using the wet etching apparatus 31b as follows.

  As shown in FIG. 35, an etching solution 37 is supplied from the etching solution nozzle 36 a to the peripheral portion of the main surface 1 a of the rotating semiconductor wafer 1. At this stage, etching of the insulating film 12 is started in the peripheral portion 1A of the main surface of the semiconductor wafer 1, but the insulating film 12 is not etched in the central portion 1B because the etching solution 37 is not touched. Then, the etching solution nozzle 36 a that discharges the etching solution 37 is positioned above the peripheral portion (outer peripheral portion) of the main surface 1 a of the rotating semiconductor wafer 1 and above the central portion of the main surface 1 a of the semiconductor wafer 1. In the horizontal direction (direction parallel to the main surface 1a of the semiconductor wafer 1 held on the rotary stage 32). That is, the etching solution nozzle 36a is moved in the direction of the arrow 39 in FIG. In the central portion 1B of the main surface 1a of the semiconductor wafer 1, the etching of the insulating film 12 is started when the etching solution 37 is supplied from the moving etching solution nozzle 36a.

  After a predetermined time elapses after the etching liquid nozzle 36a starts moving while supplying the etching liquid 37 to the main surface 1a of the semiconductor wafer 1, the main nozzle of the rotating semiconductor wafer 1 is transferred from the rinsing liquid nozzle 36. Supply of the rinsing liquid 35 to the peripheral portion of the surface 1a is started. At this stage, the etching of the insulating film 12 is stopped in the peripheral portion 1A of the main surface of the semiconductor wafer 1, but the etching of the insulating film 12 is continued in the central portion 1B because the rinsing liquid 35 is not touched. Then, the rinsing liquid nozzle 36 for discharging the rinsing liquid 35 is positioned above the peripheral portion (outer peripheral portion) of the main surface 1 a of the rotating semiconductor wafer 1 and above the central portion of the main surface 1 a of the semiconductor wafer 1. To move horizontally. That is, the rinsing liquid nozzle 36 is moved in the direction of the arrow 39a in FIG. In the central portion 1B of the main surface 1a of the semiconductor wafer 1, the etching of the insulating film 12 is stopped when the rinsing liquid 35 is supplied from the moving rinsing liquid nozzle 36.

  After the etchant nozzle 36a reaches a position above the center of the main surface 1a of the rotating semiconductor wafer 1, the etchant 37 is supplied from the etchant nozzle 36a to the main surface 1a of the semiconductor wafer 1. Then, after the rinsing liquid nozzle 36 reaches a position above the central portion of the main surface 1a of the rotating semiconductor wafer 1, the rinsing from the rinsing liquid nozzle 36 to the main surface 1a of the semiconductor wafer 1 is performed. The supply of the liquid 35 is stopped. Thereafter, a rinsing liquid 35 is supplied from the nozzle 34 to the central portion of the main surface 1 a of the rotating semiconductor wafer 1. After the rinsing process, the supply of the rinsing liquid 35 from the nozzle 34 to the main surface 1a of the semiconductor wafer 1 is finished, the semiconductor wafer 1 is rotated at high speed to dry the semiconductor wafer 1, and then the rotation of the semiconductor wafer 1 is stopped. Then, the semiconductor wafer 1 is sent to the next process or is temporarily accommodated in an accommodation case or the like before that.

  When the wet etching apparatus 31b shown in FIG. 35 is used, at each position of the main surface 1a of the semiconductor wafer 1, the etching liquid 37 supplied from the etching liquid nozzle 36a is touched (wetted) and then rinsed. Etching of the insulating film 12 proceeds until the rinsing liquid 35 supplied from the liquid nozzle 36 is touched (wetted). That is, the etching time at each position on the main surface of the semiconductor wafer 1 corresponds to the time from when the etching solution nozzle 36a passes over each position until the rinse solution nozzle 36 passes over each position. become. Therefore, by independently controlling the moving speed of the etching liquid nozzle 36 a and the moving speed of the rinsing liquid nozzle 36 according to the etching time required at each position on the main surface of the semiconductor wafer 1, the semiconductor wafer The distribution of the etching amount on one main surface can be a complicated distribution. For example, even if the distribution of the polishing amount (distribution on the main surface 1a of the semiconductor wafer 1) in step S3 is more complicated than the graph of FIG. 22, the distribution of the etching amount in step S2 corresponding to the distribution shown in FIG. (Distribution on the main surface 1a of the semiconductor wafer 1) can be realized using the wet etching apparatus 31b. Further, for example, the film thickness distribution of the insulating film 12 after CMP processing in step S3 (distribution of the film thickness t3 on the main surface 1a of the semiconductor wafer 1) is more complicated than the graphs of FIG. 30 and FIG. However, the etching amount distribution (distribution on the main surface 1a of the semiconductor wafer 1) in step S4 corresponding thereto can be realized by using the wet etching apparatus 31b.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is applicable to semiconductor device manufacturing technology.

It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; It is principal part sectional drawing in the manufacturing process of the semiconductor device of a comparative example. FIG. 14 is an essential part cross sectional view of the comparative semiconductor device during a manufacturing step following FIG. 13; 7 is a graph showing a film thickness distribution of an insulating film on a main surface of a semiconductor wafer in a manufacturing process of a semiconductor device of a comparative example. It is a process flow figure showing a part of manufacturing process of a semiconductor device which is one embodiment of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 17 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 16; FIG. 18 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 17; It is a graph which shows the film thickness distribution of the insulating film in the main surface of a semiconductor wafer. It is a graph which shows the etching amount of the insulating film in the process which correct | amends the film thickness distribution of the insulating film deposited on the main surface of a semiconductor wafer. It is a graph which shows the etching amount of the insulating film in the process which correct | amends the film thickness distribution of the insulating film deposited on the main surface of a semiconductor wafer. It is a graph which shows the polish amount of the insulating film in CMP processing. It is explanatory drawing of the process which correct | amends the film thickness distribution of the insulating film deposited on the main surface of a semiconductor wafer. It is explanatory drawing of the process which correct | amends the film thickness distribution of the insulating film deposited on the main surface of a semiconductor wafer. It is a graph which shows the movement position (position where the rinse liquid from the nozzle for rinse liquid contacts the main surface of a semiconductor wafer) of the rinse liquid nozzle. It is a graph which shows the etching time of the insulating film in each position of the main surface of a semiconductor wafer. It is a process flowchart which shows a part of manufacturing process of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 29 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 28; It is a graph which shows the film thickness distribution of the insulating film in the main surface of a semiconductor wafer. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 32 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 31; It is a graph which shows the film thickness distribution of the insulating film in the main surface of a semiconductor wafer. It is explanatory drawing of the process which correct | amends the film thickness distribution of the insulating film deposited on the main surface of a semiconductor wafer. It is explanatory drawing of a wet etching apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a Main surface 1A Peripheral part 1B Central part 2 Element isolation region 3 P-type well 4 Gate insulating film 5 Conductive film 6 Gate electrode 7 n ⁻ type semiconductor region 8 Side wall spacer 9 n ⁺ type semiconductor region 10 Metal silicide layer 11, 12 Insulating film 13 Contact hole 14 Plug 14a Conductive barrier film 14b Main conductor film 15 Wiring 15a Titanium film 15b Titanium nitride film 15c Aluminum film 15d Titanium nitride film 16 Insulating film 17 Through hole 18 Plugs 31, 31a, 31b Wet etching Device 32 Rotating stage 33 Wafer chuck 34 Nozzle 35 Rinsing liquid 36 Rinsing liquid nozzle 36a Etching liquid nozzle 37 Etching liquid 38 Center 39, 39a Arrow QN n channel type MISFET
t1, t2, t3, t4 Film thickness (thickness)
td1 Film thickness difference Tm1, Tm2, Tm3, Tm4 Time Tm11, Tm12, Tm13, Tm14 Time

Claims (20)

(A) a step of preparing a semiconductor wafer;
(B) forming a pattern layer on the main surface of the semiconductor wafer;
(C) forming a first insulating film on the main surface of the semiconductor wafer so as to cover the pattern layer;
(D) After the step (c), etching the first insulating film to correct the film thickness distribution of the first insulating film in the semiconductor wafer;
(E) a step of subjecting the upper surface of the first insulating film to a CMP process after the step (d);
Have
The film thickness distribution of the first insulating film in the semiconductor wafer is corrected in the step (d) according to the distribution of the polishing amount of the first insulating film in the semiconductor wafer in the step (e). A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
In the step (d),
In the main surface of the semiconductor wafer, in a region where the polishing amount of the first insulating film in the step (e) is larger than a region where the polishing amount of the first insulating film in the step (e) is small, A method of manufacturing a semiconductor device, comprising correcting a film thickness distribution of the first insulating film so that the film thickness of the first insulating film is increased. The method of manufacturing a semiconductor device according to claim 2.
In the step (d),
In the main surface of the semiconductor wafer, in a region where the polishing amount of the first insulating film in the step (e) is larger than a region where the polishing amount of the first insulating film in the step (e) is small, A method of manufacturing a semiconductor device, wherein the first insulating film is wet-etched so as to reduce an etching amount in the step (d). In the manufacturing method of the semiconductor device according to claim 3,
In the step (d),
In the main surface of the semiconductor wafer, in a region where the polishing amount of the first insulating film in the step (e) is larger than a region where the polishing amount of the first insulating film in the step (e) is small, A method of manufacturing a semiconductor device, wherein the first insulating film is wet-etched so that an etching time in the step (d) is shortened. In the manufacturing method of the semiconductor device according to claim 4,
In the step (e),
The polishing amount of the first insulating film in the peripheral portion of the main surface of the semiconductor wafer is larger than the polishing amount of the first insulating film in a region other than the peripheral portion of the main surface of the semiconductor wafer. A method of manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 5,
In the step (d),
The film thickness of the first insulating film in the peripheral portion of the main surface of the semiconductor wafer is larger than the film thickness of the first insulating film in a region other than the peripheral portion of the main surface of the semiconductor wafer. As described above, a method of manufacturing a semiconductor device, comprising correcting a film thickness distribution of the first insulating film in the semiconductor wafer. The method of manufacturing a semiconductor device according to claim 6.
In the step (d),
The first insulating film is wet etched so that an etching amount at the peripheral portion of the main surface of the semiconductor wafer is smaller than an etching amount at a region other than the peripheral portion of the main surface of the semiconductor wafer. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 7.
In the step (d),
The first insulating film is wet-etched so that an etching time at the peripheral portion of the main surface of the semiconductor wafer is shorter than an etching time at a region other than the peripheral portion of the main surface of the semiconductor wafer. A method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 8.
By performing the step (d), the film thickness of the first insulating film in the peripheral portion of the main surface of the semiconductor wafer and the semiconductor wafer are compared with those before performing the step (d). A method of manufacturing a semiconductor device, wherein a difference from the film thickness of the first insulating film in a region other than the peripheral portion of the main surface is increased. In the manufacturing method of the semiconductor device according to claim 9,
By performing the step (e), the film thickness of the first insulating film in the peripheral portion of the main surface of the semiconductor wafer and the thickness of the semiconductor wafer are compared with those before performing the step (e). A method for manufacturing a semiconductor device, characterized in that a difference from the film thickness of the first insulating film in a region other than the peripheral portion of the main surface is reduced. The method of manufacturing a semiconductor device according to claim 10.
The method of manufacturing a semiconductor device, wherein the pattern layer is a gate electrode pattern or a wiring pattern. The method of manufacturing a semiconductor device according to claim 11.
The method of manufacturing a semiconductor device, wherein the first insulating film is an interlayer insulating film. In the manufacturing method of the semiconductor device according to claim 12,
The first insulating film formed in the step (c) has an uneven shape reflecting the pattern layer on the upper surface of the first insulating film,
A method of manufacturing a semiconductor device, wherein an upper surface of the first insulating film is planarized by the CMP process in the step (e). 14. The method of manufacturing a semiconductor device according to claim 13,
In the step (d),
The semiconductor wafer is rotated, an etching solution for etching the first insulating film is supplied to the main surface of the rotating semiconductor wafer, and then the main surface of the semiconductor wafer is rotated from a rinse solution supply unit. While supplying the rinsing liquid for stopping the etching of the first insulating film, the rinsing liquid supply part is moved from the peripheral part side to the central part side of the main surface of the semiconductor wafer above the rotating semiconductor wafer. A method for manufacturing a semiconductor device, comprising: 15. The method of manufacturing a semiconductor device according to claim 14,
In the step (d),
Etching of the first insulating film is started on the entire surface of the main surface of the semiconductor wafer by supplying the etching solution to the central portion of the main surface of the rotating semiconductor wafer. Method. In the manufacturing method of the semiconductor device according to claim 15,
In the step (d),
Etching of the first insulating film proceeds at each position on the main surface of the semiconductor wafer from the time when the etching solution touches until the time when the etching solution is supplied from the rinsing solution supply unit. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 16,
In the step (d),
The rinse liquid is supplied to the peripheral portion of the main surface of the semiconductor wafer rotating from the rinse liquid supply section in a state where the rinse liquid supply section is stopped, and then the upper side of the rotating semiconductor wafer. A method of manufacturing a semiconductor device, wherein the rinsing liquid supply part is moved from the peripheral part side to the central part side of the main surface of the semiconductor wafer. The method of manufacturing a semiconductor device according to claim 10.
After the step (e),
(F) etching the first insulating film to correct a film thickness distribution of the first insulating film in the semiconductor wafer;
Further comprising
By performing the step (f), the film thickness of the first insulating film in the peripheral portion of the main surface of the semiconductor wafer and the thickness of the semiconductor wafer compared to before performing the step (f) A method for manufacturing a semiconductor device, characterized in that a difference from the film thickness of the first insulating film in a region other than the peripheral portion of the main surface is reduced. The method of manufacturing a semiconductor device according to claim 18.
In the step (f),
In the main surface of the semiconductor wafer, the first insulating film after the CMP process in the step (e) is smaller than a region where the thickness of the first insulating film after the CMP process in the step (e) is thinner. A method of manufacturing a semiconductor device, comprising wet etching the first insulating film so that an etching amount in the step (f) increases in a thick region. In the manufacturing method of the semiconductor device according to claim 19,
In the step (f),
In the main surface of the semiconductor wafer, the first insulating film after the CMP process in the step (e) is smaller than a region where the thickness of the first insulating film after the CMP process in the step (e) is thinner. A method of manufacturing a semiconductor device, characterized in that the first insulating film is wet-etched so that the etching time in the step (f) becomes long in a thick region.

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