JP2009295616A - Silicon substrate, method for manufacturing device, device and testing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a silicon substrate achieving electrical isolation of a wide voltage region of 500 V or larger, in a manufacturing process allowing coexistence with STI and having an isolation structure for blocking the physical movement of metal to the depth of a through-electrode, while ensuring surface planarity and metal contamination gettering performance. <P>SOLUTION: A groove of ≥1 μm width and ≥1 μm depth is formed on a silicon oxide film and the silicon oxide film is embedded in the groove, thereby realizing isolation, having breakdown voltage of ≥500 V, even on a substrate having crystal defects. Thus, a power device can be mounted mixedly on the substrate same as that of an existing device operating at a high speed by shallow trench isolation. Also, a metal is embedded in a cavity, from which a silicon surrounded by a thick isolation material is removed to form a substrate through electrode, capable of removing diffusion of metal contamination, thereby enabling multilayer substrate. In this way, wiring from a power supply is fed through the substrate, thereby making realized a power supply which also works as a heat sink, and a device in which a large-power device operating therewith and a high-speed high integration device are stacked. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a silicon substrate, a device manufacturing method, a device manufacturing method, and a testing method, which have an isolation structure that can insulate even devices with greatly different potentials and can be stacked with substrate chips having various functions.

  Conventionally, there is a demand for integrating devices having different functions on a chip. One of the manifestations is the system LSI. These include devices such as a CPU, cache memory, FPGA, nonvolatile memory (flash memory, MRAM, FeRAM, PRAM, etc.), power device, RF analog device, light emitting / receiving device, imaging device, sensor device, MEMS device.

  Since these use different potentials and voltage regions, they cannot be produced in the same manufacturing process. Therefore, the technique of manufacturing separately and connecting them on a printed circuit board is taken.

  Also, when the substrate wafer is a compound, the same substrate cannot be selected, but there are combinations that can be integrated if they are made on the same silicon wafer. For example, a power device and an LSI can be integrated although there is a difference in power supply voltage.

  However, at this time, a big difference in the operating voltage range becomes a problem. If there is a large voltage difference or potential difference, it is necessary to isolate it. For example, if devices that can operate in the 1V region and the 500V region can be integrated on one chip, the range of functional integration increases.

  In fact, in-vehicle devices are designed with high-impedance power control that increases voltage and reduces current in order to make wires thinner and lighter in weight. There is an increasing demand for low voltage operating memory devices and high voltage operating power devices to be designed on a silicon substrate.

  Further, if the front and back surfaces of the wafer are connected by electrodes, and the substrate wafer and the electrodes are insulated, functional devices having different design rules can be created as one device by stacking chips. If this is developed, functional devices stacked in three dimensions will have the same functions as artificial intelligence devices. In addition, artificial intelligence robots connected by RF communication may be possible in the near future.

  When a device is fabricated on a silicon substrate wafer (hereinafter referred to as a silicon substrate), the isolation technique is to electrically insulate transistors from each other. Isolation is also called element isolation. In a general semiconductor device process, this isolation process is the first process. FIG. 28 schematically shows the main isolation techniques known so far.

  Isolation technology has a history that has changed with the evolution of devices. Although not shown, in the pn junction isolation, the potential distribution is designed and used so that the reverse bias state can be maintained. However, if pn junctions exist adjacent to each other, for example, a bipolar transistor such as pnpn creates a thyristor circuit by creating a positive feedback connection structure. Was necessary.

  Since the density of the device cannot be increased, the LOCOS method was developed around 1971. This is a method of generating a thick insulator between elements. When the silicon wafer is oxidized using the silicon nitride film as a mask, the unmasked portion of silicon is oxidized and swelled to produce an insulating structure. At this time, a bird's beak-like laterally spread portion occurs at the boundary of the mask. This hindered miniaturization of narrowing an active region for manufacturing a transistor.

  As a countermeasure, shallow trench isolation (hereinafter referred to as STI: Shallow Trench Isolation) shown in FIG. 28 (E) has been developed. An example in which this is used for CMOS isolation is schematically shown in FIG. As shown in this figure, the p well and the n well are separated by STI. Transistors are also separated by STI. The depth of STI is generally 0.4 um, but this depends on the device generation. For these reasons, STI is suitable because it integrates devices at high density.

  Further, the depth is substantially constant within the substrate surface, and becomes shallower when designed finely. Therefore, STI cannot be used for devices that handle high power or high voltage, and it has been necessary to increase the thickness of the conventional LOCOS method or an insulating film. In addition, in a device using STI, since the surface processing for flattening is performed in the same plane by a flattening technique called chemical mechanical polishing (hereinafter referred to as CMP), the mixture of STI and LOCOS cannot be performed in the process design for the product. It was. Therefore, a high-density or high-speed high-density device operating at a low voltage and a high-power or high-voltage device are not mixedly mounted on the same chip at a high density.

  However, the STI technology was an extension of the technology called U-groove isolation, which is an isolation technology for bipolar devices, which was a high-power or high-density device at that time. An example of the structure of the U groove is shown in FIG. In this structure example, the trench is made to reach the n + buried layer which becomes the collector layer of the bipolar transistor, and the element is separated. Further, not only the U-groove but also the V-groove isolation shown in FIG. 28A, which is easy to manufacture, was used. Historically, bipolar devices required high breakdown voltage and high density, so U-shaped and V-shaped grooves were made in a silicon wafer, the surface was oxidized, and the remaining grooves were filled with polysilicon. Isolation was mainly performed using a technique of polishing the surface by CMP.

  The manufacturing process of STI is similar to these in terms of manufacturing method. First, a silicon nitride film / silicon oxide film laminated film is formed on a silicon wafer, and a silicon trench having a depth of about 0.4 μm is formed using this as a mask by a dry etching method. After this groove is oxidized (which may not be oxidized), a silicon oxide film is buried by a high-density plasma CVD apparatus, and this is polished flat by CMP to obtain a wafer surface isolated by the oxide film.

  This is a general-purpose isolation technology of the current CMOS device, and the isolation width can be 0.1 μm or less.

  The above is the element level isolation technique, but there is a technique for isolating the entire chip from the substrate. This is shown in FIG.

  The technique shown in FIG. 28B creates a large V-shaped groove on the wafer, oxidizes it, and fills the groove with 500 μm of polysilicon that is thick enough to become a substrate. The substrate wafer side is polished and removed to form an island of silicon isolated by an oxide film on the polysilicon substrate. When a device is fabricated on this silicon island, a device chip island completely isolated from the substrate and other islands can be fabricated on the polysilicon substrate chip. Therefore, it was used for ICs that operate directly with a commercial power supply of 100V.

  With the above-mentioned technology, it is possible to fabricate both high-power and high-density VLSI as well as the ability to integrate devices with greatly different potentials and voltages on a single chip. However, integration of devices with different functions such as high power, high density, and high speed requires new isolation design technology.

  The above has described the entire electrical isolation of the device. There is a prior art that uses one of the process techniques used to create the structure of the present invention to separate the chips, not the element isolation.

  FIG. 30 shows the main part of this prior art. This is because a resist mask is used to separate a 0.15 mm chip in which a coil as an inductor and a capacitor as a capacitor are combined to form a tank circuit, so that the width is 50 μm or less and the depth is 10 to 10. A 100 μm kerf is formed at a location where the substrate is to be diced, and then the back surface of the substrate is polished to separate the chips, thereby creating a powder that resonates with RF.

  This is a technique for performing a deep substrate etching step (gas dicing step in FIG. 30) using a gas, which is performed for chip separation, after a step of forming circuit elements to separate the substrate (element formation step in FIG. 30). . Since the purpose is to physically separate the chips, there is no step of filling the groove with an insulator using this technique (see, for example, Non-Patent Document 1).

(Not published for violations of public order and morals)

  In general, it is desired for integration of functions that there is an electrical isolation function of 100 V or more even at the lowest. For example, there is a demand for manufacturing an IC that operates at 100 V with dielectric isolation and an IC that operates at 3 V with STI isolation shown in FIG. 28B on one chip. However, even at a level that does not have to be taken into consideration in a high-power device, metal contamination that enters during the manufacturing process becomes a problem in a high-density device that operates at a low voltage.

  FIG. 31 shows a model of metal contamination penetration and movement. Metal particles entering from the surface move in a layer called an active layer in which a transistor is formed. When it collects in crystal defects, it creates a current leakage path and causes malfunction. In a chip having a through electrode, there is a probability that the electrode metal enters the active layer through a defect generated in an oxide film surrounding the chip.

  In addition to electrical isolation, it is different from the conventional electrical isolation in that it must be taken into account by taking into account the infiltration and migration isolation of contaminated metals at the same time.

  In other words, not only the physical depth but also the isolation is a barrier to the movement of contamination. Therefore, a thick insulating groove that is at least deeper than the thickness of the active layer is required. Groove formation must first be considered in combination with crystal defects in the substrate and metal gettering.

  In order to obtain a high yield, an epitaxial substrate wafer is used as a wafer having no COP defect. COP is an accumulation of silicon atomic vacancies, and is a regular octahedral void, and the inside is covered with an oxide film. This is schematically shown in FIG. The size is about 0.2 to 0.3um, and the smaller one is distributed statistically. Since the pulled ingot always exists, in order to avoid COP, an epitaxial film of silicon is grown by CVD (chemical vapor deposition) on a silicon substrate doped with boron at a high concentration and used. Thicknesses of 1 um, 3 um, 5 um, and 11 um are used in general-purpose LSIs.

  In addition, if at least the epitaxial layers are separated from each other so that a groove is formed deeper than this, the V-shaped opening becomes wider. Therefore, it cannot be used for products aiming at high integration. In addition, when polysilicon is buried, when charge is accumulated, the lining oxide film acts as a gate, and a huge parasitic MOS transistor is produced. This problem is the same when the U groove is used. Further, since the oxide film obtained by oxidizing the substrate has an oxide film defect due to the COP defect, the metal contamination moves or penetrates through the oxide film defect.

  On the other hand, as the name suggests, STI has a shallow depth, so that the surface can be electrically isolated, but the epitaxial layer cannot be completely physically separated to prevent migration of metal contamination. For that purpose, the depth is required to be at least 1 μm or more. Physical isolation is also necessary for isolation of deep wells in CMOS devices. Since the epitaxial layer does not include a COP (Crystal Originated Particle) defect, if minority carriers are generated, the lifetime is long, but there is no problem as long as the minority carriers are small.

  However, when the wells are close to each other and a large amount of minority carriers are generated in a short time by impact ionization of high voltage operation, it drifts and reaches the well. In order to avoid obstacles due to this, there are methods such as providing a circuit for fixing the well potential with a power source, increasing the distance between the wells, or designing without mounting a high voltage device. However, both of them give design restrictions on the degree of integration and function, and a structure that eliminates these restrictions is desired.

  When high voltage isolation is desired, further consideration must be given to securing a metal gettering function in conjunction with the substrate structure.

However, since the epitaxial layer on the substrate does not contain oxygen, there is no metal getter action. Therefore, a p-type wafer containing oxygen at a concentration of 8 × 10 ¹⁷ / cm ³ or more and containing boron for maintaining mechanical strength at a high concentration is used for the substrate. Since a certain thickness of 10 μm or more is necessary to maintain the getter function, a substrate having a thickness of 10 μm or more remains even when the back surface is thinly polished as a chip.

  Therefore, in order to obtain a high withstand voltage, it is necessary to design the isolation so that at least the epitaxial layer as the active layer is pierced and the substrate having a gettering action is left. By making a groove to this depth and filling the insulator, it is possible to achieve high isolation that is effective both in terms of electrical and metal contamination prevention. In the experiment, an oxide film with a thickness of 1 um has a withstand voltage of 500 V or more. Therefore, when the current path crosses the oxide film, a deep groove with a width of 1 um or more is created and the oxide film is buried to isolate it. Isolation of 500V or more is possible.

  However, if the substrate potential is floating, there is a concern that the substrate potential may become unstable due to the generation and inflow of minority carriers, and if the voltage is increased electrostatically to a high potential, arc discharge destruction will occur. It is predicted. Therefore, the device requires a physically deep isolation that prevents the inflow of minority carriers.

  The prior art manufacturing process shown in FIG. 30 includes a process called gas dicing. In that process, a cut groove having a width of 50 μm or less and a depth of 10 to 100 μm is produced. Since this groove is used for chip separation, it remains as a groove. If there is a groove, particles, dust, and contaminants accumulate there and are scattered on the surface of the substrate, so that the device cannot be manufactured. In other words, device manufacturing requires a flat surface structure in which grooves different from those of the prior art are filled. That is, it is necessary to realize electrical isolation in a wide voltage region of 500 V or more in a manufacturing process that can coexist with STI while ensuring surface flatness and a metal contamination gettering function.

  Next, the second problem will be described. FIG. 31 shows the through electrode. The through electrode oxidizes the silicon substrate and fills the hole with a metal material using the oxide film as a protective film. However, as described above, a defect called COP was known in the silicon substrate. However, in recent years, it has been found that it is a regular octahedral void defect, and the size is statistically distributed. . Therefore, it is difficult to avoid defects in the oxide film formed by oxidizing silicon. When the element of the high-density device is as small as 0.1 um or less, the probability of encountering this defect is low, but the electrode penetrating the substrate is a part of the device having a length of 10 to 100 um, and the probability of encountering the COP defect is low. high. Further, when a thermal oxide film encounters a defect, a hole is formed in the portion or the thickness is reduced. If it is in the gate oxide film, there is a problem that the transistor becomes defective.

  Moreover, in order to avoid metal contamination, there is a conventional example using polysilicon instead of metal as a through electrode material (Oki Technical Review (p66, No. 211, Vol. 74 No. 3, October 2007)). The main part of this is shown in FIG. In this example, doped polysilicon is used instead of metal. Although it is described that a sufficiently low resistance is obtained in the stack of DRAMs, it is necessary to reduce the resistance during conduction. For example, in order to stack an in-vehicle device, it is necessary to prevent metal contamination from a through electrode filled with metal instead of polysilicon. For this purpose, an isolation structure for preventing physical metal movement down to the entire depth of the through electrode is necessary.

  Therefore, the present invention has been made in view of the above circumstances, and realizes electrical isolation in a wide voltage region of 500 V or more in a manufacturing process capable of coexisting with STI while ensuring surface flatness and a metal contamination gettering function. It is another object of the present invention to provide a silicon substrate having an isolation structure for preventing physical metal movement to the entire depth of the through electrode, a device manufacturing method, a device, and a test method.

  The present invention proposes the following items in order to solve the above-described problems.

  (1) In the present invention, before manufacturing a transistor device on the surface of a silicon substrate, a groove having a depth of 1 μm or more in which an electric insulator is embedded is formed and a width of 1 μm or more is formed. A silicon substrate that is insulated and separated by the groove is proposed.

  (2) The present invention relates to the silicon substrate of (1), wherein there is a groove having a depth of 1 μm or more in which an electrical insulator is embedded and a width of 1 μm or more embedded in the surface of the silicon substrate. A silicon substrate characterized by surrounding shallow trench isolation with a depth of 0.5 μm or less is proposed.

  (3) The present invention proposes a silicon substrate characterized in that the silicon substrate of (1) has a DTI at the planar position of the scribe line separating the first chip and the second chip.

  (4) The present invention proposes a silicon substrate characterized in that the groove further forms a groove inside the silicon substrate of (1).

  (5) The present invention proposes a silicon substrate characterized in that the silicon substrate of (1) has a plurality of the grooves having different depths.

  (6) The present invention proposes a silicon substrate characterized in that, with respect to the silicon substrate of (5), the plurality of grooves are gathered at a distance equal to or less than one outer dimension thereof.

  (7) The present invention proposes a silicon substrate having a diameter of 300 mm with respect to the silicon substrates of (1) to (6).

  (8) The present invention proposes a device manufacturing method using the substrate according to any one of (1) to (7), wherein the STI is manufactured after the groove is formed.

  (9) The present invention proposes a device manufactured by the method described in (8) using the substrate described in any one of (1) to (7).

  (10) The present invention proposes a device manufactured using the substrate according to any one of (1) to (7), characterized in that there is a wiring straddling the groove.

  (11) The present invention proposes a device characterized in that the inner surface of the substrate surrounded by the groove by polishing the back surface of the substrate and the outer substrate of the groove are electrically isolated.

  (12) The present invention relates to the device according to (11), the wiring formed on the surface of the substrate by embedding a metal material in a cavity formed by etching and removing the inner side silicon substrate isolated by the groove from the back surface. A device characterized by producing a conductive back through electrode is proposed.

  (13) The present invention proposes a device characterized in that the device of (12) has a plurality of through-back electrodes assembled at a distance shorter than the outer shape of one of the grooves.

  (14) The present invention proposes a device characterized by having a groove surrounding a plurality of through-back electrodes assembled in (13) with respect to the device of (12) or (13).

  (15) The present invention proposes a device characterized in that, with respect to the devices of (12) to (14), the substrate surface has a front bump electrically connected to the through back electrode.

  (16) The present invention proposes a device in which a substrate on which a device having a front bump electrically connected to the through back electrode is mounted on the surface of the substrate is stacked for the devices of (12) to (14).

  (17) According to the present invention, in the device according to any one of (12) to (14), the number of bumps is smaller than the number of the through-back electrodes in the device having a front bump electrically connected to the through-back electrode on the substrate surface. We have proposed a device characterized by

  (18) In the device according to claim 11, wherein the first and second substrate chips are formed on the same substrate in which the inner portion and the outer portion of the groove are electrically insulated from each other. And the device characterized by having the said penetration back electrode as described in (13) is proposed.

  (19) The present invention proposes a test method characterized by conducting an electrical test of a device on the surface of the substrate with an electrode formed on the back surface of the substrate.

  According to the present invention, a silicon oxide film having a width of 1 μm or more and a deep groove of 1 μm or more is formed, and a silicon oxide film is buried in the groove so that isolation with a breakdown voltage of 500 V or more can be achieved even on a substrate having crystal defects. It was realized. Accordingly, there is an effect that it is possible to mount the power device on the same substrate as the existing device that operates at high speed by the shallow trench isolation. Further, by filling a cavity from which silicon surrounded by a thick isolation material was removed with metal, a through-substrate electrode that prevented diffusion of metal contamination was formed, which enabled the lamination of the substrate. This makes it possible to supply wiring from the power source through the substrate, and to realize a power supply that also serves as a heat sink, and a device in which a high-power device and a high-speed highly integrated device are stacked. .

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that the constituent elements in the present embodiment can be appropriately replaced with existing constituent elements, and various variations including combinations with other existing constituent elements are possible. Therefore, the description of the present embodiment does not limit the contents of the invention described in the claims.

The embodiment of the present invention will be described with reference to FIGS.
In order to prevent the movement of metal, for example, it is effective in terms of physical properties to shield it with a thermal oxide film, a CVD oxide film, or a CVD silicon nitride film. Considering the case where these are laminated, if the thickness of one material capable of preventing metal movement is known, at least the material can prevent metal movement. When such a shielding structure is formed on a silicon substrate, the blocking ability is determined not by the physical properties of the material but by the small number of defects in the material when the blocking material is formed on the surface having the void defect COP.

  In order to know the probability of defects when forming a thermal oxide film, an experiment was conducted to obtain the minimum required thickness by oxidizing the silicon substrate with COP and determining the relationship between the thickness and the defect rate.

FIG. 1 shows a cross section of the material used for the experiment.
FIG. 1A is a schematic view of a cross section of a silicon substrate including COP. Void defect COPs of various sizes exist. There are several to several tens of COPs having a size of 0.2 μm or more appearing on the surface of a 300 mm wafer. The smaller ones can be measured up to 0.09 um or 0.06 um.

  A p-type 10 Ωcm 300 mm silicon wafer was used as a substrate, a 7 nm thick thermal oxide film was formed, and a doped 150 nm thick polysilicon electrode was formed on 10 mm □. A schematic view of the cross section is shown in FIG.

  Since polysilicon is a material with a coverage of 100%, if there is a void due to COP, the polysilicon will enter the COP and form an electrode with a sharp tip. When this is done, the substrate is shorted by the voltage across the polysilicon. When the ratio of chips short-circuited was examined from the voltage-current characteristics, 85% or more were short-circuited.

  As the thickness of the thermal oxide film increased, the proportion of short-circuited chips decreased. When the thickness was 1 μm, there was no short-circuit chip when a voltage of 500 V was applied. Therefore, it was found that a thermal oxide film having a thickness of at least 1 μm or more is a film without pores.

  Further, there was no short-circuit chip even in a laminated structure of a CVD oxide film 1 um grown from TEOS and ozone on a 0.6 um thick thermal oxide film.

  In addition, a short-circuit chip is also formed by laminating three layers of 0.3 μm low pressure CVD silicon nitride film grown from dichlorosilane (SiH 2 Cl 2) and ammonia (NH 3) on the thermal oxide film 0.5 μm, and 1 μm oxide film grown from TEOS and ozone. There was no.

  At least the above structure is considered to give a structure without a hole through which the metal passes, and this is used as a metal movement blocking structure. The model is shown in FIG. This is a model that prevents metal from entering the active layer in which the device is fabricated.

At least a width of 1 μm or more and a deep groove of 1 μm or more were formed, and an isolation filled with an oxide as an insulator was manufactured. This will be referred to as DTI (Deep Trench Isolation).
). This basic structure is shown in FIG.

Here, FIG. 3A is a plan view, and FIG. 3B is a cross-sectional view of X1X1.
The silicon substrate 100 is a 10 Ωcm p-type wafer having a diameter of 300 mm. The DTI is made by etching the silicon substrate 101 by RIE to a depth D of, for example, 50 μm using the oxide film as a mask to form a groove (called a trench) having a design width W = 5 μm on the mask. Inside the silicon island 107 on the mask, one side I = 50 μm square silicon island 107 is formed separately.

  The oxide film as the trench etching mask is removed by wet cleaning to grow a pad oxide film of 500 nm. Using a low pressure CVD apparatus, dichlorosilane (SiH2Cl2) and ammonia (NH3) gas are guided by a nitrogen carrier gas and reacted at 820 ° C. to grow a silicon nitride film of 300 nm thereon to form a two-layer insulating film 103. To do. Using TEOS and ozone (O 3) as reaction gases, a silicon oxide material 104 is grown and flattened by chemical mechanical polishing (CMP). By this step, the silicon substrate 100 having the silicon island 107 surrounded by the DTI having a depth of 50 μm filled with the insulating material of silicon oxide was formed.

  FIG. 4 is a schematic cross-sectional view of the DTI 110 in which the oxide film as a mask is set to recede in the RIE condition setting so that the opening is widened from the bottom surface.

  Through the above steps, isolation DTI (106, 110) by deep grooves was formed. By this DTI, the inner silicon island surface 105 and the outer surface 101 of the DTI are insulated and separated. An isolation DTI that is 100 times deeper than the general depth of 400 nm of STI was fabricated to physically separate the surfaces.

To this, phosphorus was ion-implanted at ³ × 10 ¹⁴ / cm ² and annealed at 900 ° C. for 30 minutes to form electrodes of the n-type diffusion layer 1 (108) and the n-type diffusion layer 2 (109). It was confirmed that a voltage was applied from the n-type diffusion layer 2 to electrically insulate and separate even at 100V.

  By surrounding with DTI, a silicon surface region insulated from the substrate surface outside the DTI by at least 100 V or more could be formed on the same silicon substrate.

  There are practical variations of DTI. Examples of changes in the planar arrangement are shown in Examples 1 and 2 below. Examples of changes in the process procedure are shown in Examples 3 and 4 below. Example 5 in which DTI is used to separate chips in the sense of dicing is shown below in Example 5.

  In the sixth embodiment, an embodiment is shown in which an island chip surrounded by DTI and an outer chip are connected by a wiring that crosses the DTI. Examples of structures in which metal contamination from the through electrode is blocked by a thick DTI oxide film are shown in Examples 7, 8, 9, and 10 below. In addition, examples of stacking chips of these substrates are shown in Examples 11, 12, and 13 below.

<Example 1>
An example of DTI arrangement will be described with reference to FIG.
FIG. 5 schematically shows a top view of a wafer having a second DTI 2 (206) containing DTI 1 (204) and a cross section of (B) X2X2.
The width W of DTI 1 and 2 (204, 206) was 5 um and the same. The depth D of 2 of DTI is 50 um. Although the depths of DTI 1 (204) and DTI 2 (206) are shown in the same way, the depths obtained by actual etching are not exactly the same. Silicon island 1 (205) made by DTI 1 (204) and silicon island 2 (207) made by DTI 2 (206) are separated by DTI 1 (204). Silicon island 2 (207) created by DTI 2 (206) is separated from adjacent silicon island 208.

<Example 2>
An example of DTI arrangement will be described with reference to FIG.
FIG. 6 schematically shows an embodiment in which DTIs are densely arranged. Here, the width w of the DTI 304 is 5 μm, and the side I of the silicon island 305 is 5 μm. The depth D is 50 um. The interval between the DTI and the adjacent DTI is also 5 um. The DTIs (301, 302, 303, 304) in the X3X4 cross section are separated by the silicon surface 307, and the silicon islands inside the DTI are also separated from each other. Although the DTI is drawn as if it was etched vertically, the inclination can be freely adjusted by the RIE apparatus setting.

<Example 3>
A process procedure for creating an STI after producing a DTI will be described with reference to FIGS.
An example in which a DTI is manufactured before STI is manufactured is schematically shown in FIGS. FIG. 7A is a plan view of the wafer surface on which the DTI (404, 406) is manufactured, and FIG. 7B is a schematic view of a cross section of X4X4. As shown in the drawing, a plurality of DTI 1s (404) are arranged, and a DTI 2 (406) is arranged so as to surround them. Silicon island 1 (405) surrounded by DTI 1 (404) is isolated from other corresponding silicon islands. Here, the depth D of DTI 2 (406) was 50 μm. Although the DTI is drawn at the same depth, it is not exactly the same.

  Thereafter, silicon oxidation is performed at 50 nm, and a resist pattern of STI 408 is transferred thereto in an exposure process, and the oxide film is etched. Subsequently, the silicon substrate is etched to a depth of 0.4 μm and resist ashing is performed. After cleaning, a silicon oxide film is embedded by high-density plasma CVD, and the surface is polished flat by CMP to expose silicon in the active region. The surface after the process is schematically shown in FIG. The X5X5 cross section is schematically shown in FIG. As shown, STI 408 was fabricated in silicon island 2 (407). However, the depth of the STI 405 is exaggerated and drawn.

<Example 4>
A process procedure for creating a DTI after producing an STI will be described with reference to FIGS.
FIG. 9 schematically shows the surface of the substrate on which the STI 508 is manufactured. FIG. 9B schematically shows a cross section of X5X5. Here, the surface of the silicon substrate is oxidized by 50 nm, and the resist pattern of STI 508 is transferred thereto in the exposure process, and the oxide film is etched. Subsequently, the silicon substrate is etched to a depth of 0.4 μm and resist ashing is performed. After cleaning, a silicon oxide film is embedded by high-density plasma CVD, and the surface is polished flat by CMP to expose silicon in the active region. As shown, STI 508 was fabricated on silicon surface 500. However, the depth of the STI 508 is exaggerated and drawn.

  Thereafter, the surface is oxidized again to form an oxide film 502 having a thickness of 50 nm, and a silicon nitride film 503 is grown to 100 nm thereon by a chemical vapor deposition method under reduced pressure. Further, a resist pattern 504 having a pattern of DTI 506 is transferred in an exposure process, and the silicon nitride film 503 and the oxide film 502 are etched. Subsequently, the silicon substrate 501 is etched to a depth of 50 μm. In this embodiment, an example is shown in which RIE etching conditions are selected and etching is performed so that the opening is wider than the bottom surface. The state up to here is schematically shown in FIG. After resist ashing and cleaning, the inner surface of the groove is again oxidized to a thickness of 100 nm to form an oxide film 507. For the same reason as in LOCOS, the silicon nitride film is lifted at the edge to form a small bird's beak, which is not shown here. The state up to here is schematically shown in FIG.

  In the trench, silicon oxide 509 grown from TEOS and ozone is buried. This cross section is schematically shown in FIG. The surface of the oxide film 502 is left flat by CMP, and the silicon oxide film 502 is removed by cleaning to expose the silicon surface 500 in the active region. This cross section is schematically shown in FIG.

<Example 5>
With reference to FIGS. 12 and 13, a description will be given of a process example in which a DTI is arranged at a dicing position and chip separation is performed.
FIG. 12 schematically shows an example of the arrangement in which the DTI 606 is arranged at the dicing planned position of the chip and the STI isolation is produced in the internal region of the DTI.

  FIG. 12A is a plan view, and FIG. 12B is a schematic diagram of a cross section of X6 × 6. As shown in the figure, the DTI 606 is arranged at the vertical separation position 609 and the horizontal separation position 610. An STI 608 is formed on a silicon island 607 surrounded by DTI.

  FIG. 13C shows a fabricated layer 611 of the device on the silicon island 607. The DTI is at the device chip separation position 609, and the device chip 1 (612) and the device chip 2 (613) are isolated. The device layer 611 is etched until it reaches the substrate using the resist as a mask at the isolation location, and the bottom of the trench is on top of the DTI. However, in general, since the process can be designed so that no film remains at this position, the resist mask process can be made unnecessary.

  In order to improve the reliability of the chip, the surface of the chip is covered with a protective film 614. As the protective film 614, a silicon nitride film of plasma CVD was used with a thickness of 500 nm.

  The surface of the silicon substrate 601 is attached to the support plate, and the silicon substrate 615 is polished until the oxide film at the bottom of the DTI is exposed from the back surface. When the oxide film inside the DTI is removed with the HF cleaning solution, the chips 612 and 613 are separated. Even if the oxide film cannot be completely removed, it can be broken and separated.

<Example 6>
A device in which devices inside and outside the DTI are connected by wiring will be described with reference to FIGS. 14 and 15.
FIG. 14 schematically shows an embodiment of a device chip 700 in which devices inside and outside the DTI are connected by wiring. FIG. 14A is a perspective view schematically illustrating wirings that straddle a DTI on a substrate on which the DTI is manufactured. On the surface, an epitaxial layer 701 made of DTI (706) is visible. The STI 708 is formed in the subsequent process, and the CMOS process is advanced to manufacture a device. Also, as shown in the figure, there is a silicon island 709 surrounded by DTI (706). As the wiring process proceeds, wiring 1 and wiring 2 (714) straddling the DTI are created.

Next, FIG. 14B illustrates an example of a cross section through which the device manufacturing process has proceeded. An epitaxial layer 701 having a thickness of 3 μm is formed on a high concentration p-type (P ⁺⁺ ) silicon substrate 702. The DTI 706 is manufactured at a depth of 50 μm as described above. Since the depth D = 50 μm, the DTI crosses the 3 μm epitaxial layer and goes deep into the p ⁺⁺ substrate. In addition, in the figure, since it has drawn so that the whole may be seen, the relative dimension of a figure differs from actual.

  Thereafter, the STI 708 is manufactured by the method described above. In accordance with a general CMOS process, an n-well 704 and a p-well 705 are formed by a masking method twice. Since the transistor 718 on the silicon island 709 and the transistor 717 on the chip outside the DTI are designed to operate with different power supply voltages, it is necessary to create wells with different depths.

  For this reason, in this case, the CMOS well formation step is performed twice in total for forming the deep wells (704, 705) of the silicon island 709 and the shallow wells (719, 720) in the region outside the DTI. Subsequently, a gate oxide film process is performed to manufacture a transistor gate 711. The gate material has a two-layer structure of doped polysilicon and tungsten.

  A source / drain diffusion layer is formed by self-alignment using the gate electrode pattern as a mask. It should be noted that the silicide formation process can be freely inserted depending on the design.

  An interlayer film 710 is formed and planarized by CMP to form a contact hole 712. After sputtering the TiN barrier film, the hole is filled with CVD tungsten and the surface is flattened by CMP.

  Again, an interlayer film 716 is formed thereon, and a wiring pattern groove is formed. After the TiN barrier film and Cu seed are grown by the sputtering method, the groove is filled with plating Cu. A wiring is produced by flattening by CMP.

  Through the above steps, the wiring 714 straddling the DTI and the wiring 713 within the silicon island can be simultaneously performed. In order to show that the respective wirings can be formed, they are illustrated as being in the same layer, but the arrangement is determined depending on the device design.

  FIG. 15C shows a structural example in which the back surface of the substrate is polished and the silicon island substrate 709 is insulated from the chip by the DTI 706. In the figure, the substrate 715 that has been polished and removed is indicated by a broken line. The potential of the substrate of the silicon island 709 is given by connection from the wiring layer of the device. Accordingly, it is possible to provide an insulating separation substrate in the same layer that is insulated and separated in the lateral direction.

<Example 7>
A through via by DTI will be described with reference to FIGS.
In FIG. 16, there is a diffusion layer 809 surrounded by a transistor 811 and a DTI 806 separated by STI by coexisting an STI 808 and a DTI 806, and a wiring structure is formed on them to form an upper layer of the DTI 806. Shows a structure in which a front bump 827 is formed. The pattern of DTI 806 has a width W of 10 μm and an island side I of 50 μm. As shown in FIG. The contact electrode 813 connected to the diffusion layer 809 is made flat by growing tungsten by CVD using the TiN film as a barrier and polishing the surface by CMP.

  An interlayer film 815 is grown thereon to form a groove for the wiring M1 (818), a barrier metal 821 is attached, the groove is filled with plating Cu, and polishing is performed by CMP to form the wiring M1 (818). Form.

  Then, an interlayer film 816 is grown again, a connection hole 819 is formed, and the hole is filled with a barrier metal 822 and plating Cu.

  Further, the interlayer film 817 is grown again to form a groove of the wiring M2, and the groove is filled with the barrier metal 823 and the plating Cu and polished by CMP to form the wiring M2 (820). Next, a protective film 824 of an oxide film is attached, a bump hole is opened, a Ni / Al laminated glue metal 1 (826) is grown, this is etched into a bump pattern, and a normal lead is formed thereon. Apply tin solder bumps. This is reflowed to form a round front bump 827. By this process, a device in which wiring and bumps are formed on a silicon substrate having DTI is manufactured. The above shows a simple process. When manufacturing stability such as reliability is required, an insulating film and a drilling process may be added.

  In addition, although the number of wiring layers has shown the example of two layers, it can design arbitrarily. FIG. 17 shows a process of manufacturing a through via using DTI as a back electrode. FIG. 17A shows the surface adhesion of the silicon substrate 901 with the adhesive 928 to the support plate 929 and the state where the surface is flattened by back surface polishing and chemical mechanical polishing (hereinafter referred to as CMP). In the figure, the polished silicon substrate 902 is indicated by a dotted line. Further, the remaining substrate has a DTI depth of 50 μm.

  FIG. 18B shows a process from the transfer exposure of the through via pattern to the etching of the silicon substrate 901. The back surface through electrode pattern is a hole pattern having a pattern end on the DTI 906, and silicon on the back surface is removed by etching with SF6 gas. Then, it reaches the bottom of the contact electrode 913 already formed.

  FIG. 19C shows up to the point where the resist has been removed. FIG. 20D shows a state where a TiN barrier metal 931 is attached, and a plating Cu 932 having a thickness of 20 μm and a nickel glue metal 2 (933) are attached.

  FIG. 21E shows the process up to planarization removal of Cu on the back surface by CMP. A DTI through-via back surface electrode 935 surrounded by DTI 906 is completed. The back electrode has a concave shape depending on the thickness of the plated Cu. When the probe needle was applied from the back side, the electrode was surrounded by DTI, and thus showed an insulation characteristic of 500 V or more with respect to the substrate.

<Example 8>
The collective DTI through via will be described with reference to FIG.
FIG. 22 is a schematic cross-sectional view of a structure in which DTI through vias are assembled. One DTI 1006 has a width W of 5 μm, an island side length I of 10 μm, and a space between the DTIs of 5 μm. In the same process as in Example 7, a DTI through via was manufactured, and an aggregate DTI through via 1035 was manufactured.

<Example 9>
A device chip having an island chip isolated by DTI and a DTI through via will be described with reference to FIG.
FIG. 23 shows an example in which the chip is polished by CMP until the bottom of the DTI comes out. Here, FIG. 23A is a plan view seen from the back surface of the chip. FIG. 5B is a cross-sectional view of X11X11. As shown in the figure, a silicon island chip 2 (1102) surrounded by a DTI (1106) having a width of W5um is formed in the chip 1 (1101), and the chip 2 is isolated from the chip 1 by the DTI 1106. Has been. The withstand voltage is 500V or more.

  The chip 2 includes a MOS transistor 1111 having a withstand voltage of 400 V capable of switching a large power, and is connected to a common drain 1112. The current collected in the drain is connected to the through via back electrode 1135 insulated from the chip 2 by the DTI (1107) through the multi-contact hole 1113, and power is supplied from this. In the chip 1, a 24V operation transistor for control is arranged and connected to the gate of the high power MOS transistor. The DTI through via is connected to the heat sink and also plays a role of cooling.

<Example 10>
A device chip having a structure of a set DTI through via surrounded by DTI will be described with reference to FIG.
FIG. 24 is a schematic cross-sectional view of a device chip having a DTI that surrounds them in addition to the collective through via electrodes fabricated by DTI. The width W of one DTI (1206) was 5 μm, the side I of the island was 10 μm, and the space between the DTIs was 5 μm. In the same process as in Example 7, a DTI through via was manufactured, and an aggregate DTI through via 1235 was manufactured. The width W of the DTI 1207 surrounding them was 10 μm, and one side I of the island was spaced 5 μm from the collective through via. The collective DTI through vias are connected by the same number of contact holes and wiring vias, and are connected to a front bump 1227 formed of one lead tin solder.

<Example 11>
An example in which two chips each having a DTI through via are joined by a bump will be described with reference to FIG.
FIG. 25 shows an example of a device in which chip 1 (1301) and chip 2 (1302) are laminated by bonding the DTI through via electrode shown in FIGS. The front bump 1328 of the chip 2 is connected with the DTI through via back electrode 1 (1335) of the chip 1 (1301) and the resin 1330 interposed therebetween. The DTI through electrode is connected and maintains a dielectric breakdown voltage of 500 V or higher with respect to the chip 1 and the chip 2. A front bump 1 (1327) appears on the front surface, and a DTI through via back electrode 2 (1336) appears on the rear surface. By repeating this, a further stacked device chip is formed.

<Example 12>
An example in which two chips having collective through vias are joined by bumps will be described with reference to FIG.
FIG. 26 shows an example of a device in which the DTI through via electrode shown in FIG. 22 and the lead tin front bumps on the DTI through via electrode are bonded to each other and chip 1 (1401) and chip 2 (1402) are stacked. The collective front bump 1428 of the chip 2 is connected with the collective DTI through via back electrode 1 (1435) of the chip 1 (1401) and the resin 1430 interposed therebetween. The DTI through electrode is connected and maintains a dielectric breakdown voltage of 500 V or higher with respect to the chip 1 and the chip 2. The collective front bump 1 (1427) appears on the front surface, and the collective DTI through via back electrode 2 (1437) appears on the back surface. By repeating this, a further stacked device chip is formed.

<Example 13>
An example in which two chips having more through vias than front bumps are joined will be described with reference to FIG.
FIG. 27 shows an example of a device in which the DTI through via electrode shown in FIG. 24 and the lead tin front bumps on the DTI through via electrode are bonded to each other and chip 1 (1501) and chip 2 (1502) are stacked. The collective front bump 1528 of the chip 2 is connected with the collective DTI through via back electrode 1 (1535) of the chip 1 (1501) and the resin 1530 interposed therebetween. The DTI through electrode is connected and maintains a dielectric breakdown voltage of 500 V or higher with respect to the chip 1 and the chip 2. The collective front bump 1 (1527) appears on the front surface, and the collective DTI through via back electrode 2 (1537) appears on the back surface. By repeating this, a further stacked device chip is formed.

  In addition, although the disclosure that the stacking is performed with the substrate chip has been performed, it is possible to freely stack the substrate wafers and then perform dicing in order to improve the process efficiency.

  As described above, according to the present embodiment and the example, a silicon oxide film having a width of 1 μm or more and a deep groove of 1 μm or more is formed, and the silicon oxide film is buried in the groove, so that even a substrate having crystal defects is 500 V or more. Achieved withstand voltage isolation. Thereby, it becomes possible to mount the power device on the same substrate as the existing device that operates at high speed by the shallow trench isolation. Further, by filling a cavity from which silicon surrounded by a thick isolation material was removed with metal, a through-substrate electrode that prevented diffusion of metal contamination was formed, which enabled the lamination of the substrate. This makes it possible to supply wiring from the power source through the substrate, and to realize a device in which power feeding that also serves as a heat sink, a high-power device that operates therewith, and a high-speed and highly-integrated device are stacked.

  According to the present invention, a silicon substrate having a structure of a silicon island substrate surrounded by a deep groove filled with an insulating material and insulated and separated from the surrounding substrate even at a voltage higher than 100 V can be used. As a result, devices operating at different potentials or voltage regions can be mounted on one chip substrate. For example, the present invention makes it possible to manufacture a device chip in which a power control device that operates at a voltage range of 100 V or 1000 V and a device that performs high-speed control, storage, or calculation are mounted together. One-chip ICs such as automobile control, power generation and transformation systems, household products that directly control 100V power with one chip, and inverters that convert 0.6V DC power generated by solar cells into AC 100V power as input Power conversion is possible. In addition, by making a large power IC with large heat generation in the silicon island, the DTI insulator can insulate and stabilize the operation of the surrounding low voltage IC, so the function of high power and signal processing is especially good. Is suitable for the design of a one-chip IC in which is mounted together.

  The embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to the embodiments, and includes designs and the like that do not depart from the gist of the present invention.

It is a figure which shows the MOS structure when the cross section of the silicon substrate in the test sample of the oxide film defect by COP, the thermal oxide film is thin, and the thermal oxide film is sufficiently thick. It is a schematic diagram of the model which blocked metal contamination with the deep filling oxide film. FIG. 6 is a plan view of a silicon substrate having deep trench isolation (DTI) embedded with an insulator and a cross-sectional view taken along X1X1 of the plan view. It is a cross-sectional schematic diagram of the board | substrate with DTI whose opening part is wider than a bottom face. FIG. 6 is a plan view of a silicon substrate having a second DTI 2 that encloses a DTI 1 and a cross-sectional view taken along X2X2 of the plan view. FIG. 6 is a plan view of a silicon substrate on which two or more DTIs are arranged and a cross-sectional view of X3X3 in the plan view. It is the top view of the silicon substrate which produced DTI before STI production, and sectional drawing of X4X4 of a top view. It is the X5X5 sectional view of the top view of a silicon substrate which produced STI after producing DTI, and a top view. FIG. 5A is a plan view of a silicon substrate on which an STI is manufactured before a DTI manufacturing process and a cross-sectional view taken along X5X5 in the plan view. FIG. 6 is a cross-sectional view of a DTI trench etch and a cross-sectional view of oxidation of a DTI trench in DTI fabrication step 1 after fabrication of an STI. FIG. 2 is a diagram showing a cross section of a DTI TEOS-O3 silicon oxide at the end of CVD in a DTI manufacturing step 1 after manufacturing an STI and a cross section in which a TEOS-O3 silicon oxide is removed by CMP to form a flat active layer. . It is the X6X6 sectional view of the top view of a silicon substrate which has arranged DTI in the dicing position of the substrate which arranged DTI in the dicing position of a chip, and a top view. It is a figure which shows the chip | tip separated by X6X6 sectional drawing of the board | substrate by which the back surface grinding | polishing was carried out in the board | substrate which has arrange | positioned DTI in the chip | tip dicing position, and DTI. It is a figure which shows the example of the cross section of the device which has the wiring and the DTI isolation | separation silicon island which are going to straddle the DTI of the device chip | tip with which the device inside and outside of DTI was couple | bonded by wiring. FIG. 5 is a diagram showing an example of a cross section of a device chip in which a back surface of a silicon substrate is polished and removed to the bottom of the DTI in a device chip in which devices inside and outside the DTI are coupled by wiring. It is the cross-sectional schematic diagram of the model device which built the transistor and wiring on the board | substrate with DTI, and produced bump. It is the figure which showed the process to front plate adhesion | attachment to a support plate, back surface grinding | polishing, and CMP in the production process of the penetration via by DTI. It is the figure which showed the process to transcription | transfer exposure of a penetration via pattern, and a silicon substrate etch in the formation process of the penetration via by DTI. It is the figure which showed the process of resist peeling in the manufacturing process of the penetration via by DTI. It is the figure which showed the process to Cu metal plating and glue metal 2 in the formation process of the penetration via by DTI. It is the figure which showed the process to CMP of Cu of a back surface in the manufacturing process of the penetration via by DTI. It is a cross-sectional schematic diagram of the structure of the aggregate DTI through via. It is the figure which showed the cross-sectional schematic diagram of the chip | tip back surface and X11X11 of a device chip which has a chip | tip which was insulated and separated by carrying out back surface grinding | polishing to the bottom of DTI. It is the figure which showed the cross-sectional schematic diagram of the structure of the assembly | attachment DTI through-via enclosed by DTI. It is a cross-sectional schematic diagram of the structure which laminated | stacked two chips | tips of the single DTI penetration via by the bump. It is a cross-sectional schematic diagram of the structure which laminated | stacked 2 chip | tips of the assembly | stacking DTI penetration via by the bump. It is a cross-sectional schematic diagram of a structure in which two chips having more through vias than the number of front bumps are stacked. It is the figure which showed the V groove isolation, the dielectric material isolation, LOCOS, U groove isolation, and STI (Shallow Trench Isolation) which are the prior art examples of the device isolation technique. It is the figure which showed the typical cross section of the prior art example of the CMOS device isolate | separated by STI. It is a figure which shows the process of the prior art which makes a groove by gas dicing. It is a model figure of the movement of the metal which contaminates a silicon substrate. It is a figure which shows the prior art regarding a penetration electrode.

Explanation of symbols

100, 201, 401, 501, 601, 801, 901, 1001, 1101, 1
201 ... Silicon substrate 101,307 ... DTI outer surface
103, 803, 903 ... Insulating film (silicon nitride film / silicon oxide film)
104 ... Silicon oxide 105 ... Silicon island surface 106, 301, 302, 303, 304, 506, 606, 706, 806, 906
, 1006, 1106, 1107, 1206, 1207, 1306, 1307, 143
6, 1506, 1507 ... DTI
107, 208, 602, 607 ... Silicon island 108 ... DTI n-type diffusion layer 2
109, 809 ... n-type diffusion layer 2 of silicon island
110 ... DTI with opening wider than bottom
204, 404 ... 1 of DTI
205, 305, 405 ... Silicon Island 1
206, 406 ... 2 of DTI
207, 407 ... Silicon Island 2
408, 508, 608, 708, 808, 908, 1008, 1108, 1108,
1208 ... STI
DESCRIPTION OF SYMBOLS 500 ... Silicon surface 502 ... Silicon oxide film 503 ... Silicon nitride film 504 ... Photoresist 507 ... Thermal oxide film 509 ... Silicon oxide grown from TEOS and ozone 609 ... Chip Vertical dicing position 610: Horizontal dicing position of chip 611: Device manufactured layer 612: Device chip 1
613 ... Device chip 2
614: protective film 615 ... polished silicon substrate 700 ... device chip 701 ... epitaxial layer 702 ... P ++ silicon substrate 704 ... n well 705 ... p well 709 ... Silicon island in DTI 710, 716, 814, 815, 816, 817 ... interlayer film 711, 811, 911, 1011, 1211 ... transistor 712, 813, 913 ... contact electrode 713 ... in silicon island Wiring 714 ... Wiring across DTI 715 ... Polished substrate 717 ... Chip transistor 718 ... Silicon island transistor 719 ... Shallow n-well 720 ... Shallow p-well 810 ..Gate oxide film 812 ... Silicon nitride film 818, 918 ... wiring M1
819, 919, 1019 ... connection hole 820, 920, 1020 ... wiring M2
821, 822, 823, 921, 922, 923, 1023 ... barrier metal 824 ... protective film 825, 925, 1025, 1225 ... device region 826, 926, 1026 ... glue metal 1
827, 927, 1027, 1227 ... Front bump 902 ... Polished and removed silicon substrate 928 ... Adhesive 929 ... Support plate 930 ... Pattern resist of penetrating back electrode 931 ... Barrier Metal 932 ... Plating Cu
933 ... Glue metal 2
935, 1135... DTI through via back surface electrode 1101, 1301, 1401, 1501... Chip 1
1102, 1302, 1402, 1502... Chip 2
1035, 1235... Back electrode of aggregate DTI through via 1112... Drain 1111... High power transistor 1113 .. Multi-contact electrode 1327, 1527.
1328, 1528 ... Front bump 2
1330, 1430, 1530 ... Resin 1335 ... DTI through via back electrode 1
1336... DTI through via back electrode 2
1435, 1535... Back electrode 1 of collective DTI through via
1437, 1537 ... Back electrode 2 of collective DTI through via
1427 ... Collective front bump 1
1428 ... Collective front bump 2

Claims (19)

  Before manufacturing a transistor device on the surface of a silicon substrate, a groove having a depth of 1 μm or more in which an electrical insulator is embedded is formed, and an island surrounded by the groove is insulated and separated by the groove. A silicon substrate.   Before manufacturing the transistor device on the surface of the silicon substrate, there is a groove having a depth of 1 μm or more and a width of 1 μm or more embedded with an electrical insulator, and the groove depth surrounds a shallow trench isolation of 0.5 μm or less. The silicon substrate according to claim 1.   2. The silicon substrate according to claim 1, wherein a DTI is provided at a planar position of a scribe line that separates the first chip and the second chip.   The silicon substrate according to claim 1, wherein the groove further forms a groove inside thereof.   The silicon substrate according to claim 1, wherein a plurality of the grooves having different depths are provided.   6. The silicon substrate according to claim 5, wherein the plurality of grooves are gathered at a distance equal to or less than one outer dimension thereof.   7. The silicon substrate according to claim 1, wherein the diameter of the substrate is 300 mm.   The method for manufacturing a device using a substrate according to claim 1, wherein the STI is manufactured after the groove is formed.   A device manufactured by the method according to claim 8 using the substrate according to any one of claims 1 to 7.   A device manufactured using the substrate according to claim 1, wherein there is a wiring that straddles the groove.   A device characterized in that a substrate inner surface surrounded by a groove and an outer substrate in the groove are electrically insulated and separated by polishing the back surface of the substrate.   A through-back electrode that is electrically connected to a wiring formed on the surface of the substrate is manufactured by embedding a metal material in a cavity formed by etching and removing the inner side silicon substrate insulated and isolated by the groove. Item 12. The device according to Item 11.   13. The device according to claim 12, further comprising a plurality of through-back electrodes that are gathered at a distance shorter than the outer shape of the single groove.   14. The device according to claim 12, further comprising a groove surrounding the plurality of assembled through-back electrodes according to claim 13.   The device according to any one of claims 12 to 14, further comprising a front bump that is electrically connected to the through-back electrode on the surface of the substrate.   The device which laminated | stacked the board | substrate carrying the device in any one of Claim 12-14 which has a front bump electrically connected with the said penetration back electrode on the substrate surface.   The device according to any one of claims 12 to 14, wherein the device has a front bump on the surface of the substrate that is electrically connected to the through back electrode, and the number of bumps is smaller than the number of the through back electrodes.   The device according to claim 11, wherein the first and second substrate chips are formed on the same substrate in which the inner portion and the outer portion of the groove are electrically insulated. A device having a through back electrode. A test method comprising conducting an electrical test of a device on a substrate surface with an electrode formed on the back surface of the substrate.

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