JP2009294990A - Image processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve arbitration between transfer processing while reducing the overall transfer time by reducing the number of times of loading raw materials from a transfer source memory. <P>SOLUTION: An image processing system includes a plurality of types of processing in the transfer process of raw materials, and using different processing according to the characteristics of raw materials. A display list analyzing part 2b analyzes a display list 10, and successively outputs instructions for transferring the respective raw materials. Each of transfer processing parts 2c to 2e designated by the transfer instruction from the display list analyzing part 2b, outputs a request for acquiring the raw materials related to the transfer instruction. An arbitration part 5 which manages the acquisition request decides whether or not the raw materials related to the acquisition request is stored in a cash memory 4, and loads the raw materials related to the acquisition request from the NAND memory 3 to the cache memory 4 as necessary. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image processing system that performs image processing using a plurality of types of materials stored in a transfer source memory based on an instruction from a host device.

  For example, Patent Document 1 discloses an image processor that performs image processing using a material (object) stored in a transfer source memory based on a display list issued by a CPU (Central Processing Unit) that is a host device. Has been. The transfer circuit included in the image processor reads a compressed or uncompressed material stored in the transfer source memory in accordance with a series of transfer instructions issued by the CPU, and writes the read material into the transfer destination memory in the image processor. When the material to be transferred is compressed, the decompression circuit in the transfer circuit performs decompression processing, and the decompressed material is written in the transfer destination memory. Further, in this Patent Document 1, when a material used in a certain drawing process is required again in a subsequent drawing process, the material is cached in the transfer destination memory without being erased from the transfer destination memory. The points to be disclosed are also disclosed.

  Patent Document 2 discloses an associative memory device that shortens the load time of a program or data to a cache memory and reduces the deterioration of execution performance. On the other hand, Patent Document 3 discloses an image processor including a FIFO memory that temporarily stores a series of instructions (commands) generated by a host processor (host CPU). The instructions stored in the FIFO memory are read from the oldest in time sequence in the order (input order) written in the FIFO memory, and the drawing processing corresponding to this is sequentially executed.

Japanese Patent No. 3970291 Japanese Patent Laid-Open No. 2001-307489 JP 2001-299898 A

  Incidentally, in an image processing system such as that disclosed in Patent Document 1, there is a growing market need for using a NAND memory that is cheaper than a normal ROM as a transfer source memory for storing a source material. A NAND memory is a memory having a structure in which a plurality of storage elements (memory cells) are connected in series. As a typical example, a NAND flash memory that controls the amount of carriers (electrons) injected into a floating gate according to data is used. Are known. However, the NAND memory has a drawback that the sequential load following the load is relatively fast, but the initial load itself has a large penalty as a characteristic resulting from the connection structure. For this reason, if loading of individual materials corresponding to the transfer command is performed uniformly each time, a load penalty becomes apparent as a bottleneck in drawing processing.

  In recent years, with the increasing functionality and added value of image processing systems, the materials handled by the system are becoming more diversified, such as 3D still images and videos, as well as 2D still images and movies. is there. When handling these plural types of materials, the processing contents in the transfer process differ for each material due to the difference in the characteristics of the material. For example, when transferring a losslessly compressed material, a process of decompressing the material is performed in a reverse process to the lossless compression. When transferring a lossy-compressed material, a process of decompressing the material is performed in a process reverse to that of the lossy compression. In addition, even in the same lossless compression (or the same lossy compression), it is conceivable to use a plurality of types of compression algorithms depending on the material. As described above, when a plurality of types of processes coexist in the transfer process of the material and the process is properly used according to the characteristics of the material, some mediation is performed between these processes in order to improve the throughput of the entire process. There is a need.

  Therefore, an object of the present invention is to reduce the number of times the material is loaded from the transfer source memory in an image processing system in which a plurality of types of processing coexist in the material transfer process and use the processing according to the characteristics of the material. It is to enable arbitration between transfer processes while shortening the transfer time.

  Another object of the present invention is to further promote the multi-function and high added value of such an image processing system.

  In order to solve such a problem, the present invention has a cache memory, a display list analysis unit, a plurality of transfer processing units, an arbitration unit, and a drawing processing unit, and transfers based on an instruction from a host device. Provided is an image processing system for performing image processing using a material stored in an original memory. The cache memory is connected to the transfer source memory via the load bus. The display list analysis unit analyzes the display list and sequentially outputs transfer instructions for each material. This display list is issued by the host device, and the transfer commands for materials necessary for drawing are described in time series. A plurality of transfer processing units are provided corresponding to the type of material, and each is connected to the cache memory via a read bus. When the transfer processing unit is specified by the transfer command from the display list analysis unit, the transfer processing unit outputs an acquisition request for the material specified by the transfer command. In addition, when the material related to the acquisition request is stored in the cache memory, the transfer processing unit performs processing according to the characteristics of the material on the material acquired by accessing the cache memory. The arbitration unit manages acquisition requests from each of the transfer processing units. Further, the arbitration unit reads the material related to the acquisition request that is not stored in the cache memory from the transfer source memory and stores the material in the cache memory according to whether or not the material related to the acquisition request is stored in the cache memory. . The drawing processing unit draws an image using the material processed by each of the transfer processing units.

  In the present invention, the storage area of the cache memory is preferably divided into a plurality of cache blocks. In this case, the arbitration unit may manage block occupancy rights for each cache block in order to exclusively control access to the cache block by each transfer processing unit. Further, the arbitration unit, when the material related to the acquisition request with one of the transfer processing units as a request source is not cached in the cache memory, the request source with respect to any of the empty cache blocks to which block occupancy rights are not granted. A block occupancy right may be granted to In addition, when the material related to the acquisition request is cached in the cache memory, the arbitration unit may grant a block occupancy right to the request source regarding the cache block in which the material related to the acquisition request is stored. Furthermore, when the material related to the acquisition request is acquired by the request source, the arbitration unit may release the block occupancy right of the request source regarding the cache block in which the material related to the acquisition request is stored.

  In the present invention, the arbitration unit can manage the load bus occupancy right for the load bus in order to exclusively control the reading of the material from the transfer source memory based on the acquisition request from each of the transfer processing units. preferable. In this case, the arbitration unit, on the condition that the load bus occupation right other than the request source is not granted when the material related to the acquisition request with one of the transfer processing units is not cached in the cache memory A load bus occupation right may be given to the request source. The arbitration unit may not grant the load bus occupation right to the request source when the material related to the acquisition request is cached in the cache memory. Furthermore, the arbitration unit may release the load bus occupation right of the request source when the material related to the acquisition request from the request source is read from the transfer source memory and stored in the cache memory.

  In the present invention, the arbitration unit preferably manages the read bus occupancy right for the read bus in order to exclusively control the reading of the material from the cache memory by each of the transfer processing units. In this case, the arbitration unit reads the material related to the acquisition request from the transfer source memory when the material related to the acquisition request with one of the transfer processing units as a request source is not cached in the cache memory, and The read bus occupation right may be granted to the request source on the condition that it is stored in Further, when the material related to the acquisition request is cached in the cache memory, the arbitration unit may grant the read bus occupation right to the request source without reading the material related to the acquisition request from the transfer source memory. Further, the arbitration unit may release the read bus occupation right of the request source when the material related to the acquisition request stored in the cache memory is acquired by the request source.

  In the present invention, the transfer source memory is preferably a memory having a structure in which a plurality of memory cells are connected in series, as represented by a NAND memory. In addition, each of the transfer processing units acquires display list subroutines, decompression of lossless compressed image data, decompression of lossy compressed image data, or vertex data defining a three-dimensional figure as processing for a material Perform the process.

  In the present invention, it is preferable that the display list analysis unit pre-reads and analyzes the transfer command described in the display list. In this case, the display list analysis unit manages the remaining capacity of the transfer source memory that is changed by storing the material processed by each of the transfer processing units in the transfer destination memory, and sets the current remaining capacity of the transfer destination memory. Accordingly, the output timing of the transfer instruction may be controlled.

  According to the present invention, a cache memory is interposed between the transfer source memory and the transfer processing unit, and at the time of a cache hit, the material already existing in the cache memory is read without loading the material from the transfer source memory. The Since the display list issued by the host device does not interrupt the transfer of the material due to its nature, the number of times of loading the material from the transfer source memory can be reduced by assuming this. In addition, the material read from the cache memory is subjected to predetermined processing by the transfer processing unit that has issued the material acquisition request. The mediation unit manages which transfer processing unit is the request source that issued the material acquisition request. Therefore, even when a plurality of types of processes coexist in the transfer process of the material, the process corresponding to the material can be uniquely specified. As a result, while reducing the overall transfer time due to the cache effect, even if there is a difference in processing speed between a plurality of types of transfer processing, it is possible to easily perform these arbitrations. At the same time, even if the materials to be handled are diversified, the real-time performance of the drawing process is not impaired, so that it becomes possible to further promote the multi-function and high added value of the image processing system.

(First embodiment)
FIG. 1 is an overall block diagram of the image processing system according to the first embodiment. This image processing system is composed mainly of a CPU 1, a main memory 1 a, an image processor 2 incorporating a RAM 7, a plurality of NAND memories 3, a cache memory 4, an arbitration unit 5, and a display device 6. Yes. In the figure, the cache memory 4 and the arbitration unit 5 are externally attached to the image processor 2. However, these may be incorporated in the image processor 2, and the image processor 2 including the NAND memory 3 may be used. It may be in a form built in. Furthermore, the function of the CPU 1 that is the host device can be incorporated in the image processor 2.

  The CPU 1 as the host device issues a display list 10 in which a series of transfer instructions to be executed by the image processor 2 are described in time series. In the display list 10, the image processing procedure is defined by a series of commands described in time series. This display list 10 is different from the conventional display list 10 in that it does not completely define the processing procedure by itself, but becomes complete only when linked with external information. In order to enable such cooperation, a jump instruction is newly added as an instruction that can be described in the display list 10. By describing a jump instruction in the display list 10, a subroutine described later is referred to as external information in the jump portion in which the jump instruction is described. The display list 10 output from the CPU 1 to the CPU bus is supplied to the image processor 2 indirectly or directly via the main memory 1a. The display list 10 is updated as needed by the CPU 1, for example, every frame. Like the CPU 1, the main memory 1a is connected to the CPU bus, and stores and holds the display list 10 according to the designation of the CPU 1.

  The image processor 2 performs image processing using materials such as image data and a subroutine of the display list 10. Here, a large amount of image data, which is a kind of material, exists in a compressed format or an uncompressed format, and data read from the transfer source memory according to the designation of the display list 10 is transmitted via the buses 8 and 9 to the image processor. 2 is taken in. On the other hand, a subroutine, which is a kind of material, corresponds to external information called by the display list 10 (main routine) described above, and defines a procedure of image processing by a series of commands described in time series. This subroutine is described in the same description format as the display list 10. In the present embodiment, the subroutine is handled as fixed data (data that is not updated at any time by the CPU 1) rather than variable data (data that is updated at any time by the CPU 1). There may be a plurality of subroutines, and the one read from the transfer source memory in accordance with the designation of the display list 10 is taken into the image processor 4.

  FIG. 2 is an explanatory diagram of the display list 10. The display list 10 defines a transfer procedure of materials necessary for drawing an image of one frame, and a transfer command is described for each line L (command unit) from the top to the bottom of the list. One transfer command is mainly composed of “material name”, “route”, “size (after development)”, and “ROM address”.

  Data transfer from a transfer source memory storing image data as a source is performed with a significant group as one unit. In this specification, this group serving as a transfer unit is referred to as “material”. A material is a data transfer unit and can also be a data erasure unit when stored in a transfer destination memory. In the present embodiment, there are the following three types of materials handled by the image processor 2.

(Material A) Subroutine of Display List 10 In this embodiment, a three-dimensional drawing command list is used as an example of a subroutine. In this command list, a 3D drawing command using vertex information defining a 3D figure as a parameter is described in the same description format as the display list 10. The vertex information defines vertex coordinates (X, Y, Z) and the like of a polygonal polygon (for example, a triangular polygon) that is a basis for generating a three-dimensional image. This subroutine is transferred to the display list analysis unit 2b via the bus A shown in FIG. 1 by path designation (path = A) by a transfer command (stored in the RAM 7 by option designation of the display list 10). In some cases). The reason why the vertex information is made into a display list instead of the data itself is to suppress the size of the display list 10. In general, in order to perform three-dimensional drawing, vertex information (three-dimensional coordinates, etc.) that defines a three-dimensional figure is required, but the amount of information increases dramatically as the figure becomes more complex. Therefore, it may be more efficient to manage vertex information that tends to have an enormous amount of information separately from the display list 10. The vertex information has a property that it can be used without being changed because it is data unique to a figure. In view of such characteristics, even if the vertex information is treated as fixed data (data that is not updated at any time by the CPU 1) instead of variable data (data that is updated at any time by the CPU 1), the flexibility of the processing contents is not impaired. There may be a plurality of subroutines of the display list 10.

(Material B) Reversibly Compressed Image Data An example of reversibly compressed image data is a still image. Moreover, there is no restriction | limiting in particular in a reversible compression method, Arbitrary things can be used among well-known methods. This lossless compressed data is expanded in the transfer destination memory via the bus B shown in FIG. 1 by the path designation (path = B) by the transfer command. The lossless compressed data decompression unit 2d connected to the bus B decompresses and outputs the input lossless compressed data by a process reverse to the compression.

(Material C) Losslessly compressed image data An example of lossy compressed image data is a moving image. The lossy compression method is not particularly limited, and any of known methods can be used. This lossy compressed data is expanded in the transfer destination memory via the bus C shown in FIG. 1 by the path designation (path = C) by the transfer command. The irreversible data decompression unit provided on the bus C decompresses and outputs the input irreversible compressed data in a process reverse to the compression.

  The “size” in the transfer command indicates the data amount (data size) after the material to be transferred is expanded. That is, the material A is the data amount of the subroutine, and the reversible / irreversible compression data of the materials B and C is the data amount after decompression. “Size” is used for managing the remaining capacity of the material development area secured in the transfer destination memory. The “ROM address” in the transfer command is the storage address of the transfer source memory in which the material (source) to be transferred is stored. For example, the transfer command for the first line (L = 1) in the display list 10 indicates that the material name “A-1” (“A”) stored in the ROM address “ADD1” belongs to the type of subroutine. This means that the subroutine acquisition unit 2c is acquired via the existing bus “A” and the expanded size is “0 × 100”. Although omitted in FIG. 2, the display list 10 includes a drawing command for instructing the processing content of the drawing processing unit 2h in addition to the transfer command as described above.

  For example, a NAND flash memory can be used as the plurality of NAND memories 3 and plays a role as a transfer source memory for storing a source material. The NAND memory 3 stores a large number of the above-described three types of materials A to C in a compressed format or an uncompressed format. The material specified by the “ROM address” in the transfer instruction is loaded from the NAND memory 3 to the cache memory 4 except for a cache hit described later, and after loading, the cache memory is selected by any of the transfer processing units 2c to 2e. 4 leads. A RAM 7 (Random Access Memory) plays a role as a transfer destination memory for storing the developed material, and is built in the image processor 2 in this embodiment. In this RAM 7, a material development area for temporarily storing the developed material and a frame buffer for storing a display image of one frame to be displayed on the display device 6 are secured in a logically separated state. Has been.

  The cache memory 4 is provided to alleviate the load penalty, which is a drawback of the NAND memory 3, and to reduce the performance difference from the image processor 2. The cache memory 4 is connected to each NAND memory 3 via a load bus 8, and is connected to a bus interface 2 f in the image processor 2 via a read bus 9 separate from the load bus 8. ing. The cache memory 4 is configured by a high-speed SRAM (Static Random Access Memory), and the storage area is divided into a plurality of cache blocks BL (hereinafter simply referred to as “block BK”). Data stored in the cache memory 4 is managed in units of blocks. Although details will be described later, in addition to managing the cache memory 4, the arbitration unit 5 performs data transfer (load) from the NAND memory 3 to the cache memory 4 via the load bus 8 and transfer processing from the cache memory 4. Data transfer (read) to the units 2c to 2e via the read bus 9 is controlled. These loads and reads can be performed in parallel.

  The image processor 2 includes a display list analysis unit 2b, a plurality of transfer processing units 2c to 2e provided corresponding to the type of material, a bus interface 2f, a memory interface 2g, and a drawing processing unit 2h. The main component is the RAM 7. The display list analysis unit 2b acquires the display list 10 issued by the CPU 1 and analyzes the description content. Then, an instruction based on the analysis result is output to the transfer processing units 2c to 2e and the drawing processing unit 2h. Here, there are two paths through which the display list analysis unit 2b acquires the display list 10, and one of the acquisition paths is selected according to the designation described in the display list 10. However, path switching is prohibited during execution of the mode.

  FIG. 3 is a diagram showing a display list acquisition path in the first mode. The display list 10 is constructed and stored in the main memory 1a by the CPU 1 in accordance with the contents of the program. The display list analysis unit 2b acquires the display list 10 stored in the main memory 1a via the CPU bus, and analyzes the description content of the acquired display list 10. When the jump instruction in the description content is extracted, the display list analysis unit 2b acquires the subroutine 12 stored in the NAND memory 3, and analyzes the subroutine 12 as a part of the display list 10.

  FIG. 4 is a diagram illustrating a display list acquisition path in the second mode. In this case, the display list 10 issued by the CPU 1 is taken into the image processor 4 via the CPU bus and stored in the internal RAM 7. Then, the display list analysis unit 2b acquires the display list 10 stored in the RAM 7, and analyzes the description content of the acquired display list 10. At this time, if a jump instruction is extracted, the subroutine 12 is called as in the first mode.

  FIG. 5 is a flowchart of list analysis processing in the display list analysis unit 2b. This list analysis process is executed every time the display list 10 is updated.

  First, in step 1, the display list 10 is acquired by either the first mode or the second mode described above. Next, in step 2, a line variable L for specifying a line to be processed is set to 1 (initial value). L = 1 indicates that the line to be processed is the line described at the top of the display list 10.

  In step 3, the transfer instruction for the line designated by the line variable L is read. In the example of FIG. 2, when L = 1, “material name” = A−1, “path” = A, “size” = 0 × 100, “ROM address” = ADD1 described in the first line is read. It is.

  In step 4, the current remaining capacity relating to the material development area secured in the RAM 7 as the transfer destination memory is confirmed. Naturally, the remaining capacity of the material development area decreases as the material is expanded, and increases as the material is erased (including releasing the area). The display list analysis unit 2b manages the remaining capacity that varies with time by grasping the initial size of the material development area and the “size” in the transfer command. Under such management, the remaining capacity at the present time is confirmed prior to the output of the transfer command in step 6. The reason for confirming the remaining capacity is to transfer the material without any trouble even when the capacity of the RAM 7 built in the image processor 2 is limited.

  In step 5, it is determined whether the remaining capacity is sufficient to transfer the material by comparing the remaining capacity specified in step 4 with the “size” in the transfer command. When the remaining capacity is “size” or more, even if the material related to the transfer command is immediately transferred, the transferred material cannot be stored in the RAM 7 due to insufficient capacity of the RAM 7. Therefore, in this case, after an affirmative determination in step 5, the process immediately proceeds to step 6. On the other hand, when the remaining capacity is less than “size”, if the material related to the transfer command is immediately transferred, the capacity of the RAM 7 is insufficient and the material cannot be stored in the RAM 7. . Therefore, in this case, after negative determination in step 5, the process returns to step 4, and steps 4 and 5 are repeated until the material stored in the RAM 7 is erased and a sufficient remaining capacity is secured (waiting state). ). When the remaining capacity is secured, the process goes out of the loop of steps 4 and 5 and proceeds to step 6.

  Note that the subroutine A of the material A is stored in the RAM 7 (storage mode) and is acquired by the display list analysis unit 2b without being stored in the RAM 7 (analysis mode). In the latter case, the remaining capacity determination in step 5 is unnecessary, so the process always proceeds to step 6.

  In step 6, the transfer instruction designated by the line variable L is selectively output to any of the transfer processing units 2 c to 2 e designated by the “path” in the transfer instruction. In the example of FIG. 2, the transfer instruction of L = 1 is output to the subroutine acquisition unit 2c of the path A, and the instruction content is such that the material “A-1” is acquired from the ROM address “ADD1”. Whether the output destination of the acquired material “A-1” is the RAM 7 or the display list analysis unit 2b is specified by an option of this transfer instruction. Along with the output of this transfer instruction, the remaining capacity of the RAM 7 is updated, and the “size” in the transfer instruction is subtracted from the current remaining capacity (except in the above-described material A analysis mode). When the material related to the transfer command is expanded in the RAM 7 and is used in the drawing process and becomes unnecessary, the “size” in the transfer command is added to the current remaining capacity at that time.

  In step 7, it is determined whether or not the transfer command designated by the line variable L is the last in the display list 10. If the line variable L is 1, the process proceeds to step 8 due to a negative determination in step 7. Then, after adding 1 to the line variable L, the process returns to step 3, and the transfer instruction of the second line (L = 2) is processed according to the procedure of steps 3 to 6 described above. In the example of FIG. 2, the transfer instruction of L = 2 is immediately output to the lossless compressed data decompression unit 2d of the path B. Thereafter, unless the remaining capacity of the RAM 7 is insufficient, the transfer command of each line is prefetched, such as the third line and the fourth line, and is sequentially distributed to one of the transfer processing units 2c to 2e. Such prefetching of the transfer instruction is temporarily stopped when the capacity of the RAM 7 is insufficient, and then resumed when the remaining capacity is secured. Thereby, the output timing of each transfer instruction is controlled according to the remaining capacity of the RAM 7. When the output of the transfer instruction for the last line in the display list 10 is completed, a series of processing for the display list 10 is completed according to the determination result in step 7.

  As shown in FIG. 1, the three transfer processing units 2c to 2e provided in parallel selectively operate based on a transfer command from the display list analysis unit 2b. These transfer processing units 2c to 2e are connected to the cache memory 4 via the bus interface 2f and the read bus 9, and to the RAM 7 via the memory interface 2g. The processing contents of the transfer processing units 2c to 2e perform processing according to the characteristics of the material associated with the transfer processing units 2c to 2e. However, there is usually a difference in processing time due to the difference in the processing contents. Many.

  When the subroutine acquisition unit 2c is designated by the transfer instruction from the display list analysis unit 2b, the subroutine acquisition unit 2c outputs the acquisition request for the material A related to the transfer instruction, that is, the subroutine 12, with the designation of the “ROM address”. This acquisition request is transferred to the arbitration unit 5 via the bus interface 2f. Further, when the subroutine acquisition unit 2c receives a notification from the arbitration unit 5 that the subroutine 12 related to the acquisition request is stored in the cache memory 4, the subroutine acquisition unit 2c acquires the subroutine 12 by accessing the cache memory 4, and stores the subroutine 12 in the RAM 7 And through output to any one of the display list analyzer 2b. Here, when the subroutine 12 is the above-described three-dimensional drawing command list, the subroutine acquisition unit 2c may perform sorting of vertex information set as parameters, coordinate conversion, or the like. When the output destination of the subroutine 12 is the display list analyzer 2b, the display list analyzer 2b regards the acquired subroutine 12 as a part of the display list 10 and analyzes it.

  When the lossless compressed data decompression unit 2d is specified by the transfer command from the display list analysis unit 2b, the lossless data decompression unit 2d outputs the acquisition request for the material B related to the transfer command, that is, the lossless compressed data with the designation of the “ROM address”. To do. This acquisition request is transferred to the arbitration unit 5 via the bus interface 2f. Further, when the lossless compressed data decompression unit 2 d receives a notification from the arbitration unit 5 that the lossless compressed data related to the acquisition request has been stored in the cache memory 4, the lossless compressed data decompression unit 2 d acquires the lossless compressed data by accessing the cache memory 4. This is decompressed by the reverse process of compression. The decompressed image data is stored in the RAM 7 via the memory interface 2g. Note that, when particularly specified by the transfer command, the reversible compression data decompression unit 2d performs through output without processing the input material B (in this case, the material B is raw data that is not reversibly compressed). .

  When the irreversible compressed data decompression unit 2e is designated by the transfer command from the display list analysis unit 2b, the acquisition request for the material C related to this transfer command, that is, the irreversible compressed data, is designated with the "ROM address". To output. This acquisition request is transferred to the arbitration unit 5 via the bus interface 2f. In addition, when the lossy compressed data decompression unit 2 e receives a notification from the arbitration unit 5 that the lossy compressed data related to the acquisition request is stored in the cache memory 4, the lossy compressed data is accessed by accessing the cache memory 4. Is obtained and decompressed by the reverse process of compression. The decompressed image data is stored in the RAM 7 via the memory interface 2g.

  The drawing processing unit 2h performs two-dimensional drawing processing using various materials developed in the RAM 7 based on the two-dimensional drawing command from the display list analysis unit 2b, and performs three-dimensional drawing processing based on the three-dimensional drawing command. Do. The display image for one frame generated by this drawing processing is stored in the frame buffer in the RAM 7 via the memory interface 2g. Then, the display image for one frame read from the frame buffer is transferred to the display device 6 via the memory interface 2g, whereby the image is displayed on the display device 6.

  The arbitration unit 5 uses the management table 11 to manage the acquisition requests from the transfer processing units 2 c to 2 e and the material storage state in the cache memory 4. FIG. 6 is an explanatory diagram of the management table 11. In the following description, the subroutine acquisition unit 2c is appropriately referred to as “master A”, the lossless compression data expansion unit 2d is referred to as “master B”, and the lossy compression data expansion unit 2e is appropriately referred to as “master C”.

  The management table 11 manages the block occupancy rights BLP0 to 9 for each of the blocks BL0 to BL9 in the cache memory 4, and manages the material stored therein by the entry address EA. The block occupancy rights BLP0 to 9 are used to exclusively control the access of the blocks BL0 to 9 by the masters A to C, and to the request source (one of the masters A to C) that has issued a material acquisition request. Is granted. For example, when the master A that has received the transfer instruction of L = 1 in FIG. 2 outputs an acquisition request for the material A-1, the master A in any of the empty blocks BL0 to 9 (for example, the block BL0) shown in FIG. A flag is set in the column, and the ROM address ADD1 of the material A-1 to be acquired is described in the entry address EA column. As a result, the block occupation right BLP0 for storing the material A-1 is given to the master A that is the request source of the material A-1. If all the blocks BL in the cache memory 4 are occupied, the next load bus occupation right LBP is put on standby until the block BL becomes empty.

  Further, the arbitrating unit 5 refers to the entry address EA column of the management table 11 to determine whether or not the material from the request source is cached in the cache memory 4 (cache determination). Specifically, when the entry address EA that matches the ROM address of the material related to the new acquisition request does not exist in the management table 11, the cache miss, that is, the material is not stored in the cache memory 4. It is determined to be a thing. In this case, one of the empty blocks BL to which the block occupation right BLP is not assigned is assigned as a load destination. Then, this load destination block occupation right BLK is given to the request source, and the “ROM address” indicating the storage destination of the material is described in the entry address EA column. Thereafter, the material is read from the entry address EA of the NAND memory 3 and loaded into the load destination of the cache memory 4. The request source that issued the acquisition request receives a read permission from the arbitration unit 5 upon completion of loading, and reads the material using the load destination of the cache memory 4 as the read source. The material read from the read source is expanded in the RAM 7 after being processed according to its characteristics. The arbitration unit 5 cancels the block occupancy right BLP of the load destination (read source) in which the material related to the acquisition request is stored because the material related to the acquisition request is acquired by the request source.

  On the other hand, if there is an entry address EA in the management table 11 that matches the ROM address of the material related to the new acquisition request, the cache hit, that is, the material stored in the cache memory 4 It is determined. In this case, the block BL in which the material related to the acquisition request is stored is assigned as a read source, and the read source block occupation right BLP is given to the request source. Then, the arbitration unit 5 permits the request source to read from the read source in which the material related to the acquisition request is stored without loading from the NAND memory 3. The request source that has received this read permission reads the material from the read source in the cache memory 4. The material read from the read source is expanded in the RAM 7 after being processed according to its characteristics. The arbitration unit 5 releases the block occupancy right BLP of the read source in which the material related to the acquisition request is stored when the material related to the acquisition request is acquired by the request source.

  Further, the arbitrating unit 5 manages the load bus occupation right LBP relating to the load bus 8 and the read bus occupation right RBP relating to the read bus 9. The load bus occupation right LBP is used to exclusively control the load from the NAND memory 3 based on the acquisition request from the masters A to C as the request sources. The read bus occupation right RBP is used to exclusively control the read from the cache memory 4 by the masters A to C.

  The load bus occupation right LBP is given to a request source when a material related to an acquisition request from a request source is not cached in the cache memory 4. However, as a precondition for granting the load bus occupation right LBP, it is a condition that when the arbitration unit 5 receives the acquisition request, the load bus occupation right LBP is not given to another request source. Therefore, when the load bus occupancy right LBP is already granted, the next load bus occupancy right LBP waits until it is released.

  Then, when a new load bus occupation right LBP is granted while satisfying the above condition, the material related to the acquisition request is read from the NAND memory 3. Then, when the read material is stored in the load destination of the cache memory 4, the current load bus occupation right LBP is released. On the other hand, when a material related to an acquisition request from a certain request source is cached in the cache memory 4, the request source is skipped without giving the load bus occupation right LBP. The reason is that the material has already been cached, so there is no need to load it again from the NAND memory 3.

  The read bus occupancy right RBP is granted after the release of the load bus occupancy right LBP at the time of a cache miss, but is granted by skipping the process of the load bus occupancy right LBP at the time of a cache hit. When a material related to an acquisition request from a certain request source is stored in the cache memory 4 (including both at the end of loading due to a cache miss hit and at the time of a cache hit), a read bus occupation right RBP is given to this request source Is done. However, the precondition for granting the read bus occupation right RBP is that the read bus occupation right RBP is not given to another request source. Therefore, if the read bus occupation right RBP has already been granted, the next read bus occupation right RBP is kept waiting until it is released.

  When the new read bus occupancy right RBP is granted while satisfying the above condition, the request source that has received this grant reads the material related to the acquisition request from the read source of the cache memory 4. Then, when the material related to the acquisition request is acquired by the request source, the current read bus occupation right RBP is released.

  Next, specific transfer processing will be described with reference to the timing chart shown in FIG. The operation shown in the figure is in accordance with the description of the display list 10 shown in FIG. 2, but in order to avoid complication of explanation, the number of blocks of the cache memory 4 is set to 2 and each block occupancy right is set. Are BLP0 and BLP1. First, the display list analysis unit 2b prefetches the display list 10 and outputs transfer instructions A-1, B-1, C-1, A-2,... In order from the top line.

  At timing t1, the master A that has received the transfer instruction A-1 outputs an acquisition request A-1 to the arbitration unit 5. At this time, since the material A-1 does not exist in the cache memory 4, a cache miss hit (cache determination = No) occurs (hereinafter, the same applies to the materials B-1, C-1, and A-2). As a result, any vacant block occupation right BLP0 is given as master A. Then, the load bus occupation right LBP is granted to the master A on condition that the block occupation right BLP0 is granted. With the grant of the load bus occupation right LBP, loading of the material A-1 from the NAND memory 3 to the cache memory 4 is started.

  At timing t2, the master B that has received the transfer command B-1 outputs an acquisition request B-1 to the arbitration unit 5. As a result, the remaining free block occupation right BLP1 is given to the master B. However, since the load bus occupation right LBP is granted to the master A and is not vacant, the grant of this right to the master B is suspended.

  At timing t 3, the master C that has received the transfer instruction C- 1 outputs an acquisition request C- 1 to the arbitration unit 5. However, since the block occupation rights BLP0 and BLP1 are not free, the grant of this right to the master C is suspended.

  When the loading of the material A-1 is completed at the timing t4, the load bus occupation right LBP of the master A is released and the load bus occupation right LBP is granted to the next master B in the hold state (the master C is still on hold). Status). Thereby, loading of the material B-1 is started. Further, the read bus occupation right RBP is given to the master A when the loading of the material A-1 is completed. As a result, the material A-1 is read by the master A in parallel with the loading of the material B-1.

  When the reading of the material A-1 is completed at the timing t5, the acquisition request A-1 of the master A is withdrawn. Upon receiving this, the arbitration unit 5 releases the master A read bus occupation right RBP and also releases the master A block occupation right BLP0. Since the block occupation right BLP0 is vacant, the block occupation right BLP0 is given to the next master C in the pending state. However, since the load bus occupation right LBP is not free, the grant of this right to the master C is suspended.

  At timing t 6, the master A that has received the transfer instruction A- 2 outputs an acquisition request A- 2 to the arbitration unit 5. However, since the block occupation rights BLP0 and BLP1 are not free, the grant of this right to the master A is suspended.

  When the loading of the material B-1 is completed at the timing t7, the load bus occupancy right LBP of the master B is released, and the load bus occupancy right LBP is granted to the next master C in the hold state (the master A is still on hold). State). Thereby, loading of the material C-1 is started. Further, the read bus occupation right RBP is given to the master B when the loading of the material B-1 is completed. As a result, the material B-1 is read by the master B in parallel with the loading of the material C-1.

  When the reading of the material B-1 is completed at the timing t8, the acquisition request B-1 for the master B is withdrawn. Receiving this, the arbitration unit 5 releases the read bus occupation right RBP of the master B and also releases the block occupation right BLP1 of the master B. Since the block occupancy right BLP1 is vacant, the block occupancy right BLP1 is given to the next master A in the hold state. However, since the load bus occupation right LBP is not vacant, the grant of this right to the master A is suspended.

  When the loading of the material C-1 is completed at the timing t9, the load bus occupation right LBP of the master C is released, and the load bus occupation right LBP is granted to the next master A in the hold state. Thereby, loading of the material A-2 is started. Further, the read bus occupation right RBP is given to the master C when the loading of the material C-1 is completed. Thus, the material C-1 is read by the master C in parallel with the loading of the material A-2.

  When the reading of the material C-1 is completed at the timing t10, the acquisition request C-1 for the master C is withdrawn. Receiving this, the arbitrating unit 5 releases the read bus occupation right RBP of the master C and also releases the block occupation right BLP0 of the master C. When the loading of the material A-2 is completed at the timing t11, the load bus occupancy right LBP of the master A is released and the read bus occupancy right RBP is given to the master A. A lead is started. Then, when the reading of the material A-2 is completed at the timing t12, the acquisition request A-2 of the master A is withdrawn. Receiving this, the arbitrating unit 5 releases the read bus occupation right RBP of the master A and also releases the block occupation right BLP1 of the master A.

  Thereafter, at timing t13, the master A that has received the transfer instruction A-1 outputs an acquisition request A-1 to the arbitration unit 5. At this time, unlike the above-described t1 to t12, it is assumed that the material A-1 already exists in the cache memory 4. In this case, a cache hit (cache determination = affirmative) occurs. As a result, the block occupation right BLP0 of the block in which the material A-1 is stored is given as the master A. As described above, at the time of a cache hit, the grant of the load bus occupation right LBP is skipped, the read bus occupation right RBP is given to the master A, and the reading of the material A-1 by the master A is started. Then, when the reading of the material A-1 is completed at the timing t14, the acquisition request A-1 of the master A is withdrawn. Receiving this, the arbitrating unit 5 releases both the read bus occupation right RBP and the block occupation right BLP0 of the master A. The time required from when the master A outputs the acquisition request A-1 until it is withdrawn is equivalent to t1 to t5 when a cache miss hits, but is shortened to t12 to t13 when a cache hit occurs. Recognize.

  In the timing chart shown in FIG. 7, the read bus occupation right RBP is not granted to the next master unless the read bus occupation right RBP of one master is released. By alternately giving the bus occupation right RBP, the material may be read by each master in a time division manner.

  As described above, according to the present embodiment, the cache memory 4 is interposed between the NAND memory 3 and the image processor 2, and when the cache hits, the cache memory 4 is not loaded without loading the material from the NAND memory 3. The existing material is read. Since the display list 10 issued by the CPU 1 has no interruption in the transfer of the material due to its nature, the number of times of loading the material from the NAND memory 3 can be reduced by assuming this. Further, the material read from the cache memory 4 is stored in the RAM 7 or the display list analysis unit 2b via the transfer processing units 2c to 2d that issued the material acquisition request. Which of the transfer processing units 2c to 2d is the request source of the material is managed by the management table 11 of the arbitration unit 5. Therefore, even when a plurality of types of transfer processing units 2c to 2d coexist, the transfer processing units 2c to 2d that should process the material can be uniquely specified. As a result, while reducing the overall transfer time due to the cache effect, even if there is a difference in processing speed among a plurality of types of transfer processing, it is possible to easily perform these arbitrations.

  Further, according to the present embodiment, it is possible to request transfer of the next material to be transferred in addition to the material currently being transferred by prefetching the transfer command described in the display list 10 (prefetch mechanism). As a result, the overall transfer time can be further shortened. However, this prefetch mechanism is not indispensable, and the transfer instruction may be executed sequentially.

  Further, according to the present embodiment, a plurality of transfer processing units 2c to 2e share the load bus 8 by managing which transfer processing units 2c to 2e occupy the load bus 8 with the load bus occupation right LBP. Even if it is a form to do, these mediation can be performed efficiently. At the same time, by managing which transfer processing units 2c to 2e occupy the read bus 9 with the read bus occupation right RBP, a plurality of transfer processing units 2c to 2e may share the read bus 9. These mediations can be performed efficiently.

  In addition, according to the present embodiment, even when the NAND memory 3 which is cheaper than a normal ROM is used as a transfer source memory for storing a source material, due to the cache effect, there is a disadvantage inherent to this device. A certain load penalty can be effectively concealed. As a result, it is possible to accurately meet the market needs for using the NAND memory 3.

  Furthermore, according to the present embodiment, even if the materials handled by the system are diversified, the real-time performance of the drawing process is not impaired, so that it is possible to further promote multi-functionality and high added value of the image processing system.

(Second Embodiment)
FIG. 8 is an overall block diagram of an image processing system according to the second embodiment. The difference from the first embodiment described above is that the vertex data processing unit 2a is used instead of the subroutine acquisition unit 2c and that only the display list 10 is used without calling the subroutine 12 described above. Since other than that is the same as that of 1st Embodiment, the code | symbol same as FIG. 1 is attached | subjected and description here is abbreviate | omitted. The processing target of the vertex data processing unit 2a is the following material A ′.

(Material A ′) Vertex data defining a three-dimensional figure The vertex data is the vertex coordinates (X, Y, Z) of a polygonal polygon (for example, a triangular polygon) that is the basis for generating a three-dimensional image.

  When the apex data processing unit 2a is designated by the transfer command from the display list analysis unit 2b, the apex data processing unit 2a outputs a material A related to the transfer command, that is, the apex data acquisition request with the designation of “ROM address”. This acquisition request is transferred to the arbitration unit 5 via the bus interface 2f. When the vertex data processing unit 2a receives notification from the arbitration unit 5 that the vertex data related to the acquisition request is stored in the cache memory 4, the vertex data processing unit 2a acquires the vertex data by accessing the cache memory 4, and the vertex data Sort and coordinate conversion. The processed vertex data is stored in the RAM 7 via the memory interface 2g.

  As described above, according to the present embodiment, even when the vertex data itself is used as a material, the same effect as that of the first embodiment is obtained.

  In each of the above-described embodiments, the NAND memory 3 has been described as an example of the transfer source memory. The NAND memory 3 is a memory having a structure in which a plurality of storage elements (memory cells) are connected in series. As a typical example, the NAND memory 3 is a type that controls the amount of carriers (electrons) injected into a floating gate (a well-known NAND flash memory). Are of this type), and types using ferroelectrics are known. Further, instead of the NAND memory 3, an AND memory having a series connection structure similar to this may be used. Each of these series-connected memories has a drawback that the initial load penalty is large, but if the present invention is applied, this penalty can be effectively concealed. In addition, although application to a serial connection type memory is one of the optimal embodiments of the present invention, the present invention is not limited to this, and may be applied to various memories including ordinary CGROMs. Is also possible.

  In each of the above-described embodiments, one bus is allocated to each of the transfer processing units 2c to 2e and 2i. However, in order to secure the bus bandwidth, one transfer processing unit (for example, irreversible compression) is used. A plurality of buses may be allocated to the data decompression unit 2d). In this case, it is preferable to manage each bus by the management table 11 as a master.

  Further, in each of the above-described embodiments, as processing of the material in the transfer process, acquisition of the subroutine 12 regarding the display list 10 (main routine), decompression of the lossless compressed image data, decompression of the lossy compressed image data, or The vertex data processing that defines a three-dimensional figure has been described. However, the present invention is not limited to this, and can be widely applied to a mode in which two or more processes having different process contents depending on the characteristics of the material coexist. For example, (1) an arbitrary combination of the above processes, (2) a form in which another process is added to at least a part of the above process, and (3) a form in which a plurality of types of decompression processes corresponding to different lossless compression algorithms coexist. (4) A mode in which a plurality of types of decompression processing corresponding to different lossy compression algorithms coexist, and (5) a mode in which the above (1) to (4) are combined.

1 is a block diagram of an image processing system according to a first embodiment. Illustration of display list The figure which shows the display list acquisition path | route in 1st mode. The figure which shows the display list acquisition path | route in a 2nd mode. Flow chart of list analysis processing Illustration of management table Transfer processing timing chart Block diagram of an image processing system according to the second embodiment

Explanation of symbols

1 CPU
1a Main memory 2 Image processor 3 NAND memory 4 Cache memory 5 Arbitration unit 6 Display device 7 RAM
8 Load Bus 9 Read Bus 10 Display List 11 Management Table 12 Subroutine 2a Vertex Data Processing Unit 2b Display List Analysis Unit 2c Polygon Generation Unit (Master A)
2d lossless compression data decompression unit (master B)
2e Lossy compression data decompression unit (master C)
2f Bus interface 2g Memory interface 2h Drawing processor

Claims (14)

In an image processing system that performs image processing using a plurality of types of materials stored in a transfer source memory based on an instruction from a host device,
A cache memory connected to the transfer source memory via a load bus;
A display list analysis unit that is issued by the host device and analyzes a display list in which transfer instructions of materials necessary for drawing are described in time series, and sequentially outputs transfer instructions of each material;
A plurality of materials are provided corresponding to the types of materials, each of which is connected to the cache memory via a read bus, and when the self is specified by the transfer instruction from the display list analysis unit, When the acquisition request for the material specified by the transfer instruction is output, and the material related to the acquisition request is stored in the cache memory, the characteristics of the material with respect to the material acquired by accessing the cache memory A plurality of transfer processing units for performing processing according to
Managing the acquisition request from each of the transfer processing units, and the acquisition not stored in the cache memory depending on whether or not the material related to the acquisition request is stored in the cache memory An arbitration unit that reads out the requested material from the transfer source memory and stores it in the cache memory;
An image processing system comprising: a drawing processing unit that draws an image using the material processed by each of the transfer processing units. The storage area of the cache memory is divided into a plurality of cache blocks,
The arbitration unit manages block occupancy rights for each of the cache blocks in order to exclusively control access to the cache block by each of the transfer processing units. Image processing system.   When the material related to the acquisition request whose request source is one of the transfer processing units is not cached in the cache memory, the arbitration unit relates to any of the empty cache blocks to which the block occupancy right is not granted. And granting the block occupancy right to the request source, and when the material related to the acquisition request is cached in the cache memory, the request source is related to the cache block storing the material related to the acquisition request. The image processing system according to claim 2, wherein the block occupation right is given.   When the material related to the acquisition request is acquired by the request source, the arbitration unit releases the block occupancy right of the request source regarding the cache block in which the material related to the acquisition request is stored. The image processing system according to claim 3.   The arbitration unit manages a load bus occupancy right for the load bus in order to exclusively control reading of the material from the transfer source memory based on the acquisition request from each of the transfer processing units; The image processing system according to claim 1, wherein the image processing system is characterized in that:   The arbitration unit, when a material related to the acquisition request with one of the transfer processing units as a request source is not cached in the cache memory, the load bus occupation right other than the request source is not granted. The load bus occupancy right is granted to the request source on the condition that the load bus occupancy right is not granted to the request source when the material related to the acquisition request is cached in the cache memory. The image processing system according to claim 5.   The arbitration unit releases the load bus occupation right of the request source when the material related to the acquisition request from the request source is read from the transfer source memory and stored in the cache memory. The image processing system according to claim 6.   The arbitration unit manages a read bus occupancy right for the read bus in order to exclusively control reading of the material from the cache memory by each of the transfer processing units. An image processing system described in any of the above.   The arbitration unit reads the material related to the acquisition request from the transfer source memory when the material related to the acquisition request with any of the transfer processing units as a request source is not cached in the cache memory. If the read request is granted to the request source on the condition that it is stored in the cache memory, and the material related to the acquisition request is cached in the cache memory, the material related to the acquisition request The image processing system according to claim 8, wherein the read bus occupancy right is given to the request source without reading out from the transfer source memory.   The said arbitration part cancels | releases the said read bus occupation right of the said request source, when the material which concerns on the said acquisition request stored in the said cache memory is acquired by the said request source. The described image processing system.   11. The image processing system according to claim 1, wherein the transfer source memory is a memory having a structure in which a plurality of memory cells are connected in series.   Each of the transfer processing units acquires the display list subroutine, decompresses the losslessly compressed image data, decompresses the irreversibly compressed image data, or apex that defines a three-dimensional figure as processing for the material The image processing system according to claim 1, wherein data processing is performed.   The image processing system according to any one of claims 1 to 12, wherein the display list analysis unit pre-reads and analyzes the transfer command described in the display list.   The display list analysis unit manages the remaining capacity of the transfer source memory that varies by storing the material processed by each of the transfer processing units in the transfer destination memory, and the current remaining capacity of the transfer destination memory The image processing system according to claim 13, wherein an output timing of the transfer instruction is controlled according to the function.

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