JP2009293119A - Method of forming plating layer - Google Patents

Method of forming plating layer Download PDF

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JP2009293119A
JP2009293119A JP2008244535A JP2008244535A JP2009293119A JP 2009293119 A JP2009293119 A JP 2009293119A JP 2008244535 A JP2008244535 A JP 2008244535A JP 2008244535 A JP2008244535 A JP 2008244535A JP 2009293119 A JP2009293119 A JP 2009293119A
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layer
forming
plating
plating layer
substrate
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Yong Suk Kim
スク キム、ヨン
Young Soo Oh
ソー オー、ヨン
Byeung Gyu Chang
ギュ チャン、ビョン
Won Hee Yoo
ヘー ヨー、ウォン
Sung Yeol Park
ヨル パク、スン
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Samsung Electro Mechanics Co Ltd
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    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C25D5/022—Electroplating of selected surface areas using masking means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C25D5/12—Electroplating with more than one layer of the same or of different metals at least one layer being of nickel or chromium
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0076—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the composition of the mask
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0129—Thermoplastic polymer, e.g. auto-adhesive layer; Shaping of thermoplastic polymer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Other Surface Treatments For Metallic Materials (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of forming plating layer capable of minimizing chemical damage which may occur on a ceramic substrate when a metal pattern is plated on the ceramic substrate. <P>SOLUTION: The method of forming plating layer includes: a step of forming a seed layer 102 on the substrate 101; a step of forming a pattern layer 103 which is made of a thermoplastic resin and is provided with an open area on the seed layer 102; a step of forming a plating layer 104 on the seed layer 102 through the open area; and a step of applying heat to the pattern layer 103 to remove the pattern layer 103. Thereby, the method of forming plating layer is capable of minimizing chemical damage which may occur on the substrate, in particular, the ceramic substrate during plating process while securing a sufficient plating thickness. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明はメッキ層の形成方法に関するもので、より具体的に、十分なメッキ厚さを確保しながらメッキ過程で基板、特に、セラミック基板に生じ得る化学的な被害を最少化することが出来るメッキ層の形成方法に関する。   The present invention relates to a method for forming a plating layer, and more specifically, plating capable of minimizing chemical damage that can occur on a substrate, particularly a ceramic substrate, during a plating process while ensuring a sufficient plating thickness. The present invention relates to a method for forming a layer.

一般的に、多層セラミック基板は、半導体ＩＣチップのような能動素子とキャパシタ、インダクタ及び抵抗のような受動素子を複合化した部品として使われるか、または単純な半導体ＩＣパッケージとして使われている。より具体的に、上記多層セラミック基板はＰＡモジュール基板、ＲＦダイオードスイッチ、フィルター、チップアンテナ、各種パッケージ部品、複合デバイスなどの多様な電子部品を構成するため広く使われている。   In general, a multilayer ceramic substrate is used as a component in which an active element such as a semiconductor IC chip and passive elements such as a capacitor, an inductor and a resistor are combined, or is used as a simple semiconductor IC package. More specifically, the multilayer ceramic substrate is widely used to configure various electronic components such as PA module substrates, RF diode switches, filters, chip antennas, various package components, and composite devices.

このような多層セラミック基板の外部電極は、セラミック焼結体の表面に印刷された金属パターン上にＮｉ／Ａｕメッキ層をそれぞれ無電解／電解メッキ工程を通して形成することが一般である。しかし、このような方式により形成された外部電極の場合、上記Ｎｉ／Ａｕメッキ層の厚さが十分ではなく、基板の全体に均一な電流の供給が容易ではないため、メッキ層の厚さの均一度が高くない。これによって、上記外部電極にプローブチップなどを接合させる場合、接合力が落ち電気抵抗は高くなる。また、メッキ過程でメッキ液がセラミック基板の内部に浸透する場合、セラミック基板の脱色及び浸漬をもたらし、これは強度の低下につながる。   In general, the external electrode of the multilayer ceramic substrate is formed by forming an Ni / Au plating layer on a metal pattern printed on the surface of a ceramic sintered body through an electroless / electrolytic plating process. However, in the case of an external electrode formed by such a method, the thickness of the Ni / Au plating layer is not sufficient, and it is not easy to supply a uniform current to the entire substrate. Uniformity is not high. Accordingly, when a probe tip or the like is bonded to the external electrode, the bonding force is reduced and the electric resistance is increased. In addition, when the plating solution penetrates into the ceramic substrate during the plating process, the ceramic substrate is decolorized and immersed, which leads to a decrease in strength.

このような問題は多層セラミック基板の信頼性を低下させるため、当技術分野では、メッキ層が均一な厚さを有しながらも厚さを十分確保できる方案が求められる。   Since such a problem reduces the reliability of the multilayer ceramic substrate, there is a need in the art for a method that can ensure a sufficient thickness while the plating layer has a uniform thickness.

本発明は、上記のような問題点を解決するためのもので、本発明の一目的は、十分のメッキ厚さを確保しながらメッキ過程で基板、特に、セラミック基板に生じ得る化学的な被害を最少化することが出来るメッキ層の形成方法を提供することにある。   The present invention is intended to solve the above-described problems, and one object of the present invention is to provide chemical damage that can occur on a substrate, particularly a ceramic substrate, during a plating process while ensuring a sufficient plating thickness. It is an object of the present invention to provide a method for forming a plating layer that can minimize the thickness of the plating layer.

上記の目的を達成すべく、本発明の一実施形態は、基板上にシード層を形成する段階と、上記シード層上に熱可塑性樹脂からなりオープン領域を備えるパターン層を形成する段階と、上記オープン領域を通して上記シード層上にメッキ層を形成する段階と、上記パターン層を除去する段階とを含むメッキ層の形成方法を提供する。   To achieve the above object, an embodiment of the present invention includes a step of forming a seed layer on a substrate, a step of forming a pattern layer made of a thermoplastic resin and having an open region on the seed layer, and A method of forming a plating layer is provided that includes forming a plating layer on the seed layer through an open region and removing the pattern layer.

この場合、上記パターン層はポリエチレン（Ｐｏｌｙ Ｅｔｈｙｌｅｎｅ）、ポリビニリデン樹脂（Ｐｏｌｙ Ｖｉｎｙｌｉｄｅｎｅ Ｆｌｕｏｒｉｄｅ、ＰＶＤＦ）、ＬＣＰ（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｐｏｌｙｍｅｒ）及びその組み合せで構成されたグループから選択された一つの物質からなることが出来る。上記メッキ層の厚さが十分な水準になるよう上記パターン層の厚さは２０〜３０μｍであることが好ましい。   In this case, the pattern layer may be made of one material selected from the group consisting of polyethylene (Poly Ethylene), polyvinylidene resin (Poly Vinylidene Fluoride, PVDF), LCP (Liquid Crystal Polymer), and combinations thereof. . The thickness of the pattern layer is preferably 20 to 30 μm so that the plating layer has a sufficient thickness.

好ましくは、上記パターン層を除去する段階は、上記パターン層に熱を加えて行われることができる。この場合、具体的な工程条件として、上記パターン層を除去する段階は、上記パターン層を２００〜３００℃の温度で２〜３時間加熱して行われることができる。   Preferably, the step of removing the pattern layer may be performed by applying heat to the pattern layer. In this case, as a specific process condition, the step of removing the pattern layer may be performed by heating the pattern layer at a temperature of 200 to 300 ° C. for 2 to 3 hours.

上記シード層は、Ｔｉ、Ｃｒ、ＺｎＯ及びその組み合せで構成されたグループから選択された一つの物質からなる第１層、及び上記第１層上に形成されＣｕを含む第２層を備える構造であることが出来る。この場合、上記第１層の厚さは０．０５〜０．３μｍであることができ、上記第２層の厚さは０．３〜１μｍであることが出来る。   The seed layer includes a first layer made of one material selected from the group consisting of Ti, Cr, ZnO and a combination thereof, and a second layer formed on the first layer and containing Cu. There can be. In this case, the first layer may have a thickness of 0.05 to 0.3 μm, and the second layer may have a thickness of 0.3 to 1 μm.

好ましくは、上記シード層を形成する段階は、スパッタリングまたは電子ビーム蒸着工程により行われることができる。   Preferably, the step of forming the seed layer may be performed by a sputtering or electron beam deposition process.

本発明において上記メッキ層を形成する方法が特に制限される必要は無いが、上記メッキ層を形成する段階は電解メッキ方式で行われることが好ましい。   In the present invention, the method of forming the plating layer is not particularly limited, but the step of forming the plating layer is preferably performed by an electrolytic plating method.

この場合、上記基板上にシード層を形成する段階は、上記基板上面の全体領域にシード層を形成する段階であることが出来る。   In this case, the step of forming the seed layer on the substrate may be a step of forming the seed layer over the entire region of the upper surface of the substrate.

好ましくは、上記メッキ層を形成する段階は、Ｃｕ層、Ｎｉ層及びＡｕ層を順次に形成する段階であることが出来る。   Preferably, the step of forming the plating layer may be a step of sequentially forming a Cu layer, a Ni layer, and an Au layer.

また、上記基板はその内部に上記メッキ層と電気的に連結された内部電極及び導電性ビアを備えるセラミック基板であることが好ましい。   The substrate is preferably a ceramic substrate having internal electrodes and conductive vias electrically connected to the plating layer.

本発明によると、十分なメッキ厚さを確保しながらメッキ過程で基板、特に、セラミック基板に生じ得る化学的な被害を最少化することが出来るメッキ層を得ることが出来る。また、本発明によるメッキ層の形成方法により形成されたメッキ層は従来に比べてその厚さが均一であることができる。   According to the present invention, it is possible to obtain a plating layer capable of minimizing chemical damage that may occur on a substrate, particularly a ceramic substrate, during the plating process while ensuring a sufficient plating thickness. In addition, the plating layer formed by the plating layer forming method according to the present invention can have a uniform thickness compared to the conventional one.

以下、添付の図面を参照に本発明の好ましい実施形態を説明する。但し、本発明の実施形態は様々な形態に変形されることができ、本発明の範囲が以下で説明する実施形態により限定されるものではない。また、本発明の実施形態は当業界で平均的な知識を有している者に本発明をより完全に説明するため提供される。従って、図面における要素の形状及び大きさなどは、より明確な説明のため誇張されることがあり、図面上の同じ符号で表される要素は同じ要素である。   Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiment of the present invention can be modified in various forms, and the scope of the present invention is not limited by the embodiment described below. Also, embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for a clearer description, and elements denoted by the same reference numerals in the drawings are the same elements.

図１ａ乃至１ｄは、本発明の一実施形態によるメッキ層の形成方法を説明するための工程別の断面図である。   1a to 1d are cross-sectional views illustrating processes for explaining a method for forming a plating layer according to an embodiment of the present invention.

先ず、図１ａに図示された通り、基板１０１を備えて上記基板１０１の上面にシード層１０２を形成する。上記基板１０１は、その内部に形成された導電性ビア及び内部電極を備えることができ、特に、低温または高温同時焼成セラミックのようなセラミック基板が採用できるが、本発明はこれに制限されず、外部電極としてメッキ層が必要ないかなる基板も使用できる。上記シード層１０２は後述する工程により形成されるメッキ層のためのシードとして機能し、本実施形態の場合、スクリーン印刷法ではない焼結された基板１０１の上面全体にスパッタリングまたは電子ビーム蒸着工程を利用して形成することができる。このように、上記シード層１０２は上記基板１０１の上面全体に薄膜形態で形成され、これにより、後述する通り、メッキ層を電解メッキ方式で容易に形成することができる。   First, as shown in FIG. 1 a, a substrate 101 is provided and a seed layer 102 is formed on the upper surface of the substrate 101. The substrate 101 may include conductive vias and internal electrodes formed therein, and in particular, a ceramic substrate such as a low-temperature or high-temperature co-fired ceramic may be employed, but the present invention is not limited thereto, Any substrate that requires a plating layer as an external electrode can be used. The seed layer 102 functions as a seed for a plating layer formed by a process described later. In this embodiment, a sputtering or electron beam evaporation process is performed on the entire upper surface of the sintered substrate 101, which is not a screen printing method. It can be formed using. As described above, the seed layer 102 is formed in the form of a thin film on the entire upper surface of the substrate 101. Accordingly, as described later, the plating layer can be easily formed by an electrolytic plating method.

図２は、図１に図示されたシード層をより詳しく表した断面図である。図２を参照すると、上記シード層１０２は２層構造で、第１層はＴｉを含んでなるＴｉ層１０２ａで、第２層はＣｕを含んでなるＣｕ層１０２ｂである。この場合、上記Ｔｉ層１０２ａはセラミックなどからなる基板１０１とメッキ層との密着力を向上するためのもので、その厚さｔａは約０．０５〜０．３μｍに採用することができる。但し、実施形態によっては第１層としてＴｉの他にＣｒやＺｎＯを使用することができ、上記物質を相互混合して使用することも出来る。上記Ｃｕ層１０２ｂは実質的なシードとして機能し、このようなシードの機能を考えたとき、その厚さｔｂは約０．３〜１．０μｍに採用することができる。一方、図示してはいないが、上記シード層１０２と基板１０１の間にはＡｇなどからなる金属パッド層がされに含まれることも出来る。   FIG. 2 is a cross-sectional view illustrating the seed layer illustrated in FIG. 1 in more detail. Referring to FIG. 2, the seed layer 102 has a two-layer structure. The first layer is a Ti layer 102a containing Ti, and the second layer is a Cu layer 102b containing Cu. In this case, the Ti layer 102a is for improving the adhesion between the substrate 101 made of ceramic or the like and the plating layer, and the thickness ta can be adopted to be about 0.05 to 0.3 μm. However, depending on the embodiment, Cr or ZnO can be used as the first layer in addition to Ti, and the above substances can also be mixed and used. The Cu layer 102b functions as a substantial seed, and when considering the function of such a seed, the thickness tb can be set to about 0.3 to 1.0 μm. On the other hand, although not shown, a metal pad layer made of Ag or the like may be included between the seed layer 102 and the substrate 101.

次に、図１ｂに図示された通り、上記シード層１０２上にパターン層１０３を形成する。この場合、上記パターン層１０３のオープン領域Ｏはメッキ層を形成するための領域として提供される。特に、本実施形態で、上記パターン層１０３は熱により除去されるよう熱可塑性樹脂からなる。これによって、後述する通り、メッキ層を形成した後、上記パターン層１０３は容易に除去されることができ、除去過程で基板１０１、メッキ層などに与える損傷を最少化することができる。上記パターン層１０３として使用できる物質には、ポリエチレン（Ｐｏｌｙ Ｅｔｈｙｌｅｎｅ）、ポリビニリデン樹脂（Ｐｏｌｙ Ｖｉｎｙｌｉｄｅｎｅ Ｆｌｕｏｒｉｄｅ、ＰＶＤＦ）、ＬＣＰ（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｐｏｌｙｍｅｒ）などが例として挙げられる。   Next, a pattern layer 103 is formed on the seed layer 102 as shown in FIG. In this case, the open region O of the pattern layer 103 is provided as a region for forming a plating layer. In particular, in the present embodiment, the pattern layer 103 is made of a thermoplastic resin so as to be removed by heat. Accordingly, as described later, after the plating layer is formed, the pattern layer 103 can be easily removed, and damage to the substrate 101, the plating layer, and the like in the removal process can be minimized. Examples of the material that can be used for the pattern layer 103 include polyethylene (Poly Ethylene), polyvinylidene resin (Poly Vinylidene Fluoride, PVDF), and LCP (Liquid Crystal Polymer).

上記パターン層１０３の厚さｔ１は、所望とするメッキ層の厚さを考えて定めることができ、本実施形態では電解メッキにより、厚いメッキ層を得ることを目的とするため、これを考えたとき、上記厚さｔ１は２０〜３０μｍの範囲を有することが好ましい。一方、上記パターン層１０３は熱可塑性樹脂からなるパターンを形成するための多様な方法、例えば、マスク工程の後、スピンコーティングする方法などを利用して形成することができる。   The thickness t1 of the pattern layer 103 can be determined in consideration of the desired thickness of the plating layer. In this embodiment, the purpose is to obtain a thick plating layer by electrolytic plating. When the thickness t1 is preferably in the range of 20 to 30 μm. Meanwhile, the pattern layer 103 can be formed using various methods for forming a pattern made of a thermoplastic resin, for example, a spin coating method after a mask process.

次に、図１ｃに図示された通り、上記オープン領域Ｏを通して上記シード層１０２上にメッキ層１０４を形成する。具体的に図示してはいないが、本メッキ工程は、シード層１０２及びパターン層１０３が形成されている基板１０１をメッキ液が入っているメッキ槽に入れた後電気化学反応を起こす、電解メッキ方式により行われることができる。電解メッキ方式が可能なのは、上述の通り、上記基板１０１の全面に薄膜形態でシード層１０２が形成されているためと理解できる。このように、本実施形態では、パターン層１０３の間の空間を通して電解メッキ方式でメッキ層１０４を厚く形成することができ、上記基板１０１とメッキ層１０４の接触力も優れるようになる。この場合、上記メッキ層１０４はシード層１０２の構成物質によって変わるが、Ｃｕ／Ｎｉ／Ａｕの３層構造を有するよう形成することができる。   Next, as shown in FIG. 1 c, a plating layer 104 is formed on the seed layer 102 through the open region O. Although not specifically shown, this plating process is an electrolytic plating in which an electrochemical reaction occurs after the substrate 101 on which the seed layer 102 and the pattern layer 103 are formed is placed in a plating tank containing a plating solution. It can be done by a method. It can be understood that the electrolytic plating method is possible because the seed layer 102 is formed in a thin film form on the entire surface of the substrate 101 as described above. As described above, in this embodiment, the plating layer 104 can be formed thick by electrolytic plating through the space between the pattern layers 103, and the contact force between the substrate 101 and the plating layer 104 is also excellent. In this case, the plating layer 104 may be formed to have a three-layer structure of Cu / Ni / Au although it varies depending on the constituent material of the seed layer 102.

次に、図１ｄに図示された通り、基板１０１から上記パターン層１０３を除去する。上述の通り、上記パターン層１０３はポリエチレンなどの熱可塑性樹脂からなり、適切な加熱工程により容易に除去される。この場合、好ましい加熱工程条件として、加熱温度は３００〜４００℃で、加熱時間は２〜３時間程度であれば上記パターン層１０３を除去することができる。また、上記加熱工程は、上記メッキ層１０４の被害が最少化するよう上記メッキ層１０４をセラミック基板などで塞いだ状態で行われることができる。   Next, the pattern layer 103 is removed from the substrate 101 as illustrated in FIG. As described above, the pattern layer 103 is made of a thermoplastic resin such as polyethylene and is easily removed by an appropriate heating process. In this case, as a preferable heating process condition, the pattern layer 103 can be removed if the heating temperature is 300 to 400 ° C. and the heating time is about 2 to 3 hours. In addition, the heating process may be performed in a state where the plating layer 104 is covered with a ceramic substrate or the like so that damage to the plating layer 104 is minimized.

上述の通り、上記パターン層１０３は化学的方法ではなく熱により容易に除去されるため、上記メッキ層１０４、基板１０１などは化学的な被害を受けない。上記パターン層１０３を感光性物質で形成した場合であると、これを除去するためには、強酸または強塩基の使用が求められ、これにより上記メッキ層１０４、基板１０１などは化学的な損傷を受けることがあるが、本実施形態の場合には、このような被害を殆ど受けないのである。従って、メッキ層１０４と基板１０１の接着力が向上し、さらに他の電気的素子を上記メッキ層１０４と接合する場合の接着力も向上することができる。   As described above, since the pattern layer 103 is easily removed not by a chemical method but by heat, the plating layer 104, the substrate 101, etc. are not chemically damaged. If the pattern layer 103 is formed of a photosensitive material, it is necessary to use a strong acid or a strong base in order to remove the pattern layer 103. As a result, the plating layer 104, the substrate 101, etc. are chemically damaged. In the case of this embodiment, such damage is hardly received. Therefore, the adhesive force between the plated layer 104 and the substrate 101 can be improved, and the adhesive force when another electrical element is bonded to the plated layer 104 can also be improved.

一方、本発明の他の実施形態では、図３に図示された通り、シード層１０２を一部除去してメッキ層１０４の形状と同じようにすることにより、所望の電極構造を得ることが出来る。図３は、図１の実施形態で好ましく追加できる工程を表したものである。この場合、上記シード層１０２は適切なマスクを使用して当該技術分野で公知の工程により除去されることができる。   On the other hand, in another embodiment of the present invention, as shown in FIG. 3, a desired electrode structure can be obtained by removing a part of the seed layer 102 so as to have the same shape as the plating layer 104. . FIG. 3 shows steps that can be preferably added in the embodiment of FIG. In this case, the seed layer 102 can be removed by a process known in the art using an appropriate mask.

本発明者は本発明の優れた効果をみせるための実験を行い、以下では、従来技術と本発明により形成されたメッキ層を比較して説明する。   The inventor conducted an experiment to show the excellent effect of the present invention, and the following description will be made by comparing the prior art and the plating layer formed by the present invention.

先ず、熱可塑性パターンを使用せずＣｕ／Ｎｉ／Ａｕ３層構造のメッキ層を形成した従来技術と、本発明により形成されたＣｕ／Ｎｉ／Ａｕ３層構造のメッキ層を比較した。この場合、従来技術ではＮｉを無電解メッキで、Ａｕを電解メッキで形成し、本発明ではいずれも電解メッキを利用した。従来技術と本発明によって形成されたメッキ層の厚さを比較した結果、従来技術の場合、平均としてＣｕ層、Ｎｉ層、Ａｕ層がそれぞれ３．２μｍ、６．４μｍ、０．６９μｍで、本発明の場合、平均としてＣｕ層、Ｎｉ層、Ａｕ層がそれぞれ８．２μｍ、４．１μｍ、２．１μｍを得た。このように、本発明によるメッキ層は従来技術に比べて厚く形成されることができ、さらに、厚さの均一性も高かった。   First, a conventional technique in which a plated layer having a Cu / Ni / Au three-layer structure was formed without using a thermoplastic pattern was compared with a plated layer having a Cu / Ni / Au three-layer structure formed according to the present invention. In this case, in the prior art, Ni was formed by electroless plating and Au was formed by electrolytic plating, and in the present invention, both of them used electrolytic plating. As a result of comparing the thicknesses of the plating layers formed by the conventional technique and the present invention, in the case of the conventional technique, the average values of the Cu layer, the Ni layer, and the Au layer are 3.2 μm, 6.4 μm, and 0.69 μm, respectively. In the case of the invention, 8.2 μm, 4.1 μm, and 2.1 μm were obtained for Cu layer, Ni layer, and Au layer, respectively, on average. Thus, the plating layer according to the present invention can be formed thicker than the prior art, and the thickness uniformity is high.

次に、従来技術と本発明の固着強度を比較した結果、本発明によってメッキ層を形成し、これをプローブチップなどと接合させる場合、固着強度が大きく向上することが確認できた。即ち、従来技術の場合、メッキ層及びこれと接着したプローブチップを分離するまで必要なせん断応力が平均として約３６Ｎ／ｍｍ２であり、本発明はこれより２倍以上高い８２Ｎ／ｍｍ２であった。 Next, as a result of comparing the fixing strength of the prior art and that of the present invention, it was confirmed that the fixing strength was greatly improved when the plated layer was formed according to the present invention and joined to a probe tip or the like. That is, in the case of the prior art, is about 36N / mm 2 required shear stresses until the separation of the plated layer and it and the adhesive probe tip as an average, the present invention than this more than twice higher 82N / mm 2 met It was.

本発明は上述の実施形態及び添付の図面により限定されるものではなく、添付の請求範囲により限定しようとする。従って、請求範囲に記載された本発明の技術的思想を外れない範囲内で当技術分野の通常の知識を有している者により多様な形態の置換、変形及び変更が可能で、これもまた本発明の範囲に属する。   The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited by the appended claims. Accordingly, various forms of substitutions, modifications and changes can be made by persons having ordinary knowledge in the art without departing from the technical idea of the present invention described in the claims. It belongs to the scope of the present invention.

本発明の一実施形態によるメッキ層の形成方法を説明するための工程別の断面図である。It is sectional drawing according to the process for demonstrating the formation method of the plating layer by one Embodiment of this invention. 本発明の一実施形態によるメッキ層の形成方法を説明するための工程別の断面図である。It is sectional drawing according to the process for demonstrating the formation method of the plating layer by one Embodiment of this invention. 本発明の一実施形態によるメッキ層の形成方法を説明するための工程別の断面図である。It is sectional drawing according to the process for demonstrating the formation method of the plating layer by one Embodiment of this invention. 本発明の一実施形態によるメッキ層の形成方法を説明するための工程別の断面図である。It is sectional drawing according to the process for demonstrating the formation method of the plating layer by one Embodiment of this invention. 図１に図示されたシード層をより詳しく表したものである。2 is a more detailed representation of the seed layer illustrated in FIG. 図１の実施形態で好ましく追加できる工程を表したものである。The process which can be added preferably in embodiment of FIG. 1 is represented.

符号の説明Explanation of symbols

１０１ 基板
１０２ シード層
１０３ パターン層
１０４ メッキ層
１０２ａ Ｔｉ層
１０２ｂ Ｃｕ層 101 Substrate 102 Seed layer 103 Pattern layer 104 Plating layer 102a Ti layer 102b Cu layer

Claims (13)

基板上にシード層を形成する段階と、
前記シード層上に熱可塑性樹脂からなりオープン領域を備えるパターン層を形成する段階と、
前記オープン領域を通して前記シード層上にメッキ層を形成する段階と、
前記パターン層を除去する段階と、
を含むメッキ層の形成方法。 Forming a seed layer on the substrate;
Forming a pattern layer comprising an open region made of a thermoplastic resin on the seed layer;
Forming a plating layer on the seed layer through the open region;
Removing the pattern layer;
A method for forming a plating layer including: 前記パターン層は、ポリエチレン（Ｐｏｌｙ Ｅｔｈｙｌｅｎｅ）、ポリビニリデン樹脂（Ｐｏｌｙ Ｖｉｎｙｌｉｄｅｎｅ Ｆｌｕｏｒｉｄｅ、ＰＶＤＦ）、ＬＣＰ（Ｌｉｑｕｉｄ Ｃｒｙｓｔａｌ Ｐｏｌｙｍｅｒ）及びその組み合せで構成されたグループから選択された一つの物質からなることを特徴とする請求項１に記載のメッキ層の形成方法。   The pattern layer is made of one material selected from the group consisting of polyethylene (Poly Ethylene), polyvinylidene resin (Poly Vinylidene Fluoride, PVDF), LCP (Liquid Crystal Polymer), and a combination thereof. The method for forming a plating layer according to claim 1. 前記パターン層の厚さは、２０〜３０μｍであることを特徴とする請求項１に記載のメッキ層の形成方法。   The method for forming a plating layer according to claim 1, wherein the pattern layer has a thickness of 20 to 30 μm. 前記パターン層を除去する段階は、前記パターン層に熱を加えて行われることを特徴とする請求項１に記載のメッキ層の形成方法。   The method according to claim 1, wherein the removing the pattern layer is performed by applying heat to the pattern layer. 前記パターン層を除去する段階は、前記パターン層を２００〜３００℃の温度で２〜３時間加熱して行われることを特徴とする請求項４に記載のメッキ層の形成方法。   The method of forming a plating layer according to claim 4, wherein the step of removing the pattern layer is performed by heating the pattern layer at a temperature of 200 to 300 ° C. for 2 to 3 hours. 前記シード層は、Ｔｉ、Ｃｒ、ＺｎＯ及びその組み合せで構成されたグループから選択された一つの物質からなる第１層及び前記第１層上に形成されＣｕを含む第２層を備えることを特徴とする請求項１に記載のメッキ層の形成方法。   The seed layer includes a first layer made of one material selected from the group consisting of Ti, Cr, ZnO, and a combination thereof, and a second layer formed on the first layer and containing Cu. The method for forming a plating layer according to claim 1. 前記第１層の厚さは、０．０５〜０．３μｍであることを特徴とする請求項６に記載のメッキ層の形成方法。   The method of forming a plating layer according to claim 6, wherein the first layer has a thickness of 0.05 to 0.3 μm. 前記第２層の厚さは、０．３〜１μｍであることを特徴とする請求項６に記載のメッキ層の形成方法。   The method of forming a plating layer according to claim 6, wherein the second layer has a thickness of 0.3 to 1 μm. 前記シード層を形成する段階は、スパッタリングまたは電子ビーム蒸着工程により行われることを特徴とする請求項１に記載のメッキ層の形成方法。   The method of claim 1, wherein the step of forming the seed layer is performed by sputtering or electron beam evaporation. 前記メッキ層を形成する段階は、電解メッキ方式で行われることを特徴とする請求項１に記載のメッキ層の形成方法。   The method for forming a plating layer according to claim 1, wherein the step of forming the plating layer is performed by an electrolytic plating method. 前記基板上にシード層を形成する段階は、前記基板上面の全体領域にシード層を形成する段階であることを特徴とする請求項１０に記載のメッキ層の形成方法。   The method of forming a plating layer according to claim 10, wherein the step of forming the seed layer on the substrate is a step of forming the seed layer over the entire region of the upper surface of the substrate. 前記メッキ層を形成する段階は、Ｃｕ層、Ｎｉ層及びＡｕ層を順次に形成する段階であることを特徴とする請求項１に記載のメッキ層の形成方法。   The method of forming a plating layer according to claim 1, wherein the step of forming the plating layer is a step of sequentially forming a Cu layer, a Ni layer, and an Au layer. 前記基板は、その内部に前記メッキ層と電気的に連結された内部電極及び導電性ビアを備えるセラミック基板であることを特徴とする請求項１に記載のメッキ層の形成方法。   The method for forming a plating layer according to claim 1, wherein the substrate is a ceramic substrate including an internal electrode and a conductive via electrically connected to the plating layer.
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