JP2009289932A - Semiconductor device and its method for manufacturing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing which obtains a super junction structure having parallel pn layers with a division layer formed in the shape of a peeler at low cost and with good yield. <P>SOLUTION: The method of manufacturing a semiconductor device includes the steps of forming a first trench 12a on an n-type drain layer 1, epitaxially growing n-type drift layers 10a and 10b on the interior of the first trench 12a and on the drain layer 1, planarizing the drift layers 10a and 10b, forming a second trench 12b on the drain layer 1 and the drift layers 10a and 10b, and growing an n-type epitaxial layer on the interior of the second trench 12b and on the drain layer 1 and forming a drift layer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a semiconductor device having a super junction structure and a method for manufacturing the same.

In recent years, due to a demand for reducing power consumption of a power supply device, it is desired to reduce the loss of the power semiconductor device constituting the power supply device, that is, to reduce the on-resistance of the semiconductor device. The structure of a power semiconductor device is often called a vertical type having electrodes on both sides of a semiconductor layer, and in order to reduce the on-resistance of the vertical semiconductor device, the impurity concentration of the drift layer through which a drift current flows when turning on is set. It needs to be high. However, when the impurity concentration is increased, the spread of the depletion layer due to the reverse bias voltage at the time of OFF is reduced, and the breakdown voltage is lowered. Thus, the on-resistance and breakdown voltage of the power semiconductor device have a trade-off relationship.

In order to solve this trade-off relationship, a vertical semiconductor device having a semiconductor layer called a super junction structure is known.
FIG. 3 is a diagram showing a side cross-sectional structure of an n-channel MOSFET having a super junction structure.
an n-type drain layer 1;
A parallel pn layer 2 formed on the drain layer 1;
A p-type base layer 3 formed in an island shape on the parallel pn layer 2;
An n + type source layer 4 formed in an island shape on the base layer 3;
An insulating film 5 formed on the parallel pn layer 2 and the base layer 3 and the source layer 4;
A drain electrode 6 electrically connected to the drain layer 1;
A gate electrode 7 formed on the insulating film 5;
A source electrode 8 electrically connected to the source layer 4 in the opening of the insulating film 5;
The parallel pn layer 2 has a structure in which n − type drift layers 10 and p type partition layers 11 are alternately formed in the horizontal direction.

The operation of the MOSFET having a super junction structure will be described. When a voltage that increases the potential on the drain electrode 6 side (forward voltage) is applied between the drain electrode 6 and the source electrode 8 in the ON state in which a voltage equal to or higher than a predetermined threshold voltage is applied to the gate electrode 7. The region near the surface of the base layer 3 is inverted to form an inversion layer (channel), and electrons injected from the source layer 4 reach the drain layer 1 via the inversion layer and the drift layer 10. In an off state in which a voltage lower than a predetermined threshold voltage is applied to the gate electrode 7, a voltage (reverse voltage) that increases the potential on the source electrode 8 side is applied between the drain electrode 6 and the source electrode 8. In addition, the depletion layer expands laterally as the reverse voltage increases from the pn junction formed by the alternately formed n-type drift layers 10 and p-type partition layers 11, and the drift layer 2 is completely depleted. It becomes.
As described above, according to the super junction structure, even if the impurity concentration of the drift layer 10 is relatively high, the drift layer 10 is completely depleted when a reverse voltage is applied. The trade-off relationship with pressure resistance is improved.
Next, a method for manufacturing a super junction structure will be described.

FIG. 4 is a process sectional view showing a conventional embedding method described in Patent Document 1. In FIG.
First, as shown in FIG. 4A, an n − type drift layer 10a having an impurity concentration lower than that of the drain layer 1 is epitaxially grown on the n type drain layer 1, and the surface of the drift layer 10a is made of SiO 2 by thermal oxidation. A mask 9a is formed and patterned by photolithography, and a trench 12a is formed by wet etching or dry etching. At this time, the partition layer 11a is preferably formed to be equal to or deeper than the drift layer 10a.
Next, as shown in FIG. 4B, the sidewalls of the trench 12a are damaged and impurities are removed, and then the trench 12a is buried by epitaxial growth, and the p-type partition layer 11a having a higher impurity concentration than the drift layer 10a. Form.
Next, as shown in FIG. 4C, the partition layer 11a near the opening of the trench 12a is selectively removed by etching. This is to prevent growth from the opening and side walls of the trench 12a and the opening is blocked, and voids (voids) that cause deterioration of characteristics such as leakage current are not formed in the partition layer 11a. Yes, the partition layer 11a is formed while repeating the epitaxial growth step of FIG. 4B and the etching step of FIG. 4C a predetermined number of times.
Finally, as shown in FIG. 4D, the surface of the parallel pn layer 2a is planarized by chemical mechanical polishing (CMP) or the like to obtain a super junction structure.

Further, as means for further reducing the on-resistance of the semiconductor device having a super junction structure, a technique for increasing the impurity concentration of the drift layer 10 that is a current path and a technique for increasing the area of the drift layer 10 are known. The area of the drift layer 10 can be increased by forming the partition layer 11 narrowly, or by forming the parallel pn layer 2 in a column shape instead of a plate shape.

Patent 3485081

However, when the partition layer 11 is formed in a columnar shape by using the conventional embedding method, the number of repetitions of the epitaxial growth step and the etching step increases, so that the cost tends to increase. Further, the columnar trench 12 can be accurately etched. Since it was difficult to form well, there was a problem that the yield was reduced.

Therefore, the present invention is to provide a manufacturing method capable of obtaining a super junction structure having a parallel pn layer in which partition layers are formed in a columnar shape at a low cost and with a high yield.

In order to solve the above problems and achieve the above object, a method of manufacturing a semiconductor device according to claim 1 of the present invention includes:
It has a structure in which a drift layer of the first conductivity type and a partition layer of a second conductivity type different from the first conductivity type are alternately formed in the lateral direction, and a drift current flows in the longitudinal direction in the on state and is turned off. In a manufacturing method of a semiconductor device having a semiconductor region that is depleted in a state, the method for forming the semiconductor region includes:
Forming a trench on the semiconductor substrate;
Forming an epitaxial layer inside the trench and on the semiconductor substrate;
The step of planarizing the epitaxial layer is repeated a plurality of times.

Further, in order to solve the above problems and achieve the above object, a method for manufacturing a semiconductor device of the present invention according to claim 2 comprises:
Forming a second trench extending in a second direction intersecting the first direction on the semiconductor substrate;
A second semiconductor layer is embedded in the second trench by epitaxial growth, and a columnar drift layer or partition layer surrounded by the first semiconductor layer and the second semiconductor layer is formed on the semiconductor substrate. And a process.

Furthermore, in order to solve the above problems and achieve the above object, a method of manufacturing a semiconductor device according to a third aspect of the present invention includes:
Forming a first trench on the semiconductor substrate of the first conductivity type;
Forming a first conductivity type first epitaxial layer in the first trench and on the semiconductor substrate;
Planarizing the first epitaxial layer;
Forming a second trench on the first epitaxial layer and the semiconductor substrate;
Forming a second epitaxial layer of a first conductivity type within the second trench;
It is characterized by providing.

Furthermore, in order to solve the above problems and achieve the above object, a method of manufacturing a semiconductor device according to a fourth aspect of the present invention includes:
The method includes the steps of planarizing the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer, and implanting impurity ions of a second conductivity type.

Further, in order to solve the above problems and achieve the above object, a semiconductor device according to the present invention according to claim 5 is:
It has a structure in which a drift layer of the first conductivity type and a partition layer of a second conductivity type different from the first conductivity type are alternately formed in the lateral direction, and a drift current flows in the longitudinal direction in the on state and is turned off. In a semiconductor device having a semiconductor region that is depleted in a state, the semiconductor region is
Forming a trench on the semiconductor substrate;
Forming an epitaxial layer inside the trench and on the semiconductor substrate;
And the step of planarizing the epitaxial layer is repeated a plurality of times.

According to the invention of each claim, a semiconductor device having a super junction structure having a columnar partition layer can be obtained at a low cost and with a high yield.

Next, an example of a method for manufacturing a super junction structure according to an embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a process sectional view showing a method for manufacturing a super junction structure according to a first embodiment of the present invention.
First, as shown in FIG. 1A, an n − type drift layer 10a is epitaxially grown on an n type drain layer 1, and a mask 9a made of SiO 2 is formed on the surface of the drift layer 10a by thermal oxidation. An opening is provided by photolithography so that the mask 9a is formed in a stripe shape, and a trench 12a is formed by a first trench etching process by dry etching such as wet etching or reactive ion etching (RIE). At this time, the impurity concentration of the drift layer 10 a is 1.5 × 10 15 m −3, the thickness is 50 μm, the width of the mask 9 a is 5 μm, and the depth of the trench 12 a is 50 μm.

Next, as shown in FIG. 1B, a p-type partition layer 11a having an impurity concentration higher than that of the drift layer 10a is epitaxially grown by a method similar to the conventional embedding method. In the step of forming the partition layer 11a, the growth rarely proceeds from the vicinity of the opening of the strip-shaped trench 12a, so that it is not necessary to repeat the epitaxial growth and the etching step. Next, the surface of the partition layer 11a is planarized by a CMP method or the like to form the parallel pn layer 2a. The impurity concentration of the partition layer 11a is 3.5 × 10 15 m −3.

Next, as shown in FIG. 1C, a SiO2 film is provided on the surface of the parallel pn layer 2a by thermal oxidation, and an opening is formed by photolithography to form a mask 9b. As shown in the drawing, the opening formed in the mask 9b extends in a direction orthogonal to the partition layer 11a when seen in a plan view. The width of the mask 9b is 5 μm.

Next, as shown in FIG. 1D, a trench 12b is formed to a depth of 50 μm by a second trench etching process by wet etching or dry etching such as RIE.

Then, as shown in FIG. 1E, after forming the n − -type drift layer 10b by the same method as the conventional embedding method, the surface of the drift layer 10b is flattened by the CMP method or the like to form the parallel pn layer 2b. By doing so, a super junction structure having a prismatic partition layer 11b is obtained.

That is, the manufacturing method of the super junction structure according to the first embodiment of the present invention repeats the first trench etching process for forming the strip-shaped trench 12a and the second trench etching process for forming the strip-shaped trench 12b, In addition, the trench 12a and the trench 12b are different from the conventional manufacturing method in that the trench 12a and the trench 12b are formed so as to be orthogonal to each other in plan view.

According to the manufacturing method of the super junction structure according to the first embodiment of the present invention, the partition layer 11 is formed in a columnar shape, and has the super junction structure in which the area of the drift layer 10 is enlarged, and the on-resistance is reduced and the breakdown voltage is increased. Thus, a semiconductor device with an improved trade-off relationship can be obtained at a low cost and with a high yield.

FIG. 2 is a process cross-sectional view illustrating a method for manufacturing a super junction structure according to a second embodiment of the present invention.
First, as shown in FIG. 2A, the impurity concentration is made equal to that of the p-type partition layer 11a on the drain layer 1 by the same method as in FIGS. 1A and 1B of the first embodiment. An n-type drift layer 10a ′ is epitaxially grown to form a p-type partition layer 11a, and a parallel pn layer 2a ′ is formed. The impurity concentration of the drift layer 10a ′ and the partition layer 11a is 1.5 × 10 15 m −3.

Next, as shown in FIG. 2B, a parallel pn layer 2b ′ composed of the drift layer 10b ′ and the partition layer 11b is formed by the same method as in FIGS. 1C to 1E of the first embodiment.

Then, as shown in FIG. 2C, after implanting p-type impurity ions such as boron (B) from the surface of the parallel pn layer 2b ′, the impurity ions are activated, whereby the n − -type drift layer 10c. And a super junction structure having a parallel pn layer 2c composed of a p + type partition layer 11c. At this time, by implanting the ion acceleration voltage stepwise or continuously, the impurity ion implantation amount in the depth direction of the parallel pn layer 2c can be made uniform. At this time, B ions are implanted so that the total impurity amount of the drift layer 10c is equal to the total impurity amount of the partition layer 11c.

According to the method of manufacturing a super junction structure according to the second embodiment of the present invention, the impurity concentration of the drift layer 10a ′ and the partition layer 11a is equal, so the width and depth of the trench formed in the second trench etching step. In addition to the same effects as the manufacturing method of the first embodiment, the manufacturing yield can be further improved.

The transistor of the present invention is not limited to the above embodiment, and various modifications are possible. For example, since the conductivity type of each semiconductor layer may be reversed, it can also be applied to the manufacture of a p-channel MOSFET. Alternatively, the drift layer 10 may be formed by applying a filling method to the partition layer 11 epitaxially grown on the drain layer 1.
The trench 12b may be formed so as to intersect the partition layer 11a at an arbitrary angle.
Further, the embedding property is further improved by forming the trench so that the trench width gradually becomes narrower from the front surface side of the parallel pn layer 2 toward the rear surface of the trench.
In addition, the ion implantation may be performed between the second trench etching step and the drift layer 10 filling step. In this case, the ion implantation can be performed on the side surface of the trench at an angle rather than the vertical direction. The impurity concentration in the vertical direction can be easily made uniform.
The impurity concentration can be changed as appropriate so that the total impurity amount of the drift layer 10 and the partition layer 11 can be obtained.

It is process sectional drawing which shows the manufacturing method of the semiconductor device of 1st Example of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device of 2nd Example of this invention. It is sectional drawing which shows the structure of MOSFET which has the conventional super junction structure. It is process sectional drawing which shows the manufacturing method by the embedding method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Drain layer 2, 2a-2c Parallel pn layer 3 Base layer 4 Source layer 5 Insulating film 6 Drain electrode 7 Gate electrode 8 Source electrode 9, 9a, 9b Mask 10, 10a-10c Drift layer 11, 11a-11c Partition layer 12 , 12a, 12b trench

Claims (5)

It has a structure in which a drift layer of the first conductivity type and a partition layer of a second conductivity type different from the first conductivity type are alternately formed in the lateral direction, and a drift current flows in the longitudinal direction in the on state and is turned off. In a manufacturing method of a semiconductor device having a semiconductor region that is depleted in a state, the method for forming the semiconductor region includes:
Forming a trench on the semiconductor substrate;
Forming an epitaxial layer inside the trench and on the semiconductor substrate;
And a step of flattening the epitaxial layer, a method of manufacturing a semiconductor device, wherein the method is repeated a plurality of times.
Forming a second trench extending in a second direction intersecting the first direction on the semiconductor substrate;
A second semiconductor layer is embedded in the second trench by epitaxial growth, and a columnar drift layer or partition layer surrounded by the first semiconductor layer and the second semiconductor layer is formed on the semiconductor substrate. The method of manufacturing a semiconductor layer value according to claim 1, further comprising: a step.
Forming a first trench on the semiconductor substrate of the first conductivity type;
Forming a first conductivity type first epitaxial layer in the first trench and on the semiconductor substrate;
Planarizing the first epitaxial layer;
Forming a second trench on the first epitaxial layer and the semiconductor substrate;
Forming a second epitaxial layer of a first conductivity type within the second trench;
The method of manufacturing a semiconductor device according to claim 1, comprising:
4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of implanting second conductivity type impurity ions into the semiconductor substrate, the first epitaxial layer, and the second epitaxial layer.
It has a structure in which a drift layer of the first conductivity type and a partition layer of a second conductivity type different from the first conductivity type are alternately formed in the lateral direction, and a drift current flows in the longitudinal direction in the on state and is turned off. In a semiconductor device having a semiconductor region that is depleted in a state, the semiconductor region is
Forming a trench on the semiconductor substrate;
Forming an epitaxial layer inside the trench and on the semiconductor substrate;
The semiconductor device is formed by repeating the step of planarizing the epitaxial layer a plurality of times.

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