JP2009289108A - Testing device and method of controlling the same, and test system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a test system for executing a program while achieving synchronization between a plurality of CPU. <P>SOLUTION: A test program includes a plurality of processing units. Synchronization processing setting data S10 showing the processing units whose synchronization processing should be performed between a plurality of site CPUs 10 are written in a shared memory 22. A plurality of site CPUs 10 perform access to the shared memory 22 to obtain the synchronization processing setting data S10. A plurality of site CPUs 10 respectively start the execution of the test program by using a start instruction S12 from a work station 110 as an opportunity. When completing the processing units whose synchronization processing should be performed, each site CPU 10 notifies a main processor 20 of the completion of processing, and temporarily stops the execution of the program. When receiving the notification of the completion of processing from all the site CPUs 10, the main processor 20 issues a resumption instruction S16 of the program. The plurality of site CPUs 10 start the next processing units of the program by using the resumption instruction S16 from the main processor 20 as an opportunity. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device test apparatus.

  In order to efficiently test a plurality of devices under test (DUT), a test apparatus equipped with a plurality of CPUs (Central Processing Units) is used. FIG. 1 is a block diagram showing the configuration of an automatic test equipment (hereinafter referred to as ATE) 300 equipped with a plurality of CPUs (hereinafter referred to as site CPUs). The test system 400 includes an ATE 300 and a workstation 310. The ATE 300 includes a plurality of site CPUs 302_1 to 302_n. For example, the plurality of site CPUs 302_1 to 302_n are provided for each of a plurality of test units (not shown), and control corresponding test units or analyze the test results obtained from the test units.

  A plurality of site CPUs 302_1 to 302_n (hereinafter simply referred to as site CPUs 302 as necessary) can individually and independently execute programs. The workstation 310 is a general-purpose computer having a general configuration, and comprehensively controls the ATE 300 and provides an interface between the user and the ATE 300.

In the test system 400 having such a configuration, the program is executed according to the following flow.
1. The workstation 310 issues a program start command S1 to the plurality of site CPUs 302.
2. When the program activation instruction S1 is issued, each site CPU 302 executes the activated program.
3. Each site CPU 302 transmits an end notification S2 to the workstation 310 when the program ends.

  In the test system 400 of FIG. 1, when synchronizing a plurality of site CPUs 302, the following problems occur.

  For example, the ATE 300 performs a self-diagnosis immediately after its activation. At this time, the plurality of site CPUs 302 independently execute a diagnostic program in parallel. Even when all the site CPUs 302 execute the same program, if the processing speed (processing capability) differs for each site CPU 302 or the number of loop processes in the diagnostic program differs for each test unit, each site CPU 302 However, the progress of the diagnostic program and the timing to end the process are different.

  In this test system 400, when it is desired to execute a program while synchronizing a plurality of site CPUs 302, the program is divided and described for each processing unit to be synchronized, and all the site CPUs 302 have one processing unit. When the process is completed, it is necessary to return the process to the workstation 310 and then start the next program. Alternatively, a software process is required in which an end flag for each site CPU 302 to be synchronized is incorporated in the program and waits until all the flags are asserted. Such a situation increases the burden on the user of the test system 400 when programming the program.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a test system capable of executing a program while synchronizing a plurality of CPUs.

One embodiment of the present invention relates to a test apparatus that operates in cooperation with a workstation connected to the outside. This test apparatus includes a plurality of processors each capable of independently executing a predetermined program, a main processor, and a shared memory accessible from the plurality of processors and the main processor. The test apparatus performs the following steps.
1. 1. A step of receiving data indicating a processing unit to be synchronized among a plurality of processing units included in a predetermined program from a workstation and writing the data in a shared memory. 2. A plurality of processors access a shared memory and acquire data indicating a processing unit to be synchronized. 3. Start of execution of a predetermined program by each of a plurality of processors triggered by an activation command from the workstation. 4. When a plurality of processors complete a processing unit to be synchronously processed, the main processor is notified of the completion of processing and the program execution is temporarily stopped. 5. When the main processor receives notification of processing completion from all the processors, it issues a program restart instruction to the plurality of processors. Steps in which a plurality of processors start executing the next processing unit of a program triggered by a restart instruction from the main processor. The execution order of each step is arbitrarily set within a range that does not hinder processing.

  A “processing unit” can be understood as a function, main routine, subroutine, procedure, thread, program module, or a plurality of these. According to this aspect, by defining in advance a processing unit (also referred to as a synchronization processing unit) to be synchronized in the program by a user of the test apparatus (also referred to as a user), all processors complete the synchronization processing unit. Until then, the execution of the program can be temporarily stopped, and the synchronization process can be realized.

  The workstation may designate a plurality of processing units (synchronous processing units) to be synchronized between a plurality of processors. The plurality of processors may notify the main processor of the completion of processing every time one processing unit to be synchronized is completed.

  The predetermined program may be a self-diagnosis program executed when the test apparatus is activated.

  Another aspect of the present invention is a test system. This test system includes the test apparatus according to any one of the above-described aspects and a workstation that issues a start command to the test apparatus.

Still another embodiment of the present invention relates to a method for controlling a test apparatus that operates in cooperation with a workstation connected to the outside. The test apparatus includes a plurality of processors each capable of independently executing a predetermined program, a main processor, and a plurality of processors and a shared memory accessible from the main processor. The control method executes the following steps.
1. 1. A step of receiving data indicating a processing unit to be synchronized among a plurality of processing units included in a predetermined program from a workstation and writing the data in a shared memory. 2. A plurality of processors access a shared memory and acquire data indicating a processing unit to be synchronized. 3. Start of execution of a predetermined program by each of a plurality of processors triggered by an activation command from the workstation. 4. When each of the plurality of processors completes the processing unit to be synchronized, the main processor is notified of the completion of processing and the program execution is temporarily stopped. 5. When the main processor receives notification of processing completion from all the processors, it issues a program restart instruction to the plurality of processors. A step in which a plurality of processors start executing the next processing unit of a program in response to a restart instruction from the main processor

  It should be noted that any combination of the above-described constituent elements, and those in which constituent elements and expressions of the present invention are mutually replaced between methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, synchronization between a plurality of processors can be easily realized.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

FIG. 2 is a block diagram showing a configuration of the test system 200 according to the embodiment. The test system 200 includes an ATE 100 and a workstation 110.
The ATE 100 operates in cooperation with a workstation 110 connected to the outside. A plurality of ATEs 100 may be connected to a single workstation 110. The workstation 110 controls a test sequence of a DUT (not shown) by the ATE 100 based on the test program and analyzes the test result by the ATE 100. The workstation 110 is a general-purpose computer including a CPU, a memory, a hard disk, and the like.

  The ATE 100 includes a plurality of site CPUs 10_1 to 10_n, a main CPU 20, and a shared memory 22. In addition, the ATE 100 includes a test unit, a timing generator, a pattern generator, and the like (not shown).

  Each of the plurality of site CPUs 10 is configured to be able to execute a predetermined test program independently. The plurality of site CPUs 10 may be individual packages or may be integrated into a single package like a multi-core processor.

  In one embodiment, the plurality of site CPUs 10_1 to 10_n are provided for each of a plurality of test units (not shown), for example, and control corresponding test units or analyze the test results obtained from the test units.

  In another aspect, when the ATE 100 tests a plurality of DUTs in parallel, the plurality of site CPUs 10_1 to 10_n may be provided for each DUT. Each site CPU 10 may test the corresponding DUT based on the test program.

In yet another aspect, when the DUT is a multi-bank memory, each site CPU 10 may be provided for each bank. Each site CPU 10 may test the corresponding bank based on the test program.
The arrangement and functions of the plurality of site CPUs 10 are not limited to these modes.

  The main CPU 20 is a processor for controlling the ATE 100 in an integrated manner. The shared memory 22 is configured to be accessible not only from the main CPU 20 but also from a plurality of site CPUs 10_1 to 10_n. The shared memory 22 may be configured as a separate chip from the main CPU 20 or may be configured integrally with the main CPU 20.

  A test program to be executed by the plurality of site CPUs 10_1 to 10_n is stored in a storage device on the workstation 110 side, for example, a hard disk (not shown). The test program may be stored in a storage device (not shown) on the ATE 100 side. The test program is programmed as a collection of a plurality of processing units. The processing unit can be grasped as a function, a main routine, a subroutine, a procedure, a thread, a program module, or a plurality of these.

  The above is the overall configuration of the ATE 100. The ATE 100 and the workstation 110 execute the following processing.

  There is a case where it is desired to synchronize the processes of the plurality of site CPUs 10_1 to 10_n. For example, when the ATE 100 is started, prior to the start of the DUT test, when the site CPUs 10_1 to 10_n execute the self-diagnosis program, there is a situation where the processes of the site CPUs 10_1 to 10_n are desired to be synchronized. Alternatively, when a plurality of DUTs are tested in parallel, an analysis result of another DUT may be required for an analysis process of a certain DUT. In this case also, a synchronization process is required.

  In these cases, the user of the test system 200 defines in advance processing units (hereinafter referred to as synchronous processing units) to be subjected to synchronous processing, and specifies data (hereinafter referred to as synchronous processing setting data) specifying the synchronous processing units (function information). S10) is registered in the workstation 110 in advance.

  Prior to the start of test program execution by the plurality of site CPUs 10_1 to 10_n, the workstation 110 writes the synchronization processing setting data S10 indicating the defined synchronization processing unit to the shared memory 22 of the ATE 100, and registers the synchronization processing unit on the ATE 100 side. To do. One or more synchronization processing units may be registered.

  The plurality of site CPUs 10_1 to 10_n access the shared memory 22, refer to the synchronization processing setting data S10, and identify processing units to be synchronized.

  The site CPUs 10_1 to 10_n start execution of the test program in response to the activation instruction S12 from the workstation 110.

  Each of the site CPUs 10_1 to 10_n executes the processing unit included in the test program, and notifies the main processor 20 of the completion of processing when the processing of the synchronous processing unit is completed. Completion of the synchronous processing unit can be associated with a return statement in the program, for example. Specifically, each site CPU 10 notifies the processing completion (referred to as completion notification data) immediately before (or immediately after) the return statement of the synchronous processing unit (function) specified by the synchronous processing setting data S10. S14 is output to the main CPU 20. Each site CPU 10 temporarily stops execution of the program in that state. The completion notification data S14 may be realized by writing data to a register provided for each site CPU 10.

  When the main CPU 20 receives notification of processing completion from all the site CPUs 10, the main CPU 20 issues a test program restart instruction S16 simultaneously to a plurality of processors.

  The plurality of site CPUs 10 are released from the paused state in response to the restart instruction S16 from the main processor 20 and start executing the next processing unit of the test program.

  When a plurality of synchronization processing units are specified by the synchronization processing setting data S10, each of the plurality of processors notifies the main processor 20 of the completion of processing each time one synchronization processing unit is completed, and temporarily stops the processing.

The above is the configuration of the ATE 100. Hereinafter, the operation of the ATE 100 will be described. FIG. 3 is a time chart showing the operation of the ATE 100 in FIG.
In order to facilitate understanding, it is assumed that the test program includes a plurality of functions func1 to func5 corresponding to processing units and has four site CPUs. The functions func1 to func4 are executed in order by each site CPU10. The second function func2 and the fourth function func4 are designated in advance by the user as functions (synchronization processing units) to be synchronized. In this situation, the ATE 100 performs the following processing.

  The workstation 110 writes the synchronization processing setting data S10 designating the functions func2 and fucn4 to be synchronized to the shared memory 22, and registers the functions func2 and func4.

  The plurality of site CPUs 10_1 to 10_n access the shared memory 22 and refer to the synchronization processing setting data S10. As a result, each site CPU 10 is notified that the functions func2 and func4 among the functions func1 to func5 should be synchronized.

  When the activation instruction S12 is output from the workstation 110, the plurality of site CPUs 10 start executing the test program (time t0). Specifically, each of the sites CPU1 to CPU4 starts processing of the function func1. Even when the same function is executed, the time required to complete the function differs because the number of loop processes and branch processes differ for each site CPU 10.

  The function func1 is not registered as a function to be synchronized. When each site CPU 10 completes the function func1, the processing of the function fucn2 is started.

  Since the function func2 is registered as a function to be synchronously processed by the synchronous processing setting data S10, each of the site CPUs 10_1 to 10_4 outputs completion notification data S14_1 to S14_4 when the processing of the function func2 is completed. Stop.

  When the completion notification data S14 is output from all the site CPUs 10_1 to 10_4 at time t1, the main CPU 20 issues a restart instruction S16. When receiving the restart instruction S16, the site CPUs 10_1 to 10_4 start processing of the function func3 which is a subsequent processing unit.

  Since the function func3 is not registered as a function to be synchronized, each site CPU 10 starts the process of the function fucn4 when the function func3 is completed. Since the function func4 is registered as a function to be synchronized by the synchronization process setting data S10, each of the site CPUs 10_1 to 10_4 outputs completion notification data S14_1 to S14_4 when the process of the function func4 is completed. Stop.

  When the completion notification data S14 is output from all the site CPUs 10_1 to 10_4 at time t2, the main CPU 20 issues a restart instruction S16. When receiving the restart instruction S16, the site CPUs 10_1 to 10_4 start processing of the function func5 which is a subsequent processing unit.

  When all the site CPUs 10_1 to 10_4 complete the processing of the function fucn5, the processing of the test program is completed.

  The above is the operation of the ATE 100. According to the ATE 100 according to the embodiment, arbitrary processing units can be flexibly synchronized. In addition, since the synchronization process is automatically performed by the main CPU 20 and the shared memory 22 of the ATE 100, the user only has to specify the processing unit to be synchronized, and the burden of programming the test program can be reduced.

  Although the present invention has been described based on the embodiments, the embodiments only show the principle and application of the present invention, and the embodiments depart from the idea of the present invention defined in the claims. Many modifications and arrangements can be made without departing from the scope.

It is a block diagram which shows the structure of ATE which mounts several CPU. It is a block diagram which shows the structure of the test system which concerns on embodiment. 3 is a time chart showing the operation of the ATE in FIG. 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... ATE, 110 ... Workstation, 200 ... Test system, 10 ... Site CPU, 20 ... Main CPU, 22 ... Shared memory, S10 ... Synchronization processing setting data, S12 ... Start-up command, S14 ... Completion notification data, S16 ... Resume order.

Claims (7)

A test apparatus that cooperates with an externally connected workstation,
A plurality of processors each capable of independently executing a predetermined program;
A main processor;
A shared memory accessible from the plurality of processors and the main processor;
With
Receiving data indicating a processing unit to be synchronously processed among the plurality of processors among the plurality of processing units included in the predetermined program from the workstation, and writing the data into the shared memory;
The plurality of processors accessing the shared memory to obtain data indicating a processing unit to be synchronized;
Each of the plurality of processors starting execution of the predetermined program triggered by an activation command from the workstation;
When each of the plurality of processors completes the processing unit to be synchronized, notifying the main processor of the completion of processing and temporarily stopping execution of the program;
When the main processor receives notification of processing completion from all the processors, issuing a restart instruction for the program to the plurality of processors;
Triggered by a restart instruction from the main processor, the plurality of processors start executing the next processing unit of the program;
A test apparatus characterized in that The workstation specifies a plurality of processing units to be synchronized between the plurality of processors,
2. The test apparatus according to claim 1, wherein the plurality of processors notify the main processor of the completion of processing every time one processing unit to be synchronized is completed.   The test apparatus according to claim 1, wherein the predetermined program is a self-diagnosis program that is executed when the test apparatus is activated. A test apparatus according to any one of claims 1 to 3,
A workstation that issues an activation instruction to the test apparatus;
A test system comprising: A control method of a test apparatus that operates in cooperation with an externally connected workstation,
The test apparatus comprises:
A plurality of processors each capable of independently executing a predetermined program;
A main processor;
A shared memory accessible from the plurality of processors and the main processor;
The control method includes:
Receiving data indicating a processing unit to be synchronously processed among the plurality of processors among the plurality of processing units included in the predetermined program from the workstation, and writing the data into the shared memory;
The plurality of processors accessing the shared memory to obtain data indicating a processing unit to be synchronized;
Each of the plurality of processors starting execution of the predetermined program triggered by an activation command from the workstation;
When each of the plurality of processors completes the processing unit to be synchronized, notifying the main processor of the completion of processing and temporarily stopping execution of the program;
When the main processor receives notification of processing completion from all the processors, issuing a restart instruction for the program to the plurality of processors;
Triggered by a restart instruction from the main processor, the plurality of processors start executing the next processing unit of the program;
The control method characterized by including. The workstation specifies a plurality of processing units to be synchronized between the plurality of processors,
6. The control method according to claim 5, wherein the plurality of processors notify the main processor of completion of processing every time one processing unit to be synchronized is completed.   The control method according to claim 5, wherein the predetermined program is a self-diagnosis program executed when the test apparatus is started up.

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