CN112579306B - Thread setting and thread scheduling method - Google Patents
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
The invention relates to a method for setting and dispatching threads, which comprises the following steps: s1, planning a thread pool in a workstation, wherein the number of threads is site number plus 1; s2, executing thread scheduling and starting a main thread; s3, setup and Meas phases of the first test item of the main line Cheng Zhihang; s4, the main line Cheng Zhihang is provided with a Setup stage and a Meas stage of a second test item, and a site1 sub-thread is started to execute an Uload stage of the first test item; s5site1 sub-thread executes the Calc and Judge phases of the first test item, and simultaneously starts site2 sub-thread to execute the Uload phase of the first test item; s6, after the Uload of one site is executed in the S5 mode, the Calc and Judge processes of the site are executed, and the next site sub-thread is started to execute the Uload until all site sub-threads are started and completed Upload, calc, judge; s7, circulating S4-S6, sequentially executing Setup and Meas flows from a first test item to a second test item by the main thread to the last test item, and sequentially executing Upload, calc, judge flows of the previous test item by each site sub-thread; s8, synchronizing threads; s9, completing the test and destroying the thread pool.
Description
Technical Field
The invention relates to the field of integrated circuit testing, in particular to a method for setting and scheduling threads.
Background
With the development of society, people have put an increasing demand for the diversity and richness of functions of electronic products. With the progress of integrated circuit design and manufacturing technology, this requirement is becoming possible, but the chip scale is becoming larger, and not only the CPU, memory, and the universal peripheral interface USB, MIPI, SPI, but also various complex functional modules such as GPU, VPU, audio processor, AES, SHA, etc. are integrated in one chip.
The complexity and the scale expansion of the chip function provide serious challenges for the chip test, so that the development time of a test program is increased, the test time of the chip is greatly increased, and the test cost is increased.
At present, the test of the chip is basically finished by using a general ATE tester. Common ATE testers are V93000, T2000, J750, etc. The universal ATE tester mainly comprises a workstation and a test head, wherein the test head comprises a plurality of test boards, a test vector generator, a clock generator, a driver and a comparator are arranged in the test boards, and the test boards comprise a plurality of test channels, so that the connection with each Site device to be tested can be realized, and excitation or capture response can be applied to the device to be tested.
The workstation is responsible for controlling the test board card, establishes a test vector and a corresponding control instruction through API programming, sends the test vector and the corresponding control instruction to the target test board card through the downlink bus, and the test board card executes the test and acquires the chip response data, and uploads the chip response data to the workstation through the uplink bus, and then the workstation processes and judges the data to obtain the test result of the chip. FIG. 1 is a diagram of an ATE test connection.
The test of the chip often includes a plurality of test items, each test item is divided into five stages of test vector establishment (Setup), test data acquisition (Meas), test data uploading (load), test data processing (Calc) and result judgment (Judge), and the ATE tester can only complete the whole flow of one test item and then test the next test item, which is equivalent to serial execution of the test items one by one.
The conventional method for improving the chip test efficiency is that multiple test sites (sites) of the chip are tested in parallel, namely the same test vector is set, and meanwhile, a test card is started to test a plurality of chips, but because the test board card is a communication bus between a shared and a work station, the work station needs to sequentially select corresponding board cards to upload through the bus, and then data processing and result judgment are carried out.
The traditional multi-site parallel test can only realize partial parallel of single test items of a chip, namely, the test vector setting and data acquisition stage, the uploading and processing of data and the judgment of results are still serial processing among sites, the overall parallelism is not high, and the chip test efficiency and the test cost are not ideal.
Disclosure of Invention
In order to solve the problems, the invention aims to overcome the defects of the prior art, provide a multithreading processing technology, realize time hiding of three stages of test item test data uploading, test data processing and result judging, greatly improve the chip test parallelism ratio of single Site or multiple sites, reduce test time in multiple, obviously reduce test cost and have high application value.
Specifically, a method for setting and scheduling threads is provided, which comprises the following steps:
s1, thread setting is to program a thread pool in a workstation, wherein the number of accommodating threads is the number of test sites plus 1, namely, a main thread and sub threads which are equal to the number of the test sites are set;
s2, executing thread scheduling, and starting the main thread;
s3, a test vector establishment stage and a test data acquisition stage of a first test item of the main line Cheng Zhihang;
s4, a test vector establishment stage and a test data acquisition stage of a second test item of the main line Cheng Zhihang are started, and a test Site1 (Site 1) sub-thread is started to execute a test data uploading stage of the first test item;
s5, executing a test data processing and result judging stage of the first test item by the test Site1 (Site 1) sub-thread, and simultaneously starting the test Site2 (Site 2) sub-thread to execute a test data uploading stage of the first test item;
s6, after the test data of one test Site (Site) is uploaded in a step S5 mode, executing a flow of test data processing and result judgment of the test Site (Site), and starting a next test Site (Site) sub-thread to execute the test data uploading until all test Site (Site) sub-threads are started and complete the execution of the test data uploading, the test data processing and the result judgment;
s7, circulating the steps S4-S6, sequentially executing the processes of test vector establishment, test data acquisition of the first test item and the second test item until the last test item by the main thread, and sequentially executing the processes of test data uploading, test data processing and result judgment of the previous test item by each test Site (Site) sub-thread;
s8, carrying out thread synchronization on the main thread and the sub thread;
s9, completing the test and destroying the thread pool.
Thus, the present application has the advantages that: the thread execution step realizes the hiding of each test item Upload, calc, judge time, which is equivalent to the fact that each test item is changed from the traditional Setup, meas, upload, calc, judge five stages to the two stages of Setup and Meas, and Upload, calc, judge can realize dislocation hiding, so that the test time is saved.
The invention can also reasonably allocate resources through the application of multithreading, hide the uploading, calculating and processing judging time of the test data, realize the parallelism between the test item and the test Site, achieve very high test efficiency, greatly shorten the test time, reduce the test cost and have very high practical value and popularization value.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate and together with the description serve to explain the invention.
Fig. 1 is a schematic block diagram of a prior art ATE test connection to which the present invention relates.
Fig. 2 is a functional schematic block diagram according to the present invention.
FIG. 3 is a schematic flow chart of a method of thread setup and thread scheduling in accordance with the present invention.
Fig. 4 is a flow chart of test execution in accordance with the present invention.
Fig. 5 is a conventional single site test execution timing diagram.
FIG. 6 is a timing diagram of a conventional multiple site test execution.
FIG. 7 is a multi-threaded multi-site test execution timing diagram.
FIG. 8 is a timing diagram of a multi-threaded data hiding single site test execution.
FIG. 9 is a multi-threaded data hiding multi-site test execution timing diagram.
Detailed Description
In order that the technical content and advantages of the present invention may be more clearly understood, a further detailed description of the present invention will now be made with reference to the accompanying drawings.
As shown in fig. 3, a method for setting and scheduling a thread is provided, which includes the following steps:
s1, thread setting is to program a thread pool in a workstation, wherein the number of accommodating threads is the number of test sites plus 1, namely, a main thread and sub threads which are equal to the number of the test sites are set; the main thread is used for executing data test of each test item to establish Setup and data test to acquire a Meas stage, and the test Site sub-thread is used for executing data uploading load, data processing Calc and result judging Judge stage of each corresponding test Site; the sub-threads are independent sub-threads;
s2, executing thread scheduling, and starting the main thread;
s3, a test vector establishment stage and a test data acquisition stage of a first test item of the main line Cheng Zhihang;
s4, a test vector establishment stage and a test data acquisition stage of a second test item of the main line Cheng Zhihang are started, and a test Site1 (Site 1) sub-thread is started to execute a test data uploading stage of the first test item;
s5, executing a test data processing and result judging stage of the first test item by the test Site1 (Site 1) sub-thread, and simultaneously starting the test Site2 (Site 2) sub-thread to execute a test data uploading stage of the first test item;
s6, after the test data of one test Site (Site) is uploaded in a step S5 mode, executing a flow of test data processing and result judgment of the test Site (Site), and starting a next test Site (Site) sub-thread to execute the test data uploading until all test Site (Site) sub-threads are started and complete the execution of the test data uploading, the test data processing and the result judgment;
s7, circulating the steps S4-S6, sequentially executing the processes of test vector establishment, test data acquisition of the first test item and the second test item until the last test item by the main thread, and sequentially executing the processes of test data uploading, test data processing and result judgment of the previous test item by each test Site (Site) sub-thread;
s8, carrying out thread synchronization on the main thread and the sub thread;
s9, completing the test and destroying the thread pool.
In the step S1, the main thread is configured to execute a data test vector establishment and data test acquisition stage of each test item, and the test site sub-thread is configured to execute a data uploading, data processing and result judging stage of each corresponding test site.
In the step S2, the sub-thread is an independent sub-thread.
Further comprises the steps of establishing all required test items according to the specification definition of the chip, wherein the total number of the test items is N item 。
According to the tester resources, a multi-test site test is established, and the total number of the test sites is N site 。
The number of the multiple test sites can be any number and is 2 n Test stations, where n is a positive integer greater than or equal to 1, including but not limited to 2 test stations, 4 test stations, 8 test stations.
Step S1 establishes thread pool according to the number of test sites, and can accommodate the number of threads as Nthread=N s it e +1。
In addition, taking a test of an SOC chip of pegjingjun integrated circuit corporation as another example, an execution flow is shown in fig. 4, specifically:
1. according to the specification definition of the chip, all required test items are established, and the total number of the test items is N item 。
2. According to the tester resource, establishing multiple site tests, wherein the total site number is N site . Commonly used are e.g. 2site, 4site, 8site etc.
3. And executing each test item by the testing machine, and acquiring the testing time of each stage when each test item is executed. Namely the time required for the test vector Setup (Setup) stage, the test data acquisition (Meas) stage, the test data uploading (Upload) stage, the test data calculation (Calc) and the result judgment (Judge) stage. Fig. 5 is a conventional single Site test execution timing chart, and fig. 6 is a conventional multiple Site test execution timing chart, and takes 2 sites as an example.
4. Establishing thread pool according to Site number, which can accommodate N threads thread ＝N site +1, one of which is the main thread and the others are individual child threads of each site.
5. And creating a main thread from the thread pool according to the test flow.
6. The main thread is started and operated to execute the test vector establishment and acquisition stage of the test item 1, namely the Setup and Meas stages.
7. The main thread executes the Uvload stage of the Site1 test item 1, starts the Site1 sub-thread to execute the Calc+Judge stage of the Site1 test item 1 after completion, and simultaneously, the main thread executes the Uvload stage of the Site2 test item 1, and starts the Site2 sub-thread to execute the Calc+Judge stage of the Site2 test item 1 after completion.
8. Step 7, the main thread executes the uplink of each Site in turn, and starts each Site sub-thread to execute the calc+Judge stage of the corresponding Site according to the sequential scheduling, then performs thread synchronization, and releases each Site sub-thread after all the execution is completed.
9. And (3) circularly executing the steps 6-8, and sequentially completing the tests of the test item 1, the test item 2 and the test item Nitem, namely completing the whole test flow, wherein fig. 7 is a multithreading multi-site test execution time chart.
10. Furthermore, in order to fully utilize the characteristic that the dual-port RAM of the board card of the testing machine can read and write simultaneously, an exclusive data space can be applied and opened up before the main thread is created in the step 5, acquired data is written into the space in each test item Meas stage, and the data in the space is read in the upload stage and is uploaded to a workstation for processing through the bus. The size of the data space should be set to the size of the maximum amount of data required to be acquired by the test item.
11. According to the settings of step 10, the thread scheduling performed in step 6-8 is adjusted. The main thread is only responsible for the setup+meas stage of each test item, and starts setup+meas of test item 2 immediately after setup+meas of test item 1 is finished, and starts Site1 sub-thread to execute the up+calc+judge stage, and starts Site2 sub-thread to execute up+calc+judge after the up of Site1 is finished, thus completing the test of all test items of all sites in sequence, and finally synchronizing each Site sub-thread and releasing and recovering to complete the whole test flow, as in fig. 8, which is a multi-thread data hiding single Site test, and fig. 9, which is a multi-thread data hiding multi-Site test.
12. Furthermore, the time of each test item can be obtained according to the step 3, and the optimized test items can be combined and adjusted, so that the time of each test item Uload+Calc+Judge is smaller than and equal to the time of each test item Setup+Meas as much as possible, and thus, the stages of each test item Uload+Calc+Judge can be completely hidden to the maximum extent, better test parallelism is obtained, test time is reduced, and test cost is reduced.
Taking the Site number as N site The number of the test items is N item The test time of the unit test item is T item The test time of the unit test item Setup, meas, upload, calc, judge stage is T respectively setup 、T meas 、T uplod 、T Calc T and T Judge 。
As can be seen from comparing fig. 5 and 6, the conventional single Site test requires a test time of Setup, meas, upload, calc, judge five stages per test item, and the conventional multi-Site test performs each Site-to-Site Setup and Meas stage of each test item in parallel, which is equivalent to saving Setup plus Meas time by doubling the number of sites, i.e., saving (N) site -1)*(T setup +T meas )。
As can be seen from comparing FIG. 5 with FIG. 8, under single Site test, the multithreading data hiding method of the present invention only requires Setup and Meas time of each test item, and the Upload, calc, judge stage of each test item is hidden to Setup and Meas stage of the following test item, which is equivalent to saving Upload, calc, judge times of the number of test items compared with the conventional single Site test, i.e. saving (N) item -1)*(T uplod +T Calc +T Judge )。
As can be seen from comparing FIG. 6 and FIG. 9, under the multi-Site test, the Upload, calc, judge phase of each test item of the multi-thread data hiding method of the present invention is also hidden to the Setup and Meas phases of the following test item, and the Setup and Meas phases between sites are executed in parallel, which is equivalent to that of the conventional methodThe multiple Site test saves Upload, calc, judge time of the number of test items multiplied by the number of sites, namely N is saved site *(N item -1)*(T uplod +T Calc +T Judge )。
As can be seen by comparing FIG. 5 with FIG. 9, the multithread data hiding method of the present invention is superior to the conventional single Site test in that not only are the Setup and Meas stages of each test item Site executed in parallel, but also the Upload, calc, judge stage of the former test item is hidden into the Setup and Meas stages of the latter test item, thereby saving
(N site -1)*N item *(T setup +T meas )+N site *(N item -1)*(T uplod +T Calc +TJ udge )
＝(N site -1)*(N item -1)*(T setup +T meas )+(N site -1)*(T setup +T meas )+(N site -1)*(N item -1)*(T uplod +T Calc +T Judge )+(N item -1)*(T uplod +T Calc +TJ udge )
＝(N site -1)*(N item -1)*T item +(N site -1)*(T setup +T meas )+(N item -1)*(T uplod +T Calc +TJ udge )
Namely, the set, meas and upload, calc, judge time which are equivalent to the unit test item time of saving the Site number by one times the test item number and the Site time of saving the unit test item time of saving the Site number by one times the test item number are saved, and the test time is greatly reduced as the Site number and the test item number are increased, higher test benefits are obtained under the condition that the Site number with more test item number demands is increased.
Therefore, the method can completely hide the uploading, processing and judging stages of the test data in the single Site or multiple Site test, obtain very ideal parallelism, reduce the test time by times, greatly reduce the test cost and obtain very good use benefits.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations can be made to the embodiments of the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method of thread setting and thread scheduling, comprising the steps of:
s1, thread setting is to program a thread pool in a workstation, wherein the number of accommodating threads is the number of test sites plus 1, namely, a main thread and sub threads which are equal to the number of the test sites are set;
s2, executing thread scheduling, and starting the main thread;
s3, executing a test vector establishment stage and a test data acquisition stage of the test item 1 by the main thread;
s4, the main thread executes a test vector establishment stage and a test data acquisition stage of the test item 2, and simultaneously starts a test site1 sub-thread to execute a test data uploading stage of the test item 1;
s5, executing a test data processing and result judging stage of the test item 1 by the test station 1 sub-thread, and simultaneously starting a test data uploading stage of the test item 1 by the test station 2 sub-thread;
s6, after the test data of one test site is uploaded in the step S5, executing the flow of test data processing and result judgment of the test site, and simultaneously starting the next test site sub-thread to execute the test data uploading until all the test site sub-threads are started and complete the execution of the test data uploading, the test data processing and the result judgment;
s7, circulating the steps S4-S6, sequentially executing the processes of test vector establishment and test data acquisition of the test item 1 and the test item 2 until the last test item by the main thread, and sequentially executing the processes of test data uploading, test data processing and result judgment of the previous test item by each test station sub-thread;
s8, carrying out thread synchronization on the main thread and the sub thread;
s9, completing the test and destroying the thread pool.
2. The method according to claim 1, wherein in the step S1, the main thread is configured to execute a data test vector establishment and data test acquisition phase of each test item, and the test site sub-thread is configured to execute a data upload, data processing and result judgment phase of each corresponding test site.
3. The method of thread setting and thread scheduling according to claim 1, wherein in step S2, the sub-threads are independent sub-threads.
4. The method of thread setting and thread scheduling according to claim 1, further comprising establishing all required test items according to specification definition of the chip, wherein the total number of the test items is N item 。
5. The method for thread setting and thread scheduling according to claim 1, wherein a multi-test site test is established according to tester resources, and the total number of test sites is N site 。
6. The method of thread setting and thread scheduling as recited in claim 5, wherein said multiple test sites is 2 n And a test station, wherein n is a positive integer greater than or equal to 1.
7. The method of thread setting and thread scheduling according to claim 6, wherein said 2 n The test stations are 2 test stations, 4 test stations and 8 test stations.
8. The method of thread setting and thread scheduling according to claim 1, wherein said step S1 is based on a test siteThe number of threads is established to be N thread =N site +1。
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