JP2009284615A - Charging circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charging circuit for suppressing overshoot of an output caused at the time of starting and at the time of a load sudden change. <P>SOLUTION: In the charging circuit with a series regulator structure, a driving transistor 12 drives an output transistor 6 so that voltage Vs obtained by dividing output voltage Vout becomes equal to reference voltage Vref based on error voltage Ve from an error amplifier 4. A comparator 9 compares error voltage Ve from the error amplifier 4 with comparison voltage V10. A switch transistor 11 connected in parallel to a resistor 13 arranged between a power terminal 1 and a gate of the output transistor 6 is turned ON/OFF in accordance with a comparison result. A resistance value between the gate and a source of the output transistor 6 is switched in accordance with a level change of error voltage Ve. Responsibility of the output transistor 6 is then switched, and output overshoot caused at the time of starting and at the time of load sudden change is suppressed thereby. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a charging circuit having a series regulator configuration that is frequently used as a charging device, and more particularly to a technique for suppressing output overshoot that occurs during startup, sudden load change, and the like.

  2. Description of the Related Art Conventionally, a charging circuit having a series regulator configuration is frequently used in a charging device that charges a secondary battery using a power adapter, a battery, or the like as an input DC power source. A series regulator has an output transistor provided between the input terminal and the output terminal, detects the output current and output voltage, and feeds back to the control circuit of the output transistor to stabilize the output current. Operates or operates at a constant voltage to stabilize the output voltage. When such a series regulator is used as a charging circuit, the charging circuit operates at a constant current when the secondary battery connected to the output terminal is at a low battery voltage, and reduces the charging current when the battery is nearly fully charged. In general, it operates at a constant voltage.

  However, the charging circuit having the series regulator configuration has a problem that an overshoot (output overshoot) occurs in the output voltage at the time of start-up and sudden load change. Therefore, a series regulator that suppresses overshoot of the output voltage by performing a soft start operation at the time of startup has been proposed (see, for example, Patent Document 1). Hereinafter, a conventional series regulator capable of suppressing output overshoot at startup will be described with reference to FIG.

  FIG. 3 is a circuit diagram of a conventional series regulator. This series regulator is configured to operate at a constant voltage. First, a configuration for performing a constant voltage operation will be described. As shown in FIG. 3, this series regulator has an output transistor (P-type MOSFET) 26 provided between a power supply terminal (input terminal) 21 to which an input DC voltage is applied and an output terminal 22, The drain voltage of the output transistor 26 is applied to the load 27 connected to the output terminal 22 as the output voltage Vout. The output voltage Vout is divided by the feedback resistor circuit 25. This divided voltage (feedback voltage) Vs is input to the non-inverting input terminal of the error amplifier 24. On the other hand, the reference voltage Vref from the reference voltage source 23 is input to the inverting input terminal of the error amplifier 24 via the CR circuit 28. The error amplifier 24 generates an error voltage Ve having a voltage level corresponding to the voltage difference between the voltage (target voltage) Vr from the CR circuit 28 and the feedback voltage Vs. The generated error voltage Ve is applied to the gate of the output transistor 26.

  As described above, this series regulator has a configuration in which the output voltage Vout detected by the feedback resistor circuit 25 is fed back to the error amplifier 24 which is a control circuit for the output transistor 26. With this configuration, the output transistor 26 is driven so that the feedback voltage Vs becomes equal to the target voltage Vr, and the output voltage Vout of the series regulator is stabilized.

  Next, a configuration for suppressing the overshoot of the output voltage Vout by performing a soft start operation at the start-up when the output voltage Vout starts from 0V will be described.

  This series regulator is configured such that the reference voltage Vref from the reference voltage source 23 is input to the inverting input terminal of the error amplifier 24 via the CR circuit 28 so that output overshoot can be suppressed at startup. That is, when the input DC voltage is input to the power supply terminal 21, the voltage of the power supply terminal 21 rises steeply, and the reference voltage Vref from the reference voltage source 23 rises sharply following the voltage of the power supply terminal 21. The target voltage Vr from the CR circuit 28 applied to the inverting input terminal of the error amplifier 24 rises more slowly than the reference voltage Vref due to the CR time constant of the CR circuit 28. Therefore, at the time of start-up, the output voltage Vout rises so that the feedback voltage Vs follows the target voltage Vr that rises slowly, so that overshoot is suppressed.

  As described above, conventionally, some series regulators have a CR circuit so as to alleviate the rise of the target voltage Vr, which is the target value of the feedback voltage Vs, and suppress output overshoot during startup. However, until now, there has been no series regulator that can suppress output overshoot that occurs during sudden load changes.

  Hereafter, the operation | movement at the time of the load sudden change of the conventional series regulator shown in FIG. 3 mentioned above is demonstrated using FIG. FIG. 4 is an operation waveform diagram of a conventional series regulator, and shows an output current Iout, an output voltage Vout, a feedback voltage Vs, and an error voltage Ve in order from the top.

  As shown in FIG. 4, when the load 27 suddenly becomes light load or drops during steady operation of the series regulator, the output current Iout supplied to the load 27 decreases rapidly (time t1). The voltage Vout and the feedback voltage Vs increase, and the error voltage Ve also increases. However, if the response speed of the error amplifier 24 is slow, the output voltage Vout and the feedback voltage Vs continue to rise, resulting in excessive overshoot. After that, at time t2, when the error voltage Ve, that is, the gate voltage of the output transistor 26 becomes a high potential and the current flowing through the output transistor 26 is sufficiently reduced, the output voltage Vout and the feedback voltage Vs start to decrease. The error voltage Ve also decreases with a delay, and eventually shifts to a steady state in which the feedback voltage Vs and the target voltage Vr become equal.

  As described above, the conventional series regulator cannot suppress the overshoot generated in the output voltage Vout when the load suddenly changes. This overshoot becomes a problem particularly when the secondary battery to be charged is connected to the charging circuit in a state of being incorporated in the electronic device main body. That is, in this case, the output current Iout of the series regulator is the sum of the charging current for the secondary battery and the current consumption of the electronic device main body. In this state, if the consumption current of the electronic device main body is suddenly reduced and an overshoot occurs in the output voltage Vout, an overvoltage may be applied to the connected secondary battery. Such an overvoltage causes the life of the secondary battery to be shortened and the performance to deteriorate. In addition, when the secondary battery being charged is removed while the current consumption of the electronic device main body is zero or low, the output voltage Vout may rise sharply and an excessive overshoot may occur. Such an overvoltage causes a malfunction such as a malfunction of the electronic device or a protection circuit of the electronic device operating.

The overshoot can be reduced if the responsiveness of the error amplifier is increased, but in this case, there is a problem that the circuit current increases.
JP 2005-327027 A

  In view of the above-described conventional problems, the present invention switches the output transistor response at the time of start-up, sudden load change, etc., so that the output generated at the time of start-up, sudden load change, etc. without increasing the circuit current. An object is to provide a charging circuit capable of suppressing overshoot.

  A charging circuit according to claim 1 of the present invention includes an output transistor provided between an input terminal and an output terminal, and an error signal having a signal level corresponding to an error from a target value of an output voltage generated at the output terminal. An error amplifier for generating the output transistor, a control circuit for driving the output transistor so that the output voltage is equal to the target value based on the error signal, and a response of the output transistor according to the signal level of the error signal And a switching circuit for switching the characteristics.

  The charging circuit according to claim 2 of the present invention is the charging circuit according to claim 1, wherein the control circuit includes a drive transistor that drives the output transistor by being driven by the error signal, The switching circuit includes a comparator that compares a signal level of the error signal with a level at which the driving transistor is turned off.

  The charging circuit according to claim 3 of the present invention is the charging circuit according to claim 2, wherein the output transistor is a P-type MOSFET, and a drain thereof is connected to the output terminal. Is an N-type MOSFET, and its drain is connected to the gate of the output transistor.

  The charging circuit according to claim 4 of the present invention is the charging circuit according to claim 3, wherein the switching circuit switches the impedance between the source and the gate of the output transistor, whereby the response of the output transistor is achieved. It is characterized by switching sex.

  The charging circuit according to claim 5 of the present invention is the charging circuit according to claim 4, wherein the switching circuit includes a switch transistor, and the comparator causes the switch transistor to be in a conductive state or a non-conductive state. Thus, the impedance between the source and gate of the output transistor is switched.

  According to the preferred embodiment of the present invention, it is possible to suppress output overshoot that occurs at the time of startup, sudden load change, or the like without causing an increase in circuit current. Therefore, it is useful for a charging circuit that is connected to an electronic device in which a secondary battery is incorporated, supplies power to the electronic device main body, and charges the secondary electrical ground.

  In addition, by using a drive transistor that drives the gate of the output transistor in the control circuit of the output transistor, the feedback system can be opened at the time of start-up, sudden load change, etc., and phase oscillation due to a decrease in phase margin Can be prevented.

  Hereinafter, embodiments of the charging circuit of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of a charging circuit according to an embodiment of the present invention. This charging circuit is a charging circuit having a series regulator configuration.

  In FIG. 1, 1 is a power supply terminal (input terminal), 2 is an output terminal, and 3 is a reference voltage source. An input DC voltage is applied to the power supply terminal 1. An output voltage Vout is generated at the output terminal 2. The reference voltage source 3 is connected to the power supply terminal 1 and generates a reference voltage Vref using the voltage from the power supply terminal 1.

  Reference numeral 4 denotes an error amplifier. The error amplifier 4 generates an error voltage Ve as an error signal having a signal level corresponding to an error from the target value of the output voltage Vout. Specifically, in the error amplifier 4, a reference voltage Vref is applied to the non-inverting input terminal, and a feedback voltage Vs described later is applied to the inverting input terminal, and the error amplifier 4 corresponds to the voltage difference between the reference voltage Vref and the feedback voltage Vs. An error voltage Ve of a voltage level is generated.

  Reference numeral 5 is a feedback resistor circuit, and 6 is an output transistor. Here, a case where the output transistor 6 is a P-type MOSFET will be described as an example. The output transistor 6 is provided between the power supply terminal 1 and the output terminal 2. Specifically, the source is connected to the power supply terminal 1 and the drain is connected to the output terminal 2. The feedback resistor circuit 5 has a configuration in which a resistor having a resistance value R1 and a resistor having a resistance value R2 are connected in series. One end is connected to a connection point between the drain of the output transistor 6 and the output terminal 2, and the other end. Is connected to GND. With this configuration, the feedback resistor circuit 5 generates a feedback voltage Vs obtained by dividing the output voltage Vout. This feedback voltage Vs is applied to the inverting input terminal of the error amplifier 4 as described above.

  Reference numeral 7 denotes a secondary battery, and 8 denotes an electronic device main body. The secondary battery 7 and the electronic device main body 8 are connected to the output terminal 2, and the output voltage Vout is applied. Here, the case where the secondary battery 7 to be charged is connected as a load in a state where it is incorporated in the electronic device main body 8 will be described.

  Further, 9 is a comparator, 10 is a comparison voltage source, and 11 is a switch transistor. Here, a case where the switch transistor 11 is a P-type MOSFET will be described as an example. The comparison voltage source 10 generates a comparison voltage V10. Here, the comparison voltage V10 is set to a level equivalent to a gate threshold value of a driving transistor described later (a level equivalent to a level at which the driving transistor is in a non-passing state). In the comparator 9, the error voltage Ve is applied to the non-inverting input terminal, and the comparison voltage V10 is applied to the inverting input terminal. The switch transistor 11 has a gate connected to the output terminal of the comparator 9. With this configuration, the comparator 9 that monitors the error voltage Ve compares the error voltage Ve with the comparison voltage V10. When the error voltage Ve exceeds the comparison voltage V10, the switch transistor 11 is turned off, and the error voltage Ve becomes the comparison voltage. When the voltage falls below V10, the switch transistor 11 is turned on.

  Reference numeral 12 denotes a drive transistor, and reference numeral 13 denotes a resistor having a resistance value R3. Here, a case where the driving transistor 12 is an N-type MOSFET will be described as an example. The resistor 13 is connected between the power supply terminal 1 and the gate of the output transistor 6. The drive transistor 12 is connected between the gate of the output transistor 6 and GND. Specifically, the drive transistor 12 has a drain connected to the connection point between the resistor 13 and the gate of the output transistor 6, and a source connected to GND. The error voltage Ve is applied to the gate of the drive transistor 12.

  Thus, here, as a control circuit for driving the output transistor 6 so that the output voltage Vout becomes equal to the target value based on the error signal, the output transistor 6 is driven by the error voltage Ve (error signal). A driving transistor 12 is provided. That is, the drive transistor 12 drives the output transistor 6 so that the feedback voltage Vs becomes equal to the reference voltage Vref.

  Reference numeral 14 denotes a resistor having a resistance value R4. The resistor 14 is connected in parallel to the resistor 13 via the switch transistor 11. Specifically, the source of the switch transistor 11 is connected to the connection point between the power supply terminal 1 and the resistor 13, the drain of the switch transistor 11 is connected to one end of the resistor 14, and the other end of the resistor 14 is connected to the resistor 13 and the output transistor. 6 is connected to the connection point with the gate.

  In the present embodiment, the switching circuit that switches the responsiveness of the output transistor 6 in accordance with the signal level of the error signal includes the comparator 9, the comparison voltage source 10, the switch transistor 11, and the resistor 14. That is, in the present embodiment, the resistor 13 is connected in parallel to the resistor 13 via the switch transistor 11, and the comparator 9 turns the switch transistor 11 ON or OFF (conducting state or non-conducting state) according to the error voltage Ve. Thus, the impedance between the source and gate of the output transistor 6 is switched according to the error voltage Ve, and the response of the output transistor 6 is switched.

  Note that the charging circuit in this embodiment does not have a configuration for constant current operation. This is because only the configuration related to the constant voltage operation is described because the present invention aims to suppress the output overshoot.

  FIG. 2 is an operation waveform diagram of the charging circuit according to the embodiment of the present invention. In order from the top, the output current Iout, the output voltage Vout, and the feedback voltage that are the sum of the currents flowing to the secondary battery 7 and the electronic device body 8 are illustrated. Vs and reference voltage Vref, error voltage Ve and comparison voltage V10, operation of switch transistor 11, and gate voltage Vg of output transistor 6 are shown.

First, a description will be given of an operation in a steady state where the output voltage Vout is stabilized at a constant value. In a state where the input DC voltage is applied to the power supply terminal 1, the output transistor 6 is driven so that the output voltage Vout satisfies the following equation, that is, the feedback voltage Vs is equal to the reference voltage Vref.
Vout = Vref × (R1 + R2) / R2

  Specifically, the error amplifier 4 generates an error voltage Ve having a voltage level corresponding to the voltage difference between the feedback voltage Vs and the reference voltage Vref, and the error voltage Ve is applied to the gate of the drive transistor 12 to drive the error voltage Ve. The gate voltage Vg of the output transistor 6 is controlled by the transistor 12 so that the feedback voltage Vs becomes equal to the reference voltage Vref. During this steady operation, the error voltage Ve is equal to or higher than the gate threshold value of the drive transistor 12, so the level of the signal applied from the comparator 9 to the gate of the switch transistor 11 is H level, and the switch transistor 11 is turned off. Yes.

  Next, the operation when the load is suddenly reduced will be described with reference to FIG. When the output current Iout rapidly decreases (time t1) when the electronic device body 8 suddenly becomes lightly loaded or the secondary battery 7 is dropped while the charging circuit is in steady operation. The output voltage Vout and the feedback voltage Vs increase, and the error voltage Ve decreases. When the error voltage Ve falls below the comparison voltage V10 at time t2, the drive transistor 12 is turned off, and the level of the signal applied from the comparator 9 to the gate of the switch transistor 11 is inverted to L level, and the switch transistor 11 is turned on. . Therefore, since the gate voltage Vg of the output transistor 6 is pulled up to the voltage applied to the power supply terminal 1 by the resistor 13 and the resistor 14 connected in parallel, the gate charge of the output transistor 6 is rapidly discharged. As a result, the output transistor 6 is rapidly turned off, so that the output overshoot amount is suppressed.

  Thereafter, the output voltage Vout and the feedback voltage Vs start to decrease, and the error voltage Ve starts to increase after a delay. When the error voltage Ve exceeds the comparison voltage V10 at time t3, the level of the signal applied from the comparator 9 to the gate of the switch transistor 11 is reversed again to the H level, the switch transistor 11 is turned off, and the drive transistor 12 is turned on. It becomes an active state, and normal feedback control for controlling the output voltage Vout works.

  In the period t2 to t3 when the driving transistor 12 is OFF, the feedback system of the charging circuit is in an open state, so that there is no stability problem such as phase margin even when the switch transistor 11 is ON. Further, since the switch transistor 11 is OFF during the ON period of the drive transistor 12 and the drive transistor 12 is OFF during the ON period of the switch transistor 11, a steady current flowing through the resistor 14 is not generated, and the resistor 14 is provided. There is no increase in current consumption due to.

  The charging circuit is also effective in suppressing output overshoot at startup. That is, at the start-up when the input DC voltage is input to the power supply terminal 1, the voltage of the power supply terminal 1 rises steeply, and the reference voltage Vref from the reference voltage source 3 rises sharply following the voltage of the power supply terminal 1. If the output terminal 2 is at the GND potential level at the start-up, the feedback voltage Vs generated in the feedback resistor circuit 5 is also in the GND potential level, and the error voltage Ve is set to raise the feedback voltage Vs to the reference voltage Vref. As a result, the necessary voltage is applied to the gate of the output transistor 6. When the output voltage Vout exceeds “Vref × (R1 + R2) / R2”, the error voltage Ve starts to decrease. Thereafter, an operation similar to that after time t1 described above is performed, and output overshoot is suppressed.

  In the present embodiment, the configuration in which the resistor 14 is connected in parallel to the resistor 13 to reduce the impedance between the gate and the source of the output transistor 6 has been described. However, the present invention is not limited to this configuration. Absent. For example, the resistor 14 can be omitted by using the on-resistance of the switch transistor 11.

  As described above, according to the present embodiment, by switching the responsiveness of the output transistor 6 according to the level change of the error voltage Ve at the time of start-up or sudden load change, the increase in circuit current is not caused. Output overshoot that occurs during startup, sudden load change, etc. can be suppressed.

  Further, since the drive transistor is used to drive the gate of the output transistor, the feedback system can be opened at the time of start-up, sudden load change, etc., and phase oscillation due to a decrease in phase margin can be prevented.

  The charging circuit according to the present invention can suppress an output overshoot that occurs at the time of start-up or sudden load change without causing an increase in circuit current, and can be connected to an electronic device in which a secondary battery is incorporated. It is useful for a charging circuit that supplies power to the main body and charges the secondary electrical ground.

The circuit diagram which shows the example of 1 structure of the charging circuit in embodiment of this invention Operation waveform diagram at the time of sudden decrease in load of the charging circuit in the embodiment of the present invention Circuit diagram of conventional series regulator Waveform diagram of conventional series regulator when load decreases suddenly

Explanation of symbols

1, 21 Power supply terminal 2, 22 Output terminal 3, 23 Reference voltage source 4, 24 Error amplifier 5, 25 Feedback resistance circuit 6, 26 Output transistor 7 Secondary battery 8 Electronic device body 9 Comparator 10 Comparison voltage source 11 Switch transistor 12 Drive transistor 13 Resistor 14 Resistor 27 Load 28 CR circuit

Claims (5)

An output transistor provided between the input terminal and the output terminal;
An error amplifier that generates an error signal having a signal level corresponding to an error from a target value of the output voltage generated at the output terminal;
A control circuit for driving the output transistor based on the error signal so that the output voltage is equal to the target value;
A switching circuit that switches the response of the output transistor in accordance with the signal level of the error signal;
With a charging circuit. The control circuit includes a drive transistor that drives the output transistor by being driven by the error signal,
The charging circuit according to claim 1, wherein the switching circuit includes a comparator that compares a signal level of the error signal with a level at which the driving transistor is in a non-conductive state. The output transistor is a P-type MOSFET, and its drain is connected to the output terminal,
3. The charging circuit according to claim 2, wherein the driving transistor is an N-type MOSFET, and a drain thereof is connected to a gate of the output transistor.   4. The charging circuit according to claim 3, wherein the switching circuit switches responsiveness of the output transistor by switching impedance between a source and a gate of the output transistor.   5. The switch circuit according to claim 4, wherein the switching circuit includes a switch transistor, and the comparator switches the impedance between the source and the gate of the output transistor when the switch transistor is turned on or off. Charging circuit.

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