JP2009277771A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has a low-density impurity region made low in resistance by suppressing an increase in junction depth, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device is provided with: an internal transistor having a first gate electrode 103a, a first impurity region 106a containing a first impurity, and a first inside side wall spacer 107a and a first outside side wall spacer 109a formed on a side surface of the first gate electrode; and an input/output transistor having a second gate electrode 103b, a second impurity region 106b containing an impurity of the same conductivity type with the first impurity, and a second inside side wall spacer 107b and a second outside side wall spacer 109b formed on a side surface of the second gate electrode 103b. The second inside side wall spacer 107b contains the second impurity in an interface region formed with the second outside side wall spacer 109b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a plurality of MIS (Metal Insulator Semiconductor) transistors and a manufacturing method thereof.

In order to realize miniaturization and high speed required for semiconductor integrated circuits in recent years, it is required to achieve both improvement in driving capability and reduction in parasitic capacitance while miniaturizing the gate dimensions of transistors.
As one of the effective methods for improving the driving capability of the transistor, the impurity implantation amount in the ion implantation process is increased when forming a low concentration impurity region adjacent to the high concentration impurity region which becomes the source / drain region of the transistor. There is a method of reducing the resistance of the low-concentration impurity region. However, according to the above method, the amount of overlap between the gate electrode and the low concentration impurity region increases. As a result, the effective gate length of the transistor is reduced and the short channel effect is deteriorated, so that miniaturization of the gate dimension is hindered. In addition, an increase in the amount of overlap increases a parasitic capacitance between the gate electrode and the source / drain region, which hinders high-speed operation of the transistor.

  Therefore, in an internal circuit transistor that requires high driving power and reduced parasitic capacitance, by performing ion implantation for forming a low concentration impurity region after forming a sidewall insulating film on the sidewall of the gate electrode, The resistance of the low-concentration impurity region is reduced without increasing the amount of overlap with the gate electrode. Here, in a semiconductor device including an internal transistor having a thin gate insulating film and an input / output transistor having a thick gate insulating film, a manufacturing method for performing ion implantation after forming a sidewall insulating film of the gate electrode of the internal transistor Is shown (for example, refer to Patent Document 1). Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to FIGS. FIGS. 10A to 10D, FIGS. 11A to 11C, and FIGS. 12A and 12B are cross-sectional views showing a conventional method for manufacturing a semiconductor device.

  First, as shown in FIG. 10A, an element isolation region 401 made of a silicon oxide film or the like is formed on a semiconductor substrate 400 made of p-type silicon. Thereby, active regions 400a and 400b made of the semiconductor substrate 400 surrounded by the element isolation region 401 are formed. Thereafter, a first gate insulating film 402a made of a silicon oxide film is formed on the active region 400a, and a second gate insulating film 402b made of a silicon oxide film is formed on the active region 400b. Next, a first gate electrode 403a made of a polycrystalline silicon film is formed on the first gate insulating film 402a, and a second gate electrode made of a polycrystalline silicon film is formed on the second gate insulating film 402b. 403b is formed.

  Next, as illustrated in FIG. 10B, a resist 406 that covers the active region 400 a is formed on the semiconductor substrate 400. Next, phosphorus is ion-implanted using the resist 406 as a mask, thereby forming a low-concentration impurity region 407b serving as an extension region or LDD region of the input / output transistor under the second gate electrode 403b in the active region 400b. Thereafter, the resist 406 is removed by ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia hydrogen peroxide cleaning.

  Next, as shown in FIG. 10C, an insulating film 408 made of a silicon oxide film having a thickness of 10 nm is deposited on the entire surface of the semiconductor substrate 400 so as to cover the active regions 400a and 400b. Subsequently, as shown in FIG. 10D, the insulating film 408 is subjected to anisotropic dry etching to form an offset spacer 408a on the side wall of the first gate electrode 403a and the second gate electrode 403b. An offset spacer 408b is formed on the side wall.

  Next, as illustrated in FIG. 11A, a resist 411 that covers the active region 400 b is formed on the semiconductor substrate 400. Next, arsenic is ion-implanted using the resist 411 as a mask to form a low-concentration impurity region 407a serving as an extension region or LDD region of the internal transistor below the side of the first gate electrode 403a in the active region 400a.

  Next, as shown in FIG. 11B, the resist 411 is removed by ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia hydrogen peroxide cleaning, and then the active regions 400 a and 400 b are covered over the entire surface of the semiconductor substrate 400. Then, an insulating film 413 made of a silicon oxide film with a thickness of 10 nm is deposited. Subsequently, an insulating film 414 made of a silicon nitride film having a thickness of 40 nm is deposited on the insulating film 413.

  Next, as shown in FIG. 11C, the insulating films 414 and 413 are anisotropically dry-etched, whereby the first gate electrode 403a is formed on the side wall of the first insulating film 413 via the offset spacer 408a. The inner side wall spacer 413a and the first outer side wall spacer 414a made of the insulating film 414 are formed, and the second inner side made of the insulating film 414 is formed on the side wall of the second gate electrode 403b via the offset spacer 408b. A second outer side wall spacer 414b including the side wall spacer 413b and the insulating film 414 is formed. Thus, a sidewall spacer 415a composed of a first inner sidewall spacer 413a and a first outer sidewall spacer 414a is formed in the internal transistor region, and a second inner sidewall is formed in the input / output transistor region. Sidewall spacers 415b composed of spacers 413b and second outer side wall spacers 414b are formed.

  Next, as shown in FIG. 12A, arsenic is formed in the active regions 400a and 400b using the first gate electrode 403a, the second gate electrode 403b, the offset spacers 408a and 408b, and the side wall spacers 415a and 415b as masks. Are ion-implanted to form a high-concentration impurity region 417a serving as a source / drain region of the internal transistor and a high-concentration impurity region 417b serving as a source / drain region of the input / output transistor region.

  Next, as shown in FIG. 12B, silicide films 419a and 419b are formed on the first gate electrode 403a and the high-concentration impurity region 417a, and on the second gate electrode 403b and the high-concentration impurity region 417b, respectively. Respectively. Next, after an interlayer insulating film 421 is formed on the entire surface of the semiconductor substrate 400, contact plugs 423a and 423b penetrating the interlayer insulating film 421 are formed on the silicide films 419a and 419b, respectively. Subsequently, metal wirings 424a and 424b connected to the contact plugs 423a and 423b, respectively, are formed.

In this conventional manufacturing method, after forming an offset spacer 408a on the side wall of the first gate electrode 403a, ion implantation is performed to form a low concentration impurity region 407a of the internal transistor. As a result, in the MOS transistor having a predetermined effective channel length, the overlap length between the first gate electrode 403a and the low-concentration impurity region 407a which is a part of the source / drain region can be shortened, and the overlap capacitance can be reduced. Can be reduced.
JP 2003-86704 A

  However, in the conventional method, after forming the low-concentration impurity region 407a of the input / output transistor, the silicon surface of the semiconductor substrate 400 in the internal transistor region is about 0.5 nm in an ammonia overwater cleaning step for removing the resist 406. It will be wet etched to some extent. In the above-described conventional method, the case where one type of N-type input / output transistor is formed has been shown. However, for example, N-type and P-type input transistors can be applied to a plurality of power supply voltages such as 3.3V system and 1.8V system. When each output transistor is formed, since the number of wet etching increases, the wet etching amount of the semiconductor substrate in the internal transistor region increases to about 2 nm. Since the ion implantation for forming the low concentration impurity region of the internal transistor region is performed on the wet etched semiconductor substrate, the junction of the low concentration impurity region may be deepened by the amount of wet etching of the substrate. It becomes a problem. Here, with the miniaturization of the transistor, it is necessary to make the low-concentration impurity region of the internal transistor shallow. For example, in a 32 nm generation semiconductor device, since a shallow junction of 15 nm or less is required, the amount of wet etching of the semiconductor substrate before ion implantation must be reduced.

  In view of the above, an object of the present invention is to provide a semiconductor device having a low-concentration impurity region in which the junction depth is suppressed and having a low resistance and a high driving capability, and a method for manufacturing the same. .

  In order to achieve the above object, a semiconductor device of the present invention is a semiconductor device including a first MIS transistor and a second MIS transistor, wherein the first MIS transistor is on a first active region in a semiconductor substrate. A first gate insulating film formed on the first gate insulating film; a first gate electrode formed on the first gate insulating film; and formed laterally below the first gate electrode in the first active region. A first impurity region formed by diffusing the first impurity, a first inner sidewall spacer formed on a side surface of the first gate electrode and having an L-shaped cross section, and the first A first outer side wall spacer formed on an L-shaped inner surface of the inner side wall spacer, and the second MIS transistor has a second active side in the semiconductor substrate. A second gate insulating film formed on the region, a second gate electrode formed on the second gate insulating film, and laterally below the second gate electrode in the second active region Formed on the side surface of the second gate electrode and a second impurity region formed by diffusing a second impurity of the same conductivity type as the first impurity and having an L-shaped cross section A second inner side wall spacer; and a second outer side wall spacer formed on an L-shaped inner surface of the second inner side wall spacer. The second impurity is contained in an interface region with the second outer sidewall spacer.

  In this configuration, when the second impurity region is formed, the semiconductor substrate is ion-implanted in a state covered with the insulating film constituting the second inner side wall spacer, so that the impurity is also injected into the insulating film. As a result, the second inner side wall spacer containing the second impurity is formed. On the other hand, since the insulating film constituting the first inner side wall spacer is provided after the formation of the first impurity region and at the time of forming the second impurity region, the insulating film is formed at the time of forming the first impurity region. The first impurity is not implanted into the first electrode.

  As described above, in the configuration of the present invention, the first impurity region is formed before the second impurity region is formed. Therefore, the wet etching process is performed before the formation of the first impurity region. Can be avoided. Thereby, the junction of the first impurity region can be formed relatively shallow, and the parasitic resistance of the first impurity region can be reduced. As a result, in the semiconductor device of the present invention, it is possible to realize a semiconductor device that includes the first MIS transistor having the first impurity region with a low resistance and has sufficient driving capability.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a first MIS transistor formed in a first active region of a semiconductor substrate; a second MIS transistor formed in a second active region of the semiconductor substrate; (A) forming a first gate insulating film on the first active region and forming a second gate insulating film on the second active region. (B) forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film; and the first active region A step (c) of forming a first impurity region by ion-implanting a first impurity under the side of the first gate electrode in the step, and after the step (c), on the semiconductor substrate The first activity A step (d) of forming a first insulating film covering the region and the second active region; and passing through the first insulating film below the side of the second gate electrode in the second active region. A step (e) of forming a second impurity region by ion-implanting a second impurity having the same conductivity type as the first impurity; and after the step (e), on the first insulating film A step (f) of forming a second insulating film; and anisotropically etching the first insulating film and the second insulating film to form the second insulating film on the side surface of the first gate electrode. Forming a first inner side wall spacer having an L-shaped cross section made of one insulating film and a first outer side wall spacer made of the second insulating film, and on a side surface of the second gate electrode; Further, the cross-sectional shape made of the first insulating film is L And a Jo second inner sidewall spacers and forming a second outer side wall spacer made of the second insulating film (g).

  According to this method, it is not necessary to form a resist in the first MIS transistor region before forming the first impurity region, and wet etching for removing the resist is not performed. Therefore, the first MIS transistor It is possible to avoid the surface of the semiconductor substrate from being scraped in the region. As a result, the junction depth of the first impurity region can be suppressed from increasing. Further, when the second impurity region is formed, the first MIS transistor region is protected by the first insulating film, so that a resist that covers the first MIS transistor region when the second impurity region is formed. Even if formed, the surface of the first impurity region provided in the first MIS transistor region can be prevented from being scraped. Therefore, when the method for manufacturing a semiconductor device of the present invention is used, an increase in junction depth is suppressed, and a MIS transistor having a first impurity region with a small parasitic resistance can be formed. In addition, a semiconductor device having a high driving capability can be manufactured.

  According to the semiconductor device and the manufacturing method thereof of the present invention, since the MIS transistor having the first impurity region having a shallow junction and a low resistance is provided, the semiconductor device that can operate at high speed even when miniaturized. Can be realized.

(First embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a first embodiment of the present invention will be described with reference to the drawings. 1A to 1D, FIGS. 2A to 2D, and FIGS. 3A and 3B are cross-sectional views illustrating a method for manufacturing a semiconductor device of this embodiment.

  First, as shown in FIG. 1A, an element isolation region 101 made of a silicon oxide film or the like is formed on a semiconductor substrate 100 made of p-type silicon by, for example, an STI (Shallow Trench. Isolation) method. Thus, active regions 100a and 100b made of the semiconductor substrate 100 surrounded by the element isolation region 101 are formed. Thereafter, a first gate insulating film 102a made of a silicon oxide film with a film thickness of 2 nm, for example, is formed on the active region 100a, and a second film made of a silicon oxide film with a film thickness of 5 nm, for example, is formed on the active area 100b. The gate insulating film 102b is formed. Next, a first gate electrode 103a made of a polycrystalline silicon film is formed on the first gate insulating film 102a, and a second gate electrode made of a polycrystalline silicon film is formed on the second gate insulating film 102b. 103b is formed.

  Next, as shown in FIG. 1B, an insulating film 104 made of a silicon oxide film having a thickness of, for example, 7 nm is formed on the entire surface of the semiconductor substrate 100 so as to cover the active regions 100a and 100b.

  Next, as shown in FIG. 1C, by performing anisotropic dry etching on the insulating film 104, an offset spacer 104a made of the insulating film 104 having a thickness of, for example, 5 nm is formed on the side wall of the first gate electrode 103a. And an offset spacer 104b made of an insulating film 104 having a thickness of, for example, 5 nm is formed on the sidewall of the second gate electrode 103b.

  Next, as illustrated in FIG. 1D, a resist 105 that covers the active region 100 b is formed on the semiconductor substrate 100. Next, using the resist 105 as a mask, for example, n-type impurity arsenic (first impurity) is ion-implanted to extend the extension region or the LDD region of the internal transistor below the side of the first gate electrode 103a in the active region 100a. A low concentration impurity region (first impurity region) 106a is formed.

  Next, as shown in FIG. 2A, the resist 105 is removed by ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia hydrogen peroxide cleaning, and then the active regions 100a and 100b are covered over the entire surface of the semiconductor substrate 100. For example, an insulating film 107 made of a silicon oxide film having a thickness of 10 nm is deposited.

  Next, as illustrated in FIG. 2B, a resist 108 that covers the active region 100 a is formed on the semiconductor substrate 100. Next, using the resist 108 as a mask, for example, an n-type impurity such as phosphorus (second impurity) is ion-implanted through the insulating film 107, so that the input and output transistors of the active region 100b are laterally below the second gate electrode 103b. A low concentration impurity region (second impurity region) 106b to be an extension region or an LDD region is formed. At this time, phosphorus is also ion-implanted into a portion of the insulating film 107 covering the active region 100b.

  Next, as shown in FIG. 2C, the resist 108 is removed by ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia hydrogen peroxide cleaning, and then the active regions 100a and 100b are covered on the insulating film 107, for example, An insulating film 109 having a thickness of 30 nm and made of a silicon nitride film is formed.

  Subsequently, as shown in FIG. 2D, the insulating films 109 and 107 are subjected to anisotropic dry etching, whereby the first gate electrode 103a is made of the first insulating film 107 through the offset spacer 104a. The inner side wall spacer 107a and the first outer side wall spacer 109a made of the insulating film 109 are formed, and the second inner side made of the insulating film 107 is formed on the side wall of the second gate electrode 103b via the offset spacer 104b. A second outer side wall spacer 109b including the side wall spacer 107b and the insulating film 109 is formed. As a result, a sidewall spacer 110a composed of the first inner side wall spacer 107a and the first outer side wall spacer 109a is formed in the internal transistor region, and the second inner side wall is formed in the input / output transistor region. A side wall spacer 110b composed of the spacer 107b and the second outer side wall spacer 109b is formed. The second inner side wall spacer 107b contains phosphorus, which is an impurity of the low concentration impurity region 106b. However, the first inner side wall spacer 107a contains arsenic, which is an impurity of the low concentration impurity region 106a. Not included.

  Next, as shown in FIG. 3A, for example, in the active regions 100a and 100b, the first gate electrode 103a, the second gate electrode 103b, the offset spacers 104a and 104b, and the sidewall spacers 110a and 110b are used as masks. By ion-implanting n-type impurity arsenic, a high-concentration impurity region 111a serving as the source / drain region of the internal transistor and a high-concentration impurity region 111b serving as the source / drain region of the input / output transistor region are formed.

  Next, as shown in FIG. 3B, silicide films 112a and 112b are formed on the first gate electrode 103a and the high-concentration impurity region 111a, and on the second gate electrode 103b and the high-concentration impurity region 111b. Form each one. Next, after forming an interlayer insulating film 113 on the entire surface of the semiconductor substrate 100, contact plugs 114a and 114b penetrating the interlayer insulating film 113 are formed on the silicide films 112a and 112b, respectively. Subsequently, metal wirings 115a and 115b connected to the contact plugs 114a and 114b, respectively, are formed. The semiconductor device of this embodiment can be manufactured through the above steps.

  The feature of the semiconductor device manufacturing method of this embodiment is that the ion implantation process of the input / output transistor region is not performed until the step of forming the low-concentration impurity region 106a of the internal transistor region shown in FIG. According to this method, it is not necessary to form a resist in the internal transistor region before forming the low-concentration impurity region 106a, and wet etching for removing the resist is not performed. The silicon surface can be prevented from being scraped. As a result, the junction depth of the low-concentration impurity region 106a in the internal transistor region can be suppressed from increasing. Furthermore, in the manufacturing method of this embodiment, when the low concentration impurity region 106b in the input / output transistor region is formed by ion implantation, a resist 108 is formed on the insulating film 107 to cover the internal transistor region. The low concentration impurity region 106a is protected by the insulating film 107, and the surface of the low concentration impurity region 106a can be prevented from being scraped when the resist 108 is removed. Therefore, when the manufacturing method of this embodiment is used, an increase in junction depth is suppressed, and an internal transistor having a low-concentration impurity region 106a with low parasitic resistance can be formed. A semiconductor device having the same can be realized.

  Here, the configuration of the low-concentration impurity region 106a of the internal transistor formed by the manufacturing method of this embodiment will be described with reference to FIG. 4A is a cross-sectional view showing the configuration of the low-concentration impurity region of the internal transistor according to this embodiment, and FIG. 4B is a cross-sectional view showing the configuration of the low-concentration impurity region of the conventional internal transistor. It is.

  As shown in FIGS. 4A and 4B, in the low concentration impurity region formed by the manufacturing method of the present embodiment, the amount of chipping of the substrate is smaller than that of the conventional low concentration impurity region 407a. In the low-concentration impurity region 407a formed by the conventional method, the amount of chipping of the substrate becomes large. Therefore, the depth (junction depth) from the interface between the gate insulating film 402a and the semiconductor substrate 400 to the lower surface of the low-concentration impurity region 407a. As a result, the current path under the end of the gate electrode 403a is expanded, and the parasitic resistance of the low-concentration impurity region 407a is increased. On the other hand, in this embodiment, the junction depth of the low-concentration impurity region 106a from the interface between the gate insulating film 102a and the semiconductor substrate 100 can be reduced by about 0.5 to 2.0 nm, for example, The short channel effect, that is, the threshold voltage drop when the gate length is reduced can be reduced by about 10%. As a result, it is possible to form a low-concentration impurity region that is made shallow and in which an increase in parasitic resistance is suppressed.

  In the semiconductor device manufacturing method of this embodiment, the first inner side wall spacer 107a and the second inner side wall spacer 107b are formed using the insulating film 107 provided as a protective film for the low concentration impurity region 106a. Since it is formed, it is not necessary to separately form an insulating film for the inner side wall spacer, and the manufacturing cost can be reduced.

  Further, in the method of manufacturing the semiconductor device of this embodiment, the offset spacer 104a made of the insulating film 104 is formed with a relatively thin film thickness of 5 nm in the step shown in FIG. ), An increase in the amount of overlap between the first gate electrode 103a and the low-concentration impurity region 106a can be suppressed. As a result, deterioration of characteristics due to the short channel effect can be suppressed. The material of the insulating film 104 is not limited to a silicon oxide film, and for example, a silicon nitride film or the like may be used.

  In the step shown in FIG. 2B, ions may be implanted into the active region 100b from a direction inclined by, for example, 10 degrees to 45 degrees with respect to a direction perpendicular to the semiconductor substrate 100. Thus, even when ion implantation is performed through the insulating film 107, the amount of overlap between the second gate electrode 103b and the low-concentration impurity region 106b can be controlled, and an input / output transistor having desired characteristics is formed. be able to.

  Next, the configuration of the semiconductor device formed by the semiconductor device manufacturing method of this embodiment will be described with reference to FIG. As shown in FIG. 3B, the semiconductor device of this embodiment includes an internal transistor and an input / output transistor on the same semiconductor substrate. The internal transistor is formed below the first gate insulating film 102a and the first gate electrode 103a formed on the active region 100a in the semiconductor substrate 100, and laterally below the first gate electrode 103a in the active region 100a. For example, a low-concentration impurity region 106a formed by diffusing an n-type first impurity such as phosphorus, an offset spacer 104a formed on the side surface of the first gate electrode 103a, and a side surface of the offset spacer 104a are formed. And a first inner side wall spacer 107a having an L-shaped cross section, and a first outer side wall spacer 109a formed on the L-shaped inner surface of the first inner side wall spacer 107a. .

  On the other hand, the input / output transistor is formed laterally below the second gate insulating film 102b and the second gate electrode 103b formed on the active region 100b in the semiconductor substrate 100 and the second gate electrode 103b in the active region 100b. A low-concentration impurity region 106b formed by diffusing an n-type second impurity such as arsenic, an offset spacer 104b formed on the side surface of the second gate electrode 103b, and a side surface of the offset spacer 104b A second inner side wall spacer 107b having an L-shaped cross section, and a second outer side wall spacer 109b formed on the L-shaped inner surface of the second inner side wall spacer 107b. I have.

  Here, in the semiconductor device of the present embodiment, the second inner side wall spacer 107b has the same second impurity as the impurity diffused in the low concentration impurity region 106b in the interface region with the second outer side wall spacer 109b. Contains impurities. On the other hand, the first inner side wall spacer 107a does not contain the same first impurity as the impurity diffused in the low concentration impurity region 106a in the interface region with the first outer side wall spacer 109a. As described above, the configuration of the inner sidewall spacers is different from each other because the formation process of the low-concentration impurity regions 106a and 106b is different from each other.

  First, when forming the low-concentration impurity region 106b, the semiconductor substrate 100 is ion-implanted in a state covered with the insulating film constituting the second inner side wall spacer 107b, so that the impurity is also implanted into the insulating film. As a result, the second inner side wall spacer 107b having the second impurity is obtained. In particular, in the semiconductor device of the present embodiment, the second inner side wall spacer 107b contains the second impurity in the L-shaped corner portion in the interface region with the second outer side wall spacer 109b. This is a point different from the conventional semiconductor device. In the conventional semiconductor device, even if impurities are not implanted into the inner side wall spacer when the low concentration impurity region is formed, the exposed portion of the inner side wall spacer (on the outer side wall spacer) Impurities for forming high-concentration impurity regions are implanted into uncovered upper and lower ends. However, since the L-shaped corner portion of the inner sidewall spacer is covered with the outer sidewall spacer, no impurity is implanted.

  Next, since the insulating film constituting the first inner sidewall spacer 107a is provided after the formation of the low concentration impurity region 106a and at the time of forming the low concentration impurity region 106b, when the low concentration impurity region 106a is formed, The first impurity is not implanted into the insulating film. In particular, in the semiconductor device of the present embodiment, the first inner sidewall spacer 107a does not contain the first impurity in the L-shaped corner portion in the interface region with the first outer sidewall spacer 109a. . This is because, for example, the first impurity for forming the high concentration impurity region 111a is formed in the exposed portion of the first inner sidewall spacer 107a when the high concentration impurity region 111a is formed after the low concentration impurity region 106a is formed. This is because the L-shaped corner portion of the first inner side wall spacer 107a is covered with the first outer side wall spacer 109a, so that the first impurity is not injected.

  According to the above configuration, the low-concentration impurity region 106a of the internal transistor is formed without going through the wet etching step, so that the junction of the low-concentration impurity region 106a can be formed relatively shallow, and the low-concentration impurity region The parasitic capacitance of 106a can be reduced. As a result, a semiconductor device including an internal transistor having a low-concentration impurity region 106a with low resistance and having sufficient driving capability can be realized.

  In the semiconductor device and the manufacturing method thereof according to the present embodiment, it is preferable that the film thickness of the first gate insulating film 102a is smaller than the film thickness of the second gate insulating film 102b. By reducing the thickness of the first gate insulating film 102a provided in the internal transistor region, an internal transistor that can operate at high speed can be realized. Further, by making the thickness of the second gate insulating film 102b provided in the input / output transistor region larger than the thickness of the first gate insulating film 102a, for example, a transistor requiring a relatively large breakdown voltage is formed. Even so, the second gate insulating film 102b can be prevented from being broken, and an input / output transistor having desired characteristics can be realized.

  In the semiconductor device and the manufacturing method thereof according to the present embodiment, the semiconductor device provided with the n-type internal transistor and the n-type input / output transistor on the same semiconductor substrate is taken as an example. However, the semiconductor device is not limited thereto. Absent. For example, not only an n-type transistor but also a p-type internal transistor and an input / output transistor are provided, and a semiconductor device in which a plurality of transistors are formed can provide the same effects as those of the present embodiment.

(Second Embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a second embodiment of the present invention will be described with reference to the drawings. 5A, 5B, 6A, and 6B are cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. In the manufacturing method of the present embodiment, the same steps as those shown in FIGS. 1A to 1D, FIGS. 2A and 2B in the manufacturing method of the first embodiment are performed, and then FIG. The process shown in (a) is performed. Therefore, steps similar to those in the manufacturing method according to the first embodiment will be briefly described.

  First, the configuration shown in FIG. 2B is obtained by the same steps as those shown in FIGS. 1A to 1D and FIGS. 2A and 2B.

  Next, as shown in FIG. 5A, after the resist 108 is removed by ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia water / aqueous cleaning, the active regions 100a and 100b are covered on the insulating film 107, for example, An insulating film 116 having a thickness of 5 nm and made of a silicon oxide film, and an insulating film 109 having a thickness of 30 nm and made of a silicon nitride film, for example, are sequentially formed.

  Next, as shown in FIG. 5B, by performing anisotropic dry etching on the insulating films 109, 116, and 107, in the internal transistor region, the sidewall of the first gate electrode 103a is interposed via the offset spacer 104a. , A first inner side wall spacer 107 a made of an insulating film 107, a first intermediate side wall spacer 116 a made of an insulating film 116, and a first outer side wall spacer 109 a made of an insulating film 109. 110a is formed. At the same time, in the input / output transistor region, the second inner side wall spacer 107b made of the insulating film 116 and the second intermediate side made of the insulating film 116 are formed on the side wall of the second gate electrode 103b via the offset spacer 104b. A side wall spacer 110b including the wall spacer 116b and the second outer side wall spacer 109b made of the insulating film 109 is formed. The second inner side wall spacer 107b contains phosphorus, which is an impurity of the low concentration impurity region 106b. However, the first inner side wall spacer 107a contains arsenic, which is an impurity of the low concentration impurity region 106a. Not included.

  Next, as shown in FIG. 6A, for example, the active regions 100a and 100b are formed in the active regions 100a and 100b using the first gate electrode 103a, the second gate electrode 103b, the offset spacers 104a and 104b, and the sidewall spacers 110a and 110b as masks. By ion-implanting n-type impurity arsenic, a high-concentration impurity region 111a serving as the source / drain region of the internal transistor and a high-concentration impurity region 111b serving as the source / drain region of the input / output transistor region are formed.

  Subsequently, as shown in FIG. 6B, silicide films 112a and 112b are formed on the first gate electrode 103a and the high-concentration impurity region 111a, and on the second gate electrode 103b and the high-concentration impurity region 111b. Form each one. Next, after forming an interlayer insulating film 113 on the entire surface of the semiconductor substrate 100, contact plugs 114a and 114b penetrating the interlayer insulating film 113 are formed on the silicide films 112a and 112b, respectively. Subsequently, metal wirings 115a and 115b connected to the contact plugs 114a and 114b, respectively, are formed. The semiconductor device of this embodiment can be manufactured through the above steps.

  According to the method for manufacturing a semiconductor device of this embodiment, it is not necessary to form a resist in the internal transistor region before forming the low-concentration impurity region 106a, as in the first embodiment. It is possible to avoid the silicon surface of the semiconductor substrate 100 of the internal transistor from being scraped by wet etching. Further, since the internal transistor region is protected by the insulating film 107 when the low concentration impurity region 106b is formed, the surface of the low concentration impurity region 106a can be prevented from being scraped when the resist 108 is removed. Therefore, when the semiconductor device manufacturing method of this embodiment is used, an internal transistor having a low-concentration impurity region 106a having a shallow junction and a low parasitic resistance can be formed, and a semiconductor device having a high driving capability even when miniaturized. Can be realized.

  Note that the configuration of the semiconductor device of this embodiment is different from that of the first embodiment only in the configuration of the sidewall spacers 110a and 110b, and thus detailed description thereof is omitted. In the semiconductor device of the present embodiment, the side wall spacers 110a and 110b are further provided with a first intermediate side wall spacer 116a and a second intermediate side wall spacer 116b, respectively. Here, the second inner side wall spacer 107b has the same second impurity as the impurity diffused in the low-concentration impurity region 106b in the interface region with the second intermediate side wall spacer 116b in the L-shaped corner portion. Contains. On the other hand, the first inner side wall spacer 107a contains the same first impurity as the impurity diffused in the low concentration impurity in the interface region with the first intermediate side wall spacer 116a in the L-shaped corner. Not. With this configuration, it is possible to realize a semiconductor device including an internal transistor having a low-concentration impurity region 106a having a shallow junction and a low parasitic resistance, and having a high driving capability.

(Third embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to a third embodiment of the present invention will be described with reference to the drawings. 7A to 7D, 8A to 8D, 9A, and 9B are cross-sectional views illustrating the method for manufacturing the semiconductor device of the present embodiment. Note that the semiconductor device manufacturing method of the present embodiment differs from the manufacturing method of the first embodiment in the configuration of the gate insulating film and the gate electrode. Accordingly, the same parts are denoted by the same reference numerals, and detailed description thereof is omitted.

  First, as shown in FIG. 7A, an element isolation region 101 made of a silicon oxide film or the like is formed on a semiconductor substrate 100 made of p-type silicon. Thus, active regions 100a and 100b made of the semiconductor substrate 100 surrounded by the element isolation region 101 are formed. Thereafter, on the active region 100a, for example, a first gate insulating film 120a in which a high dielectric constant film having a thickness of 2 nm is stacked on a silicon oxide film having a thickness of 1 nm is formed, and on the active region 100b, For example, the second gate insulating film 120b in which a high dielectric constant film having a thickness of 2 nm is stacked on a silicon oxide film having a thickness of 5 nm is formed. Next, a first gate electrode 123a composed of a metal film 121a made of a refractory metal on the first gate insulating film 120a and a silicon film 122a made of a polycrystalline silicon film and formed on the metal film 121a. The second gate insulating film 120b is formed of a metal film 121b made of a refractory metal and a silicon film 122b made of a polycrystalline silicon film and formed on the metal film 121b. A gate electrode 123b is formed.

  Next, as shown in FIGS. 7B and 7C, an insulating film 104 made of a silicon oxide film having a thickness of 7 nm, for example, is formed on the entire surface of the semiconductor substrate 100 so as to cover the active regions 100a and 100b. Thereafter, the insulating film 104 is anisotropically dry-etched to form offset spacers 104a made of the insulating film 104 with a thickness of, for example, 5 nm on the sidewalls of the first gate electrode 123a and the second gate electrode 123b, and for example, a film Offset spacers 104b each having a thickness of 5 nm and made of an insulating film 104 are formed.

  Next, as illustrated in FIG. 7D, a resist 105 that covers the active region 100 b is formed on the semiconductor substrate 100. Next, using the resist 105 as a mask, for example, n-type impurity arsenic is ion-implanted, so that a low-concentration impurity region serving as an extension region or LDD region of the internal transistor is formed laterally below the first gate electrode 123a in the active region 100a. 106a is formed.

  Next, as shown in FIG. 8A, after the resist 105 is removed by ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia hydrogen peroxide cleaning, the active regions 100a and 100b are covered over the entire surface of the semiconductor substrate 100. For example, an insulating film 107 made of a silicon oxide film having a thickness of 5 nm is deposited.

  Next, as illustrated in FIG. 8B, a resist 108 that covers the active region 100 a is formed on the semiconductor substrate 100. Next, using the resist 108 as a mask, for example, phosphorus of an n-type impurity is ion-implanted through the insulating film 107, so that the extension region or the LDD region of the input / output transistor is formed laterally below the second gate electrode 123b in the active region 100b. A low concentration impurity region 106b is formed. At this time, phosphorus is also ion-implanted into a portion of the insulating film 107 covering the active region 100b.

  Next, as shown in FIG. 8C, after removing the resist 108 by performing ashing, sulfuric acid / hydrogen peroxide cleaning, and ammonia hydrogen peroxide cleaning, the active regions 100a and 100b are covered on the insulating film 107, for example, An insulating film 109 having a thickness of 30 nm and made of a silicon nitride film is formed.

  Subsequently, as shown in FIG. 8D, the insulating films 109 and 107 are anisotropically dry-etched to form an insulating film on the side wall of the first gate electrode 123a via the offset spacer 104a in the internal transistor region. A side wall spacer 110a composed of a first inner side wall spacer 107a made of 107 and a first outer side wall spacer 109a made of an insulating film 109 is formed. At the same time, in the input / output transistor region, the second inner side wall spacer 107b made of the insulating film 107 and the second outer side side made of the insulating film 109 are arranged on the side wall of the second gate electrode 123b via the offset spacer 104b. Sidewall spacers 110b composed of wall spacers 109b are formed. The second inner side wall spacer 107b contains phosphorus, which is an impurity of the low concentration impurity region 106b. However, the first inner side wall spacer 107a contains arsenic, which is an impurity of the low concentration impurity region 106a. Not included.

  Next, as shown in FIG. 9A, for example, the active regions 100a and 100b are formed in the active regions 100a and 100b using the first gate electrode 123a, the second gate electrode 123b, the offset spacers 104a and 104b, and the sidewall spacers 110a and 110b as masks. By ion-implanting n-type impurity arsenic, a high-concentration impurity region 111a serving as the source / drain region of the internal transistor and a high-concentration impurity region 111b serving as the source / drain region of the input / output transistor region are formed.

  Next, as shown in FIG. 9B, silicide films 112a and 112b are formed on the first gate electrode 123a and the high concentration impurity region 111a, and on the second gate electrode 123b and the high concentration impurity region 111b, respectively. Respectively. Next, after forming an interlayer insulating film 113 on the entire surface of the semiconductor substrate 100, contact plugs 114a and 114b penetrating the interlayer insulating film 113 are formed on the silicide films 112a and 112b, respectively. Subsequently, metal wirings 115a and 115b connected to the contact plugs 114a and 114b, respectively, are formed. The semiconductor device of this embodiment can be manufactured through the above steps.

  If the method for manufacturing a semiconductor device according to the present embodiment is used, the semiconductor substrate 100 in the internal transistor region is prevented from being scraped before the formation of the low-concentration impurity region 106a as in the first embodiment, and the low-concentration concentration is reduced. When the impurity region 106b is formed, the surface of the formed low concentration impurity region 106a can be prevented from being scraped. As a result, an internal transistor having a low-concentration impurity region 106a having a shallow junction and a low parasitic resistance can be formed, and a semiconductor device having high driving ability even when miniaturized can be realized.

  In the semiconductor device manufacturing method of this embodiment, high dielectric constant films are used as the first gate insulating film 120a and the second gate insulating film 120b, and the first gate electrode 123a and the second gate electrode 123b are used. A laminated film of a metal film and a silicon film is used. Accordingly, since the leakage current and the depletion of the gate electrode can be suppressed even if the semiconductor device is miniaturized, a highly reliable semiconductor device in which a decrease in driving capability is suppressed can be manufactured. In the present embodiment, the gate electrode made of a laminated film is used in both the internal transistor and the input / output transistor, but the present invention is not limited to this. For example, the above-described effects can be obtained even when the second gate electrode 123b of the input / output transistor is formed of only a polycrystalline silicon film and has a structure different from that of the first gate electrode 123a.

  The configuration of the semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment only in the gate structure, and thus detailed description thereof is omitted. In the semiconductor device and the manufacturing method thereof according to the present embodiment, as in the second embodiment, the second inner sidewall spacer 107a and the first outer sidewall spacer 109a, as well as the second A first intermediate sidewall spacer and a second intermediate sidewall spacer each having an L-shaped cross section may be formed between the inner sidewall spacer 107b and the second outer sidewall spacer 109b.

  The semiconductor device and the manufacturing method thereof of the present invention are useful for miniaturization and high drive of the semiconductor device.

(A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. (A), (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. (A) is sectional drawing which shows the structure of the low concentration impurity area | region of this invention, FIG.4 (b) is sectional drawing which shows the structure of the conventional low concentration impurity area | region. (A), (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. (A), (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. (A)-(d) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. (A), (b) is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. (A)-(d) is sectional drawing which shows the manufacturing method of the conventional semiconductor device. (A)-(c) is sectional drawing which shows the manufacturing method of the conventional semiconductor device. (A), (b) is sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

100 Semiconductor substrate 100a, 100b Active region 101 Element isolation region 102a First gate insulating film 102b Second gate insulating film 103a First gate electrode 103b Second gate electrode 104 Insulating film 104a, 104b Offset spacer 105 Resist 106a, 106b Low concentration impurity region 107 Insulating film 107a First inner side wall spacer 107b Second inner side wall spacer 108 Resist 109 Insulating film 109a First outer side wall spacer 109b Second outer side wall spacer 110a, 110b Side wall Spacers 111a and 111b High-concentration impurity regions 112a and 112b Silicide films 113 Interlayer insulating films 114a and 114b Contact plugs 115a and 115b Metal wiring 16 Insulating film 116a First intermediate sidewall spacer 116b Second intermediate sidewall spacer 120a First gate insulating film 120b Second gate insulating film 121a, 121b Metal film 122a, 122b Silicon film 123a First gate electrode 123b Second gate electrode

Claims (14)

In a semiconductor device including a first MIS transistor and a second MIS transistor,
The first MIS transistor is
A first gate insulating film formed on the first active region in the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A first impurity region formed in a side lower side of the first gate electrode in the first active region and formed by diffusing a first impurity;
A first inner sidewall spacer formed on a side surface of the first gate electrode and having an L-shaped cross section;
A first outer sidewall spacer formed on an L-shaped inner surface of the first inner sidewall spacer;
The second MIS transistor is
A second gate insulating film formed on a second active region in the semiconductor substrate;
A second gate electrode formed on the second gate insulating film;
A second impurity region formed under the second gate electrode in the second active region and formed by diffusing a second impurity of the same conductivity type as the first impurity;
A second inner side wall spacer formed on a side surface of the second gate electrode and having an L-shaped cross section;
A second outer sidewall spacer formed on an L-shaped inner surface of the second inner sidewall spacer;
The second inner side wall spacer contains the second impurity in an interface region with the second outer side wall spacer. The semiconductor device according to claim 1,
The semiconductor device, wherein the second inner side wall spacer contains the second impurity in an interface region with the second outer side wall spacer in an L-shaped corner portion. The semiconductor device according to claim 1 or 2,
The first inner sidewall spacer does not contain the first impurity in an interface region with the first outer sidewall spacer in an L-shaped corner portion. The semiconductor device according to any one of claims 1 to 3,
A first offset spacer formed between the first gate electrode and the first inner sidewall spacer;
A semiconductor device further comprising a second offset spacer formed between the second gate electrode and the second inner sidewall spacer. The semiconductor device of any one of Claims 1-4 WHEREIN:
The first inner side wall spacer and the second inner side wall spacer are made of a silicon oxide film,
The semiconductor device according to claim 1, wherein the first outer side wall spacer and the second outer side wall spacer are made of a silicon nitride film. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the first impurity is different from the second impurity. The semiconductor device according to any one of claims 1 to 6,
The semiconductor device is characterized in that the film thickness of the first gate insulating film is smaller than the film thickness of the second gate insulating film. The semiconductor device according to any one of claims 1 to 7,
The first MIS transistor is an internal transistor;
The semiconductor device, wherein the second MIS transistor is an input / output transistor. The semiconductor device according to any one of claims 1 to 8,
A first intermediate sidewall spacer formed between the first inner sidewall spacer and the first outer sidewall spacer and having an L-shaped cross section;
A second intermediate sidewall spacer formed between the second inner sidewall spacer and the second outer sidewall spacer and having an L-shaped cross section; and the second inner sidewall spacer. The spacer includes the second impurity in an interface region with the second intermediate sidewall spacer. The semiconductor device according to any one of claims 1 to 9,
The first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film,
The second gate electrode has a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film. A semiconductor device characterized by the above. In a method of manufacturing a semiconductor device comprising: a first MIS transistor formed in a first active region in a semiconductor substrate; and a second MIS transistor formed in a second active region in the semiconductor substrate.
Forming a first gate insulating film on the first active region and forming a second gate insulating film on the second active region;
Forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film;
A step (c) of forming a first impurity region by ion-implanting a first impurity under the side of the first gate electrode in the first active region;
A step (d) of forming a first insulating film covering the first active region and the second active region on the semiconductor substrate after the step (c);
A second impurity having the same conductivity type as that of the first impurity is ion-implanted through the first insulating film below the side of the second gate electrode in the second active region. Forming a region (e);
A step (f) of forming a second insulating film on the first insulating film after the step (e);
By performing anisotropic dry etching on the first insulating film and the second insulating film, a cross-sectional shape made of the first insulating film is formed on the side surface of the first gate electrode. A first outer side wall spacer made of the first inner side wall spacer and the second insulating film, and a cross-sectional shape made of the first insulating film on the side surface of the second gate electrode is L A step (g) of forming a second inner sidewall spacer having a letter shape and a second outer sidewall spacer made of the second insulating film. In the manufacturing method of the semiconductor device according to claim 11,
After the step (b) and before the step (c), a first offset spacer is formed on the side surface of the first gate electrode and a second side is formed on the side surface of the second gate electrode. A method of manufacturing a semiconductor device, further comprising a step (h) of forming an offset spacer. In the manufacturing method of the semiconductor device according to claim 11 or 12,
A step (i) of forming a third insulating film on the first insulating film after the step (e) and before the step (f);
In the step (f), the second insulating film is formed on the third insulating film,
In the step (g), the first insulating film, the third insulating film, and the second insulating film are anisotropically dry-etched to thereby form the first inner sidewall spacer and the first insulating film. A first intermediate sidewall spacer having an L-shaped cross-section made of the third insulating film is formed between the outer sidewall spacer and the second inner sidewall spacer and the second outer sidewall spacer. A method of manufacturing a semiconductor device, comprising: forming a second intermediate sidewall spacer having an L-shaped cross section made of the third insulating film between the sidewall spacers. In the manufacturing method of the semiconductor device of any one of Claims 11-13,
The first gate electrode includes a first metal film formed on the first gate insulating film and a first silicon film formed on the first metal film,
The second gate electrode has a second metal film formed on the second gate insulating film and a second silicon film formed on the second metal film. A method of manufacturing a semiconductor device.

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