JP2009272641A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for achieving a fine-pitch pattern and improving stability in patterning precision. <P>SOLUTION: The method of manufacturing a semiconductor device includes: a first process for forming a first photoresist pattern in a partial region on a substrate; a second process for depositing a thin film on the surface of at least the first photoresist pattern by supplying not less than two kinds of source gas alternately; and a third process for forming a second photoresist pattern at one portion of a region in which the first photoresist pattern is not formed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, a semiconductor device, and a semiconductor manufacturing apparatus, and, for example, to a pattern formation method for a semiconductor device (semiconductor device) using a double patterning method.

  In recent years, memory devices such as flash memory, dynamic random access memory (DRAM), static random access memory (SRAM), and semiconductor devices such as logic devices have been required to be highly integrated. Is essential. In order to integrate a large number of devices in a small area, the size of each individual device must be made small. To this end, the pitch, which is the sum of the width and spacing of the pattern to be formed, is reduced. There must be. However, there is a resolution limit in a photolithography process for forming a necessary pattern, and there is a limit in forming a pattern having a fine pitch.

In recent years, a technique (pattern formation technique) for forming a fine pattern on a substrate and processing the lower layer of the pattern by using this as a mask (pattern formation technique) has been widely adopted for IC creation in the semiconductor industry, and has received great attention. Have been bathed. Thus, as one of the newly proposed lithography techniques, a double patterning method is being studied in which patterning is performed twice or more to form a photoresist pattern. According to this double patterning method, it is said that a pattern finer than a pattern formed by one patterning can be formed, and as one of them, a technique for performing exposure twice or more is being studied. .

JP2002-151381

In the double patterning method, in order to form the second photoresist pattern after forming the first photoresist pattern, a process is performed so as not to cause any damage to the first photoresist pattern when the second photoresist pattern is formed. It is necessary to build.
Specifically, (1) deterioration of resist characteristics due to penetration of the solvent contained in the photoresist into the first photoresist pattern at the time of forming the second photoresist pattern, and (2) first due to heat treatment applied during the second photoresist processing. Deformation of the photoresist pattern (deterioration occurs when heated at 150 ° C. with a general resin-based photoresist material), (3) Generation of resist dimension deviation of the first photoresist pattern in the development process during the formation of the second photoresist pattern (substantially Development time is increased by the amount of time required for the second photoresist processing, resulting in a deviation from a desired resist dimension), and (4) overcoming problems such as occurrence of damage to the first photoresist when rework occurs in the second photoresist processing. Process technology needs to be developed.

The main object of the present invention is to provide the stability of patterning accuracy in the double patterning technology, in which the second photoresist formation process does not have the side effects as described in (1) to (4) above on the first photoresist. An object of the present invention is to provide a method for manufacturing a semiconductor device.

  According to one aspect of the present invention, at least a first step of forming a first photoresist pattern in a partial region on a substrate and two or more source gases are alternately supplied to the substrate. And a second step of depositing a thin film on the surface of the photoresist pattern, and a third step of forming the second photoresist pattern in a part of the region where the first photoresist pattern is not formed. A first method for manufacturing a semiconductor device is provided.

  According to another aspect of the present invention, a first step of forming a first photoresist pattern in a partial region on a substrate, a first source gas containing a first substance, and a second substance are included. A second source gas is alternately supplied to the substrate to deposit a thin film on at least the surface of the first photoresist pattern, and a second region is formed in a part of the region where the first photoresist pattern is not formed. And a third step of forming a photoresist pattern, wherein the catalyst is supplied to the substrate together with at least one of the first source gas and the second source gas in the second step. A method for manufacturing a second semiconductor device is provided.

  According to another aspect of the present invention, at least a first step of forming a first photoresist pattern in a partial region on a substrate and two or more source gases are alternately supplied to the substrate. A second step of depositing a thin film on the surface of the photoresist pattern, and a third step of forming the second photoresist pattern in a part of the region where the first photoresist pattern is not formed. A photoresist pattern forming method is provided.

According to the first semiconductor device manufacturing method, the second semiconductor device manufacturing method, and the photoresist pattern forming method according to one aspect of the present invention, a thin film (for example, a SiO ₂ film) is formed on the first photoresist pattern. By doing so, the first photoresist pattern can be protected, and when the second photoresist solvent is applied, the second photoresist solvent can be prevented from penetrating into the first photoresist pattern.

  In addition, according to the first semiconductor device manufacturing method, the second semiconductor device manufacturing method, and the photoresist pattern forming method according to one aspect of the present invention, by forming a thin film on the first photoresist pattern, During the formation of the two photoresist pattern, the mechanical strength of the first photoresist pattern can be improved.

According to the first semiconductor device manufacturing method, the second semiconductor device manufacturing method, and the photoresist pattern forming method according to one aspect of the present invention, a thin film (for example, SiO ₂ film) is formed on the first photoresist pattern. By forming the film, the first photoresist pattern can be protected at the time of reworking the second photoresist pattern.

1 is a perspective view showing a schematic configuration of a substrate processing apparatus according to a preferred embodiment of the present invention. It is a schematic block diagram of the vertical processing furnace used in the preferable Example of this invention, and the member accompanying it, and has shown the processing furnace part with the longitudinal cross-section especially. It is the sectional view on the AA line of FIG. In a preferred embodiment of the present invention, it is a schematic diagram showing how a photoresist pattern is formed on a wafer used as a substrate. FIG. 4 is a diagram showing a schematic main gas supply sequence when forming a SiO ₂ film by an ALD method in a preferred embodiment of the present invention. In a preferred embodiment of the present invention, it is a view at the time of forming the SiO ₂ film by an ALD method. FIG. 6 is a diagram showing wet etching characteristics of a SiO ₂ film in a preferred embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
The substrate processing apparatus according to this embodiment is a semiconductor device (IC (Integrated
Circuits)) is configured as an example of a semiconductor manufacturing apparatus used for manufacturing.
In the following description, as an example of the substrate processing apparatus, a case will be described in which a vertical apparatus that performs a film forming process or the like on a substrate is used. However, the present invention is not based on the use of a vertical apparatus, and for example, a single wafer apparatus may be used. Also, the mechanism of film formation is not limited to the SiO ₂ film that combines Si raw material, oxidation raw material, and catalyst. For example, a technique capable of low-temperature film formation, such as a film forming technique using light energy, should be applied. Can do.

  As shown in FIG. 1, in the substrate processing apparatus 101, a cassette 110 containing a wafer 200 as an example of a substrate is used, and the wafer 200 is made of a material such as silicon. The substrate processing apparatus 101 includes a housing 111, and a cassette stage 114 is installed inside the housing 111. The cassette 110 is carried on the cassette stage 114 by an in-process transfer device (not shown) or unloaded from the cassette stage 114.

  The cassette stage 114 is placed by the in-process transfer device so that the wafer 200 in the cassette 110 maintains a vertical posture and the wafer loading / unloading port of the cassette 110 faces upward. The cassette stage 114 rotates the cassette 110 clockwise 90 degrees rearward of the casing 111 so that the wafer 200 in the cassette 110 is in a horizontal posture, and the wafer loading / unloading port of the cassette 110 faces the rear of the casing 111. It is configured to be operable.

  A cassette shelf 105 is installed in a substantially central portion of the casing 111 in the front-rear direction, and the cassette shelf 105 is configured to store a plurality of cassettes 110 in a plurality of rows and a plurality of rows. The cassette shelf 105 is provided with a transfer shelf 123 in which the cassette 110 to be transferred by the wafer transfer mechanism 125 is stored.

  A reserve cassette shelf 107 is provided above the cassette stage 114, and is configured to store the cassette 110 in a preliminary manner.

  A cassette carrying device 118 is installed between the cassette stage 114 and the cassette shelf 105. The cassette carrying device 118 includes a cassette elevator 118a that can move up and down while holding the cassette 110, and a cassette carrying mechanism 118b as a carrying mechanism. The cassette carrying device 118 is configured to carry the cassette 110 among the cassette stage 114, the cassette shelf 105, and the spare cassette shelf 107 by continuous operation of the cassette elevator 118a and the cassette carrying mechanism 118b.

  A wafer transfer mechanism 125 is installed behind the cassette shelf 105. The wafer transfer mechanism 125 includes a wafer transfer device 125a that can rotate or linearly move the wafer 200 in the horizontal direction, and a wafer transfer device elevator 125b that moves the wafer transfer device 125a up and down. The wafer transfer device 125 a is provided with a tweezer 125 c for picking up the wafer 200. The wafer transfer device 125 loads (charges) the wafer 200 to the boat 217 by using the tweezers 125c as a placement portion of the wafer 200 by continuous operation of the wafer transfer device 125a and the wafer transfer device elevator 125b. The boat 217 is configured to be detached (discharged).

  A processing furnace 202 for heat-treating the wafer 200 is provided above the rear portion of the casing 111, and a lower end portion of the processing furnace 202 is configured to be opened and closed by a furnace port shutter 147.

  Below the processing furnace 202, a boat elevator 115 that raises and lowers the boat 217 with respect to the processing furnace 202 is provided. An arm 128 is connected to the lifting platform of the boat elevator 115, and a seal cap 219 is horizontally installed on the arm 128. The seal cap 219 is configured to support the boat 217 vertically and to close the lower end portion of the processing furnace 202.

  The boat 217 includes a plurality of holding members, and is configured to hold a plurality of (for example, about 50 to 150) wafers 200 horizontally with the centers thereof aligned in the vertical direction. Yes.

  Above the cassette shelf 105, a clean unit 134a for supplying clean air that is a cleaned atmosphere is installed. The clean unit 134a includes a supply fan and a dustproof filter, and is configured to distribute clean air inside the casing 111.

  A clean unit 134 b that supplies clean air is installed at the left end of the housing 111. The clean unit 134b also includes a supply fan and a dustproof filter, and is configured to distribute clean air in the vicinity of the wafer transfer device 125a, the boat 217, and the like. The clean air is exhausted to the outside of the casing 111 after circulating in the vicinity of the wafer transfer device 125a, the boat 217, and the like.

  Next, main operations of the substrate processing apparatus 101 will be described.

  When the cassette 110 is loaded onto the cassette stage 114 by an in-process transfer device (not shown), the cassette 110 holds the wafer 200 in a vertical position on the cassette stage 114 and the wafer loading / unloading port of the cassette 110 is directed upward. It is placed so that it faces. Thereafter, the cassette 110 is placed in a clockwise direction 90 in the clockwise direction behind the housing 111 so that the wafer 200 in the cassette 110 is placed in a horizontal posture by the cassette stage 114 and the wafer loading / unloading port of the cassette 110 faces the rear of the housing 111. ° Rotated.

  Thereafter, the cassette 110 is automatically transported and delivered by the cassette transport device 118 to the designated shelf position of the cassette shelf 105 or the spare cassette shelf 107 and temporarily stored, and then the cassette shelf 105 or the spare cassette shelf. It is transferred from 107 to the transfer shelf 123 by the cassette transfer device 118 or directly transferred to the transfer shelf 123.

  When the cassette 110 is transferred to the transfer shelf 123, the wafer 200 is picked up from the cassette 110 by the tweezer 125c of the wafer transfer device 125a through the wafer loading / unloading port and loaded (charged) into the boat 217. The wafer transfer device 125 a that has delivered the wafer 200 to the boat 217 returns to the cassette 110 and loads the subsequent wafer 110 into the boat 217.

  When a predetermined number of wafers 200 are loaded into the boat 217, the furnace port shutter 147 that has closed the lower end of the processing furnace 202 is opened, and the lower end of the processing furnace 202 is opened. Thereafter, the boat 217 holding the wafer group 200 is loaded into the processing furnace 202 by the ascending operation of the boat elevator 115, and the lower part of the processing furnace 202 is closed by the seal cap 219.

  After loading, arbitrary processing is performed on the wafer 200 in the processing furnace 202. After the processing, the wafer 200 and the cassette 110 are carried out of the casing 111 in the reverse procedure described above.

  As shown in FIGS. 2 and 3, the processing furnace 202 is provided with a heater 207 for heating the wafer 200. The heater 207 includes a cylindrical heat insulating member whose upper portion is closed and a plurality of heater wires, and has a unit configuration in which the heater wires are provided on the heat insulating member. A quartz reaction tube 203 for processing the wafer 200 is provided inside the heater 207.

  A manifold 209 made of stainless steel or the like is provided at the lower end of the reaction tube 203 via an O-ring 220 that is an airtight member. The lower end opening of the manifold 209 is airtightly closed by a seal cap 219 as a lid through an O-ring 220. In the processing furnace 202, a processing chamber 201 is formed by at least the reaction tube 203, the manifold 209, and the seal cap 219.

  The seal cap 219 is provided with a boat support 218 that supports the boat 217. As shown in FIG. 1, the boat 217 includes a bottom plate 210 fixed to the boat support base 218 and a top plate 211 disposed above the bottom plate 210, and a plurality of support columns are disposed between the bottom plate 210 and the top plate 211. 212 has a construction in which it is constructed. A plurality of wafers 200 are held on the boat 217. The plurality of wafers 200 are supported by the support columns 212 of the boat 217 in a state in which the wafers 200 are held in a horizontal posture with a certain interval therebetween.

  In the processing furnace 202 described above, in a state where a plurality of batch-processed wafers 200 are stacked on the boat 217, the boat 217 is inserted into the processing chamber 201 while being supported by the boat support 218, and the heater 207 is The wafer 200 inserted into the processing chamber 201 is heated to a predetermined temperature.

  As shown in FIGS. 2 and 3, two source gas supply pipes 310 and 320 for supplying a source gas and a catalyst supply pipe 330 for supplying a catalyst are connected to the processing chamber 201. .

  The source gas supply pipe 310 is provided with a mass flow controller 312 and a valve 314. A nozzle 410 is connected to the tip of the source gas supply pipe 310. The nozzle 410 is an arc-shaped space between the inner wall of the reaction tube 203 constituting the processing chamber 201 and the wafer 200, and extends in the vertical direction along the inner wall of the reaction tube 203. A large number of gas supply holes 410 a for supplying a source gas are provided on the side surface of the nozzle 410. The gas supply holes 410a have the same or inclined opening area from the lower part to the upper part, and are provided at the same opening pitch.

  Further, a carrier gas supply pipe 510 for supplying a carrier gas is connected to the source gas supply pipe 310. The carrier gas supply pipe 510 is provided with a mass flow controller 512 and a valve 514.

The source gas supply pipe 320 is provided with a mass flow controller 322 and a valve 324. A nozzle 420 is connected to the tip of the source gas supply pipe 320. Similarly to the nozzle 410, the nozzle 420 is an arc-shaped space between the inner wall of the reaction tube 203 constituting the processing chamber 201 and the wafer 200, and extends in the vertical direction along the inner wall of the reaction tube 203. ing. A large number of gas supply holes 420 a for supplying a source gas are provided on the side surface of the nozzle 420. Similarly to the gas supply holes 410a, the gas supply holes 420a have the same or inclined opening areas from the lower part to the upper part, and are provided at the same opening pitch.

  Further, a carrier gas supply pipe 520 for supplying a carrier gas is connected to the source gas supply pipe 320. The carrier gas supply pipe 520 is provided with a mass flow controller 522 and a valve 524.

  The catalyst supply pipe 330 is provided with a mass flow controller 332 and a valve 334. A nozzle 430 is connected to the tip of the catalyst supply pipe 330. Similarly to the nozzle 410, the nozzle 430 is an arc-shaped space between the inner wall of the reaction tube 203 constituting the processing chamber 201 and the wafer 200, and extends in the vertical direction along the inner wall of the reaction tube 203. ing. A large number of catalyst supply holes 430 a for supplying a catalyst are provided on the side surface of the nozzle 430. Similarly to the gas supply holes 410a, the catalyst supply holes 430a have the same or inclined opening areas from the lower part to the upper part, and are further provided at the same opening pitch.

  Further, a carrier gas supply pipe 530 for supplying a carrier gas is connected to the catalyst supply pipe 330. The carrier gas supply pipe 530 is provided with a mass flow controller 532 and a valve 534.

As an example of the above configuration, the raw material gas supply pipe 310 has an Si raw material (TDMAS: trisdimethylaminosilane (TDMAS, SiH (N (CH ₃ ) ₂ ) ₃ ), DCS: dichlorosilane (SiH ₂ Cl) as an example of the raw material gas. ₂ ), HCD: hexachlorodisilane (Si ₂ Cl ₆ ), trichlorosilane (SiCl ₄ ), etc.) are introduced. H ₂ O, H ₂ O ₂ or the like is introduced into the source gas supply pipe 320 as an example of an oxidizing source. As an example of the catalyst, pyridine (C ₅ H ₅ N), pyrimidine, quinoline, or the like is introduced into the catalyst supply pipe 330.

  An exhaust pipe 231 for exhausting the inside of the processing chamber 201 is connected to the processing chamber 201 via a valve 243e. A vacuum pump 246 is connected to the exhaust pipe 231, and the inside of the processing chamber 201 can be evacuated by the operation of the vacuum pump 246. The valve 243e can start and stop the vacuum evacuation of the processing chamber 201 by opening and closing operations, and can also adjust the valve opening degree and adjust the pressure inside the processing chamber 201. This is an open / close valve.

  A boat 217 is provided at the center in the reaction tube 203. The boat 217 can be moved up and down (in and out) with respect to the reaction tube 203 by the boat elevator 115. A boat rotation mechanism 267 that rotates the boat 217 is provided at the lower end of the boat support 218 that supports the boat 217 in order to improve processing uniformity. By driving the boat rotation mechanism 267, the boat 217 supported by the boat support 218 can be rotated.

Each of the mass flow controllers 312, 322, 332, 512, 522, 532, valves 314, 324, 334, 514, 524, 534, valve 243e, heater 207, vacuum pump 246, boat rotating mechanism 267, boat elevator 115, etc. The member is connected to the controller 280. The controller 280 is an example of a control unit that controls the overall operation of the substrate processing apparatus 101. , 534 opening / closing operation, valve 243e opening / closing and pressure adjustment operation, heater 207 temperature adjustment, vacuum pump 246 activation / deactivation, boat rotation mechanism 267 rotation speed adjustment, boat elevator 115 elevation operation, etc. It has become.

  Next, as an example of a method for manufacturing a semiconductor device (semiconductor device), an example in which the present invention is applied when manufacturing a large scale integration (LSI) will be described.

  An LSI is manufactured through an assembly process, a test process, and a reliability test process after performing a wafer process for processing on a silicon wafer. The wafer process is divided into a substrate process in which processing such as oxidation and diffusion is performed on a silicon wafer and a wiring process in which wiring is formed on the surface, and cleaning, heat treatment, film formation, etc. are repeatedly performed mainly in the lithography process. It is. In the lithography process, a photoresist pattern is formed, and the lower layer of the pattern is processed by etching using the pattern as a mask.

  Here, an example of a process sequence for forming a photoresist pattern on the wafer 200 will be described with reference to FIG.

  In the process sequence, a first photoresist pattern forming step of forming a first photoresist pattern 603a on the wafer 200, a first photoresist protective film forming step of forming a thin film as a first photoresist protective film on the first photoresist pattern 603a, A second photoresist pattern process for forming a second photoresist pattern 603b on the thin film is performed in this order. Hereinafter, each step will be described.

<First photoresist pattern forming step>
In the first photoresist pattern forming step, a first photoresist pattern 603 a is formed on the hard mask 601 formed on the wafer 200.
First, a first photoresist solvent 602a is applied on the hard mask 601 formed on the wafer 200 (FIG. 4a). Next, the first photoresist pattern 603a is formed by baking, selective exposure using a mask pattern or the like by a light source such as an ArF excimer light source (193 nm) or a KrF excimer light source (248 nm), development, and the like (FIG. 4b). ).

<First photoresist protective film formation process>
In the first photoresist protective film forming step, a thin film is formed as a protective material on the first photoresist pattern 603a formed in the first photoresist pattern forming step and in a portion where the first photoresist pattern 603a is not formed. Thereby, the shape change and film quality change of the first photoresist pattern 603a are prevented to protect from the second photoresist solvent 602b described later. Hereinafter, an example in which the SiO ₂ film 604 as a protective film is formed at an extremely low temperature by the ALD method using the substrate processing apparatus 101 will be described.

ALD (Atomic Layer Deposition) method is CVD (Chemical)
Vapor Deposition) is a method in which at least two types of source gases used for film formation are alternately supplied onto a substrate one by one under a certain film formation condition (temperature, time, etc.). This is a technique in which a film is formed by adsorbing on a substrate in atomic units and utilizing a surface reaction. At this time, the film thickness is controlled by the number of cycles in which the source gas is supplied (for example, if the film forming speed is 1 kg / cycle, 20 cycles are performed when a 20 mm film is formed).

In this embodiment, the case where HCD is used as the Si source gas, H ₂ O is used as the oxidation source, pyridine is used as the catalyst, and N ₂ is used as the carrier gas will be described with reference to FIGS. 1, 2 and 5. To do.

  In the film forming process, the controller 280 controls the substrate processing apparatus 101 as follows. That is, the heater 207 is controlled to keep the inside of the processing chamber 201 at a temperature lower than the alteration temperature of the photoresist film, for example, 150 ° C. or lower, preferably 100 ° C. or lower, more preferably 75 ° C. Thereafter, a plurality of wafers 200 are loaded into the boat 217, and the boat 217 is loaded into the processing chamber 201. Thereafter, the boat 217 is rotated by the boat driving mechanism 267 to rotate the wafer 200. Thereafter, the vacuum pump 246 is operated and the valve 243e is opened to evacuate the inside of the processing chamber 201. When the temperature of the wafer 200 reaches 75 ° C. and the temperature is stabilized, the temperature in the processing chamber 201 is maintained at 75 ° C. In this state, the following four steps are sequentially executed.

(Step 1)
With HCD introduced into the source gas supply pipe 310, H ₂ O into the source gas supply pipe 320, a catalyst into the catalyst supply pipe 330, and N ₂ into the carrier gas supply pipes 510, 520 and 530 (inflow), Valves 314, 334, 514, 524, and 534 are appropriately opened. However, the valve 324 remains closed.

As a result, as shown in FIG. 5, HCD flows through the source gas supply pipe 310 while being mixed with N ₂ , flows out to the nozzle 410, and is supplied to the processing chamber 201 through the gas supply hole 410a. Further, the catalyst also flows through the catalyst supply pipe 330 while being mixed with N ₂ , flows out to the nozzle 430, and is supplied to the processing chamber 201 from the catalyst supply hole 430 a. Further, N ₂ flows through the carrier gas supply pipe 520 and flows out to the nozzle 420, and is supplied to the processing chamber 201 through the gas supply hole 420a. The HCD and the catalyst supplied to the processing chamber 201 pass through the surface of the wafer 200 and are exhausted from the exhaust pipe 231.

  In step 1, the valves 314 and 334 are controlled to set the time for supplying HCD and catalyst to an optimum time (for example, 10 seconds). Further, the valves 314 and 334 are controlled so that the ratio of the supply amount of HCD and the catalyst becomes a constant ratio (for example, 1: 1). At the same time, the valve 243e is appropriately adjusted to set the pressure in the processing chamber 201 to an optimum value within a certain range (for example, 3 Torr). In step 1 described above, HCD and catalyst are supplied into the processing chamber 201, so that Si is adsorbed onto the first photoresist pattern 603 a and the hard mask 601 formed on the wafer 200.

(Step 2)
The valves 314 and 334 are closed to stop the supply of HCD and catalyst, and N ₂ is continuously supplied to the processing chamber 201 from the carrier gas supply pipes 510, 520, and 530 as shown in FIG. Purge with ₂ . The purge time is 15 seconds, for example. There may be two steps of purging and evacuation within 15 seconds. As a result, HCD and catalyst remaining in the processing chamber 201 are removed from the processing chamber 201.

(Step 3)
While the valves 514, 524, and 534 are kept open, the valves 324 and 334 are appropriately opened. Valve 314 remains closed. As a result, as shown in FIG. 5, H ₂ O flows through the source gas supply pipe 320 while being mixed with N ₂ , flows out to the nozzle 420, and is supplied to the processing chamber 201 from the gas supply hole 420a. Further, the catalyst also flows through the catalyst supply pipe 330 while being mixed with N ₂ , flows out to the nozzle 430, and is supplied to the processing chamber 201 from the catalyst supply hole 430 a. Further, N ₂ flows through the carrier gas supply pipe 510 and flows out to the nozzle 410, and is supplied to the processing chamber 201 from the gas supply hole 410a. The H ₂ O and catalyst supplied to the processing chamber 201 pass through the surface of the wafer 200 and are exhausted from the exhaust pipe 231.

In Step 3, the valves 324 and 334 are controlled to set the time for supplying H ₂ O and the catalyst to an optimum time (for example, 20 seconds). Further, the valves 314 and 334 are controlled so that the ratio of the supply amount of H ₂ O and the catalyst becomes a constant ratio (eg, 1: 1). At the same time, the valve 243e is appropriately adjusted so that the pressure in the processing chamber 201 becomes an optimum value within a certain range (for example, 7 Torr). In the above step 3, by supplying H ₂ O and a catalyst into the processing chamber 201, a SiO ₂ film is formed on the first photoresist pattern 603a and the hard mask 601 formed on the wafer 200. The supply concentration of H ₂ O and the catalyst is more preferably the same concentration.

In addition, the characteristic required as an oxidation raw material supplied in step 3 (a raw material corresponding to H ₂ O) is that the molecule contains atoms having a high electronegativity and is electrically biased. . The reason is that since the catalyst has a high electronegativity, the activation energy of the raw material gas is lowered to promote the reaction. Therefore, as the source gas supplied in Step 3, H ₂ O, H ₂ O ₂ or the like having an OH bond is appropriate, and nonpolar molecules such as O ₂ or O ₃ are inappropriate.

(Step 4)
The valves 324 and 334 are closed to stop the supply of H ₂ O and the catalyst, and N ₂ is continuously supplied from the carrier gas supply pipes 510, 520, and 530 to the processing chamber 201 as shown in FIG. Is purged with N ₂ . The purge time is 15 seconds, for example. There may be two steps of purging and evacuation within 15 seconds. As a result, H ₂ O and catalyst remaining in the processing chamber 201 are removed from the processing chamber 201.

Thereafter, steps 1 to 4 are set as one cycle, and this cycle is repeated a plurality of times to form a SiO ₂ film having a predetermined thickness on the first photoresist pattern 603 a and the hard mask 601 formed on the wafer 200. In this case, in each cycle, the atmosphere composed of the Si raw material and the catalyst in Step 1 and the atmosphere composed of the oxidizing raw material and the catalyst in Step 3 are mixed in the processing chamber 201 as described above. Note that the film is formed so that it does not. As a result, a SiO ₂ film 604 as a first photoresist protective film is formed on the first photoresist pattern 603a and the hard mask 601 (FIGS. 4c and 7).

Thereafter, the inside of the processing chamber 201 is evacuated to exhaust HCD, H ₂ O, and catalyst remaining in the processing chamber 201, the valve 243 e is controlled to set the processing chamber 201 to atmospheric pressure, and the boat 217 is moved to the processing chamber 201. Unload from. This completes one film formation process (batch process).

As the film thickness of the SiO ₂ film 604, about 5% of the half pitch (Hp) which is the limit resolution of lithography is necessary as the first photoresist protective film. Therefore, for example, a film thickness of 5 to 25 mm is sufficient for Hp 30 nm, and preferably 15 mm.

<Second photoresist pattern forming step>
In the second photoresist pattern forming step, on the SiO ₂ film 604 formed on the first photoresist in the first photoresist protective film forming step, at a position different from the position where the first photoresist pattern 603a is formed, A second photoresist pattern 603b is formed.
In this step, the same processing as in the first photoresist pattern forming step is performed.
First, a second photoresist solvent 602b is applied on the SiO ₂ film 604, which is a protective film for the first photoresist (FIG. 4d). Next, baking, exposure with an ArF excimer light source (193 nm), a KrF excimer light source (248 nm), development, and the like are performed to form a second photoresist pattern 603b (FIG. 4e).

As described above, a fine photoresist pattern can be formed by performing the first photoresist pattern forming step, the first photoresist protective film forming step, and the second photoresist pattern forming step. FIG. 6 shows a diagram when an SiO ₂ film is formed by the ALD method.

  In the above description, the first photoresist pattern 603a is formed on the hard mask 601 formed on the wafer 200. However, the hard mask 601 may be omitted.

In addition, after the second photoresist pattern is formed and after performing predetermined processing (for example, dimension inspection, alignment inspection, rework processing, etc.), in order to remove the SiO ₂ film 604 as necessary, the following is performed. A (first photoresist protective film) removing step may be performed.

<First photoresist protective film removal step>
In the first photoresist protective film removing step, the SiO ₂ film 604 as the first photoresist protective film formed in the first photoresist protective film forming step is removed.

There are two removal methods, a wet etching method and a dry etching method. As an etching solution for removing the SiO ₂ film 604 by wet etching, for example, a hydrofluoric acid (HF) solution, such as a dilute HF solution, can be used. Incidentally, the SiO ₂ film formed by the ALD method has a fast wet etching rate. FIG. 7 shows a comparison of etching rates of SiO ₂ films formed by different methods as their characteristics. As shown in FIG. 7, when the wet etching rate of the thermal oxide film is used as a reference, the SiO ₂ film formed by the CVD method is 5 times, and the SiO ₂ film formed by the ALD method is 15 times, which is formed by the ALD method. It can be seen that the wet etching rate of the SiO ₂ film is fast.
Further, when the SiO ₂ film 604 is removed by a dry etching method, for example, oxygen plasma or the like can be used.

  In the above description, the process of forming the photoresist pattern twice has been described. However, the photoresist pattern may be formed three or more times. In this case, the photoresist pattern forming process and the photoresist protective film forming process are repeated a predetermined number of times. .

  If the photoresist pattern is formed three times or more, the first photoresist pattern forming step → the first photoresist protective film forming step → the second photoresist pattern forming step → the first photoresist protective film removing → the third photoresist pattern forming, if necessary. The protective film may be removed one by one in the following order: process → second photoresist protective film forming process → fourth photoresist pattern forming process → second photoresist protective film removal → fifth photoresist pattern forming process →.

For example, trisdimethylaminosilane (TDMAS, SiH (N (CH ₃ ) ₂ ) ₃ ), dichlorosilane (SiH ₂ Cl ₂ ), hexachlorodisilane (Si ₂ Cl ₆ ), trichlorosilane (SiCl ₄ ) is used as the Si raw material, For example, H ₂ O, H ₂ O ₂ , O ₂ , O _3, etc. are used as the oxidation raw material, and the Si raw material and the oxidation raw material are alternately supplied by the ALD method, and the alternate supply is repeated a plurality of times as desired. A SiO ₂ film having a thickness can be formed. Thereby, the SiO ₂ film 604 as the first photoresist protective material can be formed at a low temperature.

  As described above, the first photoresist pattern can be protected by forming a thin film on the surface of the first photoresist pattern. When the second photoresist solvent is applied, the second photoresist solvent is used as the first photoresist pattern. Can be prevented from penetrating into

  Further, since the second photoresist solvent can be prevented from penetrating into the first photoresist pattern as described above, the second photoresist pattern can be formed in a portion where the first photoresist pattern is not formed, and the first photoresist is formed. A fine photoresist pattern in which the minimum distance between the pattern and the second photoresist pattern is 50 nm or less can be formed.

  Furthermore, by forming a thin film on the surface of the first photoresist pattern, the mechanical strength of the first photoresist pattern can be improved in the second photoresist pattern forming step.

Furthermore, by applying a thin film capable of performing a process at an extremely low temperature, such as an extremely low temperature (catalyst) SiO ₂ film formed using a catalyst, as the first photoresist protective film, Since the thin film can be formed at a temperature lower than the temperature at which the alteration occurs, alteration of the first photoresist pattern can be prevented in the thin film first photoresist protective film forming step.

Furthermore, since the SiO ₂ film has a high wet etching rate, it can be easily removed when the SiO ₂ film needs to be removed.

In addition, in the photoresist processing, problems such as misalignment with respect to the lower layer and misalignment of the lower layer usually occur. In this case, the photoresist pattern once formed is removed by ashing treatment using oxygen plasma or the like to form a photoresist pattern. A rework process (re-work) is performed in which the process is restarted from the beginning. However, there is a problem in that the first photoresist pattern is damaged by oxygen plasma or the like during the rework process of the second photoresist pattern. However, as described above, the first photoresist pattern is protected during the rework process of the second photoresist pattern by forming a thin film such as a SiO ₂ film that can withstand the ashing process using oxygen plasma or the like on the first photoresist pattern. be able to.

  Further, when forming the second photoresist pattern, it is necessary to detect an alignment mark formed on the wafer for alignment with the lower layer pattern. Therefore, the thin film as the first photoresist protective film is required to have transparency.

In the above-described embodiment, as the first photoresist protective film, the cryogenic SiO ₂ film, which is a thin film formed by using an ALD method using a Si raw material, an oxidizing raw material, and a catalyst, has been described. However, the present invention is not limited to this as long as the film can be formed at a temperature capable of preventing the above, and other film forming methods and other film types are also applicable. For example, a film forming technique using light energy such as a film forming method for inducing a predetermined reaction by irradiating the source gas with ultraviolet light or the like may be used.

  Furthermore, in the above-described embodiment, when forming a thin film in the first photoresist protective film forming step, an example of a vertical substrate processing apparatus has been described. However, the present invention also applies to a single wafer processing apparatus. Applicable.

  In the above-described embodiment, the substrate processing apparatus for forming a thin film is described as an example of the semiconductor manufacturing apparatus. However, the semiconductor manufacturing apparatus includes a photoresist processing apparatus for forming a photoresist pattern in addition to the substrate processing apparatus. May be. Thereby, the formation of the photoresist pattern and the thin film formation can be processed consistently.

  Hereinafter, preferred embodiments of the present invention will be additionally described.

(Appendix 1)
According to one aspect of the invention,
A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of alternately supplying two or more source gases to the substrate and depositing a thin film on at least the surface of the first photoresist pattern;
A third step of forming a second photoresist pattern in a part of the region where the first photoresist pattern is not formed;
A method of manufacturing a semiconductor device is provided.

(Appendix 2)
According to another aspect of the invention,
A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of alternately supplying a first source gas containing a first substance and a second source gas containing a second substance to the substrate to deposit a thin film on at least the surface of the first photoresist pattern; ,
A third step of forming a second photoresist pattern in a part of the region where the first photoresist pattern is not formed;
Have
In the second step, there is provided a method for manufacturing a semiconductor device, characterized in that a catalyst is supplied to the substrate together with at least one of the first source gas and the second source gas.

(Appendix 3)
According to another aspect of the invention,
A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of alternately supplying two or more source gases to the substrate and depositing a thin film on at least the surface of the first photoresist pattern;
A third step of forming a second photoresist pattern in a part of the region where the first photoresist pattern is not formed;
A method for forming a photoresist pattern is provided.

(Appendix 4)
Furthermore, a semiconductor device manufactured by performing etching using the formed first and second photoresist patterns as a mask is provided.

(Appendix 5)
Furthermore, a semiconductor device manufactured by processing a lower layer of the first photoresist pattern and the second photoresist pattern and processing the substrate is provided, and the semiconductor device manufactured by removing at least a part of the thin film is provided. .

(Appendix 6)
According to another aspect of the invention,
A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of forming a thin film on at least the surface of the first photoresist pattern;
A third step of forming a second photoresist pattern in a portion where the first photoresist pattern is not formed;
A method of manufacturing a semiconductor device having the above is provided.

(Appendix 7)
Preferably, the second step is performed at a processing temperature lower than the alteration temperature of the first photoresist for forming the first photoresist pattern.

(Appendix 8)
Preferably, in the second step, a thin film is formed on the substrate and on the surface of the first photoresist pattern and the surface of the portion where the first photoresist pattern is not formed.

(Appendix 9)
Preferably, the first step forms a plurality of first photoresist patterns in a partial region on the substrate, and the second step forms a thin film on the top and side surfaces of at least the plurality of first photoresist patterns. The thin film is formed so that the minimum distance between the opposing portions of the surface of the thin film formed on the side surface is larger than the width of the second photoresist pattern.

(Appendix 10)
Preferably, in the third step, the second photoresist pattern is formed so that the minimum distance from the first photoresist pattern is 50 nm or less.

(Appendix 11)
Preferably, the thin film is formed at a processing temperature of 150 ° C. or lower.

(Appendix 12)
Preferably, the thin film is formed at a processing temperature of 100 ° C. or lower.

(Appendix 13)
Preferably, the thin film is formed at a processing temperature of 75 ° C.

(Appendix 14)
Preferably, the thin film is transparent to visible light.

(Appendix 15)
Preferably, the thin film is a SiO ₂ film.

(Appendix 16)
Preferably, the SiO ₂ film is formed using a Si raw material, an oxidizing raw material, and a catalyst.

(Appendix 17)
Preferably, the Si raw material is any one of trisdimethylaminosilane (SiH (N (CH ₃ ) ₂ ) ₃ ), dichlorosilane (SiH ₂ Cl ₂ ), hexachlorodisilane (Si ₂ Cl ₆ ), and trichlorosilane (SiCl ₄ ). It is.

(Appendix 18)
Preferably, the oxidation raw material includes a plurality of atoms having different electronegativity from each other in the molecule.

(Appendix 19)
Preferably, the raw material _oxide, H 2 _O, is either H 2 _{O 2.}

(Appendix 20)
Preferably, the decomposition temperature of the catalyst is higher than the vaporization temperature of the oxidation raw material.

(Appendix 21)
Preferably, the catalyst is any one of pyridine, pyrimidine and quinoline.

(Appendix 22)
Preferably, the method includes a fourth step of removing the second photoresist pattern by an ashing process using oxygen plasma.
The thin film has a composition that is resistant to oxygen plasma.

(Appendix 23)
Preferably, a processing chamber for processing a substrate;
A raw material supply unit for supplying Si raw material, oxidizing raw material, and catalyst to the processing chamber;
A control unit for controlling at least the raw material supply unit;
Have
The control unit
Using a substrate processing apparatus that controls the raw material supply unit so that the Si raw material and the catalyst and the oxidizing raw material and the catalyst are alternately supplied to the processing chamber,
A thin film is formed.

(Appendix 24)
Preferably,
A processing chamber for processing the substrate;
A first raw material supply system for supplying Si raw material into the processing chamber;
A second raw material supply system for supplying an oxidation raw material into the processing chamber;
A catalyst supply system for supplying the catalyst into the processing chamber;
A heating unit for heating the substrate;
A control unit for controlling the first raw material supply system, the second raw material supply system, the catalyst supply system, and the heating unit;
Have
The control unit
The heating unit is controlled so that the temperature at which the substrate is heated is lower than the alteration temperature of the first photoresist that forms the first photoresist pattern, and the Si raw material and catalyst, and the oxidizing raw material and catalyst alternately Using a substrate processing apparatus for controlling the raw material supply unit so as to repeat the alternate supply a plurality of times.
A thin film is formed.

(Appendix 25)
Preferably, the method includes a fifth step of removing the thin film after forming the second photoresist pattern.

(Appendix 26)
Preferably, the thin film has a composition that is easy to remove.

(Appendix 27)
Preferably, the thin film is removed by a dry etching method.

(Appendix 28)
Preferably, the thin film is a SiO ₂ film and is removed by a wet etching method using a dilute HF aqueous solution.

(Appendix 29)
Preferably, in the third step, the second photoresist pattern is formed by applying a second photoresist solvent,
The thin film has a composition capable of preventing immersion of the second photoresist solvent.

(Appendix 30)
According to another aspect of the invention,
A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of forming a thin film on at least the surface of the first photoresist pattern;
A third step of forming a second photoresist pattern in a portion where the first photoresist pattern is not formed;
A method for forming a photoresist pattern is provided.

(Appendix 31)
Preferably, etching is performed using the first photoresist pattern and the second photoresist pattern formed by the above-described photoresist pattern forming method as a mask, and a lower layer of the first photoresist pattern and the second photoresist pattern is processed to form a desired substrate. A semiconductor device manufactured by performing the above process is provided.

(Appendix 32)
Preferably, the minimum distance between the first photoresist pattern and the second photoresist pattern is 50 nm or less.

(Appendix 33)
According to another aspect of the present invention, a photoresist processing apparatus for forming a photoresist pattern in a partial region on a substrate subjected to a predetermined process;
There is provided a semiconductor manufacturing apparatus having a substrate processing apparatus for forming a thin film on at least a surface of the photoresist pattern.

(Appendix 34)
Preferably, the photoresist processing apparatus is
A first photoresist processing apparatus for forming a first photoresist pattern in a partial region on a substrate subjected to predetermined processing;
A second photoresist processing apparatus for forming a second photoresist pattern in a portion where the first photoresist pattern is not formed;
Is a photoresist processing apparatus.

(Appendix 35)
Preferably, the substrate processing apparatus includes:
A processing chamber for processing the substrate;
A first raw material supply system for supplying Si raw material into the processing chamber;
A second raw material supply system for supplying an oxidation raw material into the processing chamber;
A catalyst supply system for supplying the catalyst into the processing chamber;
A heating unit for heating the substrate;
A control unit for controlling the first raw material supply system, the second raw material supply system, the catalyst supply system, and the heating unit;
Have
The control unit
While heating the substrate to a processing temperature lower than the first photoresist alteration temperature,
A first raw material supply system, a second raw material supply system, a catalyst supply system, and a heating unit so that the Si raw material and the catalyst, the oxidation raw material and the catalyst are alternately supplied to the processing chamber, and the alternating supply is repeated a plurality of times. To control.

(Appendix 36)
Preferably, the third step comprises
A photoresist solvent coating step of forming a photoresist film by coating a photoresist solvent on the substrate on which the first photoresist pattern and the thin film are formed;
An exposure process in which a substrate is exposed using a predetermined mask pattern to selectively sensitize a photoresist film and transfer a desired pattern;
A development step of immersing the exposed substrate in a developer and removing an excess portion of the photoresist film.

DESCRIPTION OF SYMBOLS 101 Substrate processing apparatus 105 Cassette shelf 107 Reserve cassette shelf 110 Cassette 111 Case 114 Cassette stage 115 Boat elevator 118 Cassette transfer device 118a Cassette elevator 118b Cassette transfer mechanism 123 Transfer shelf 125 Wafer transfer mechanism 125a Wafer transfer device 125b Wafer transfer Loading device elevator 125c Tweezer 128 Arm 134a, 134b Clean unit 147 Furnace port shutter 200 Wafer 201 Processing chamber 202 Processing furnace 203 Reaction tube 207 Heater 209 Manifold 210 Bottom plate 211 Top plate 212 Post 217 Boat 218 Boat support base 219 Seal cap 220 O-ring 231 Exhaust pipe 243e Valve 246 Vacuum pump 267 Boat rotation mechanism 280 Controller 310 320 Source gas supply pipe 330 Catalyst supply pipe 312, 322, 332 Mass flow controller 314, 324, 334 Valve 410, 420, 430 Nozzle 410 a, 420 a Gas supply hole 430 a Catalyst supply hole 510, 520, 530 Carrier gas supply pipe 512, 522 , 532 Mass flow controller 514, 524, 534 Valve 601: Hard mask (HM)
602a: first photoresist solvent 602b: second photoresist solvent 603a: first photoresist pattern 603b: first photoresist pattern 604: SiO ₂ film

Claims (5)

A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of alternately supplying two or more kinds of source gases to the substrate and depositing a thin film on at least the surface of the first photoresist pattern;
A third step of forming a second photoresist pattern in a part of the region where the first photoresist pattern is not formed;
A method for manufacturing a semiconductor device, comprising: A first step of forming a first photoresist pattern in a partial region on the substrate;
A first source gas containing a first substance and a second source gas containing a second substance are alternately supplied to the substrate to deposit a thin film on at least the surface of the first photoresist pattern. Process,
A third step of forming a second photoresist pattern in a part of the region where the first photoresist pattern is not formed;
Have
In the second step, a catalyst is supplied to the substrate together with at least one of the first source gas and the second source gas. A first step of forming a first photoresist pattern in a partial region on the substrate;
A second step of alternately supplying two or more kinds of source gases to the substrate and depositing a thin film on at least the surface of the first photoresist pattern;
A third step of forming a second photoresist pattern in a part of the region where the first photoresist pattern is not formed;
A method for forming a photoresist pattern, comprising:   A semiconductor device manufactured by performing etching using the first photoresist pattern and the second photoresist pattern formed by using the photoresist pattern forming method according to claim 3 as a mask. A semiconductor device manufactured by processing the lower layer of the first photoresist pattern and the second photoresist pattern and processing the substrate, wherein the semiconductor device is manufactured by removing at least a part of the thin film. The semiconductor device according to claim 4.