JP2009271184A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct emission luminance in accordance with deterioration of a light emitting element. <P>SOLUTION: The display device comprises a non-display part 7 and a non-display part drive control circuit 9, in addition to a display part. The non-display part drive control part 9 includes a peak hold circuit 901 which detects a maximum value of accumulative luminance value; a latch circuit 902 which holds the maximum value of accumulative luminance value detected by the circuit 901 at an optional time of a frame period; a subtractor 903 which computes an update value that is a difference between the maximum value of accumulative luminance value of the just-before frame and the maximum value of accumulative luminance value of the current frame; and drive circuits 906-908 which drives a pixel disposed in the non-display part 7 based on the update value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device, and more particularly to a display device that performs luminance correction based on deterioration of a light emitting element.

  An organic EL display device is a self-luminous element and does not require a backlight necessary for a liquid crystal display device or the like, and thus can be easily reduced in weight and thickness. In addition, since the response speed is as high as several μs, there is no problem such as afterimage, and therefore, development aimed at practical use has been actively conducted.

  FIG. 15 is a block diagram showing a configuration example of a conventional organic EL display device.

  The organic EL display device includes a signal control circuit 1, a power supply circuit 2, a frame memory 3, a data line driving circuit 4, a scanning line driving circuit 5, and a display unit 6.

  The display unit 6 includes a pixel array arranged in an m × n matrix in order to display an image.

  The signal control circuit 1 sends a clock signal, a data signal, a control signal, and the like necessary for various controls from a video signal, a synchronization signal, a clock signal, and the like supplied from the outside to the frame memory 3, the data line driving circuit 4, and the scanning line driving. Supply to circuit 5 and the like.

  Then, image data conversion processing, data transfer processing, timing control processing, and the like necessary for displaying a video are performed.

  The power supply circuit 2 supplies power to each part constituting the display device, and in FIG. 15, supply to the power supply line (Vdd) and the common electrode (GND) of the display unit 6 is shown.

  The frame memory 3 is a storage circuit for storing image data having luminance information for displaying video.

  The scanning line driving circuit 5 performs timing control of data programming processing from the data line driving circuit 4 to the pixels arranged in the display unit 6.

  FIG. 16 is a block diagram illustrating a configuration example of the scanning line driving circuit 5. FIG. 17 is a timing chart showing the driving timing of the scanning line driving circuit 5 shown in FIG.

  The signal control circuit 1 generates a vertical synchronization signal and a horizontal synchronization signal in order to transfer image data from the frame memory 3 to the data line driving circuit 4.

  Then, a clock signal CLK # 3, a vertical start signal, and a write signal for performing data programming processing from the data line driving circuit 4 to the pixels arranged in the display unit 6 are generated and output to the scanning line driving circuit 5.

  The scanning line driving circuit 5 includes a shift register 501, a logical product circuit 502, and an output circuit 503.

  The shift register 501 receives a vertical start signal indicating the start of data transfer and a clock signal CLK # 3 having a horizontal synchronization period.

  The shift register 501 includes an internal register that is not less than m, which is the number of effective scanning lines of the panel, and not more than the number of scanning lines. Then, by sequentially outputting the vertical start signal according to CLK # 3, a scanning line selection signal for performing line sequential scanning is generated.

The AND circuit 502 receives a scanning line selection signal that is an output of the shift register 501 and a write signal that is an output of the signal control circuit 1. The write signal is a control signal indicating a desired timing for performing a data programming process on the pixels arranged in the display unit 6. The logical product circuit 502 takes the logical product of the scanning line selection signal and the write signal and outputs the logical product as scanning line signals S _{1 to} Sm via the output circuit 503.

  The data line driving circuit 4 transfers image data for one scan, which is a video signal, from the frame memory 3 to the display unit 6.

  FIG. 18 is a block diagram illustrating a configuration example of the data line driving circuit 4. FIG. 19 is a timing chart showing the driving timing of the data line driving circuit 4 shown in FIG.

  The signal control circuit 1 transfers image data from the frame memory 3 to the data line driving circuit 4 by an address bus, a data bus, a read control signal, and a clock signal CLK # 1 (not shown).

  Then, the data line driving circuit 4 generates a clock signal CLK # 2 and a latch signal having a horizontal synchronization period necessary for receiving image data.

  The data line driving circuit 4 includes a shift register 401, a latch circuit 402, a D / A converter 403, and an output circuit 404.

  The shift register 401 includes an internal register having at least n display pixels. The shift register 401 transfers the image data for one scan transferred from the frame memory 3 to the internal register in synchronization with the clock signal CLK # 2, and serial-parallel converts the image data.

  The latch circuit 402 latches the output bits of the shift register 401 by the horizontal synchronization period latch signal output from the signal control circuit 1 and holds image data for one scan for one scan period.

The latched image data is input to the D / A converter 403, converted into an analog signal, output from the output circuit 404 as data line signals D _{1 to} D _n , and supplied to the pixels arranged in the display unit 6. Is done.

  FIG. 20 is a circuit diagram illustrating a specific configuration example of pixels arranged in the display unit 6.

  The pixels are arranged at intersections of orthogonally arranged scanning lines and data lines, and are composed of a switching transistor Tr1, a driving transistor Tr2, a storage capacitor Cs, and an organic EL element OLED.

  The switching transistor Tr1 functions as a switching transistor that operates according to the scanning line signal, and operates as a sampling circuit that holds the data line signal in the holding capacitor Cs. The driving transistor Tr2 operates as a drive control circuit that drives the organic EL element OLED to emit light according to the signal potential held in the holding capacitor Cs.

  Accordingly, the pixel programmed with the data line signal by the scanning line signal holds the driving state corresponding to the signal potential for one frame period.

  FIG. 21 is a block diagram illustrating a configuration example of an organic EL display device described in Patent Document 1.

  A display unit 6 that displays an image and a non-display unit 7 that does not display an image are provided. The non-display unit 7 includes a pixel including a light emitting element and a measurement circuit that detects a change in light emission luminance.

  The pixels arranged in the non-display portion 7 are driven and controlled by inputting the same scanning line signal and data line signal as the pixels arbitrarily selected from the pixels arranged in the display portion 6.

  Then, the luminance emitted in response to the drive control is detected by a measurement circuit arranged in the non-display unit 7.

Based on the detected luminance information, correction data is generated by the image data correction circuit 11, the luminance of the display unit 6 pixels is corrected, and at the same time, the luminance of the non-display unit 7 pixels is also corrected.
JP 2001-265283 A

  However, characteristic fluctuations due to threshold fluctuations of the driving transistor Tr2 and temporal fluctuations of the organic EL element OLED greatly affect the light emission luminance.

  Therefore, in putting an organic EL display device into practical use, it is necessary to solve luminance unevenness, color shift (color balance collapse), and the like due to luminance fluctuation.

  As a countermeasure against these luminance fluctuations, there is a luminance correction method using a forward control method.

  However, the organic EL material is very weak against moisture, oxygen, light, heat, and impurities, and the deterioration rate of the organic EL material varies greatly depending on the manufacturing process conditions and driving conditions.

  Therefore, in order to use the brightness correction method based on the forward control, it is necessary to suppress variations in the manufacturing process, which may reduce the yield and increase the cost.

  Further, as a countermeasure against luminance fluctuation, there is a luminance correction method using a feedback control method.

  However, since it is necessary to provide a photodetection element and a feedback circuit such as a detection signal line such as a driving voltage for the pixels arranged in the display unit 6, the aperture ratio decreases and the wiring load capacity increases.

  As a result, the deterioration of the light emitting element may be accelerated due to an increase in peak light emission luminance and a temperature increase such as heat generation as required specifications.

  Furthermore, according to the technique described in Patent Document 1, it is possible to perform luminance correction on a pixel of the display unit 6 that is arbitrarily selected, but many other pixels have different driving conditions and different deterioration characteristics. For this reason, correction for all the pixels arranged in the display unit 6 may not be possible.

  Accordingly, an object of the present invention is to provide a technique for correcting light emission luminance in accordance with deterioration of a light emitting element.

  In order to solve the above problems, the present invention provides a display unit for displaying an image, a plurality of pixels including a light emitting element, a pixel including the light emitting element, and the luminance of the light emitting element. A non-display portion that does not display video, a cumulative calculation processing circuit for calculating and storing the cumulative luminance value of each pixel of the display portion, and the cumulative luminance value based on the cumulative luminance value In a display device comprising: a non-display unit drive control circuit that controls pixels arranged in a non-display unit; and a correction processing circuit that corrects the luminance of the pixels arranged in the display unit based on the accumulated luminance value The non-display unit drive control circuit includes a peak hold circuit that detects a maximum value of the cumulative luminance value, and a label that holds the maximum value of the cumulative luminance value detected by the peak hold circuit at an arbitrary timing of a frame period. A subtractor for calculating an update value that is a difference between the maximum value of the accumulated luminance value of the immediately preceding frame and the maximum value of the accumulated luminance value of the current frame, and the non-display unit based on the updated value. And a driving circuit for driving the pixels arranged in the.

  According to the present invention, in addition to the display unit 6 for displaying an image, the non-display unit 7 for monitoring the light emission characteristics of the pixels is provided, thereby reducing the aperture ratio of the display unit 6 and increasing the wiring load capacity. The light emitting element characteristics can be measured without incurring.

  The cumulative luminance value of each pixel arranged in the display unit 6 is calculated, and the pixels arranged in the non-display unit 7 are driven and controlled according to the update value ΔPmax of the maximum value, so that among the pixels arranged in the display unit 6 Thus, driving equivalent to that of the pixel having the most severe stress condition can be performed.

  Further, since the luminance correction control performed by the correction processing circuit is also reflected in the accumulated luminance value, the driving conditions of the pixels of the display unit 6 and the non-display unit 7 are the same.

  As described above, since the pixels arranged in the display unit 6 and the non-display unit 7 can be driven in the same manner and can measure the light emitting element characteristics, variations in the manufacturing process can be reduced.

  Further, since there is no need to provide a feedback circuit in the display unit 6, the aperture ratio can be improved and an increase in wiring load capacity can be suppressed. As a result, it is possible to reduce the peak emission luminance as the required specification, suppress the temperature rise such as heat generation, and suppress the deterioration.

  Furthermore, among the pixels arranged in the display unit 6, the pixels that can take the maximum accumulated luminance value change according to the video signal, and are not limited to specific pixels. Therefore, the pixels of the display unit 6 that perform the same drive as the pixels arranged in the non-display unit 7 are all the pixels arranged in the display unit 6.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of an active matrix display device as one embodiment of the present invention.

  In addition to the configuration shown in FIG. 15, the display device according to the present embodiment includes a non-display unit 7 that does not display a video signal indicating video, a cumulative calculation processing circuit 8, a non-display unit drive control circuit 9, and a correction processing circuit. 10.

  The cumulative calculation processing circuit 8 includes a cumulative calculation memory 801 and an adder 802.

  The cumulative calculation memory 801 stores the cumulative luminance value for each pixel constituting the m × n matrix of the display unit 6.

  The adder 802 performs an addition operation between the luminance value obtained by performing the deterioration correction on the video signal output from the frame memory 3 and the accumulated luminance value stored in the accumulated operation memory 801.

  Here, an organic EL display device corresponding to a full high-definition television is assumed as the display device of the present embodiment. As specific performance, it is assumed that the frame frequency is 120 Hz, progressive scanning, the number of pixels is 1920 × 1080 (m = 1080, n = 1920), the number of quantization bits is 16 bits, and the guaranteed durability time of the apparatus is 100,000 hours.

  At this time, the minimum address space required for the cumulative calculation memory is 2M bits.

Further, the value necessary for storing the accumulated luminance value of each frame as integer type data is 120 × 3600 × 100000 × 2 ¹⁶ <2 ⁵⁵ , and it is sufficient that the data capacity of 8 bytes per pixel is sufficient. .

  Therefore, the capacity of the cumulative calculation memory required for full-color display with three colors of RGB is 2 megabits × 8 bytes × (RGB) = 48 Mbytes.

  As the cumulative calculation memory 801, a non-volatile memory is desirable, but it has problems of the number of write cycles and high-speed operation.

  Therefore, a configuration in which a volatile memory such as a DRAM and a nonvolatile memory are used together may be employed. A volatile memory is used for normal cumulative calculation processing, and a data transfer step between the volatile memory and the non-volatile memory is used when the power supply is started or shut down.

  The non-display portion drive control circuit 9 includes a peak hold circuit 901, a latch circuit 902, a subtractor 903, a comparator 904, a latch circuit 905A, a latch circuit 905B, a switch 906, a D / A converter 907, and an output circuit 908. .

  The peak hold circuit 901 holds and outputs the maximum accumulated luminance value P (i, j) max, which is the maximum value of the accumulated luminance value P (i, j) for each pixel constituting the m × n matrix of the display unit 6. . The output maximum accumulated luminance value P (i, j) max is input to the latch circuit 902, the subtractor 903, and the comparator 904.

  The latch circuit 902 latches the maximum accumulated luminance value P (i, j) max at an arbitrary timing in the frame period (vertical synchronization signal period), and outputs the maximum accumulated luminance value Pmax in the immediately preceding frame.

  The subtractor 903 subtracts the maximum accumulated luminance value P (i, j) max that is the output of the peak hold circuit 901 and the maximum accumulated luminance value Pmax of the previous frame that is the output of the latch circuit 902 {P (i , J) max−Pmax}. That is, the difference between the maximum cumulative luminance value of the previous frame and the maximum cumulative luminance value of the current frame is calculated.

  Then, the latch circuit 905A latches the subtraction value {P (i, j) max−Pmax} at an arbitrary timing of the frame period (vertical synchronization signal period), and outputs the update value ΔPmax.

  The update value ΔPmax is converted into an analog signal by the D / A converter 907 via the switch 906 and is output from the output circuit 908 to be used as a control signal for driving the pixels arranged in the non-display unit 7.

  The switching unit 906 can perform switching control between the update value ΔPmax and a desired reference value in accordance with the switching signal output from the signal control circuit, and provides a control signal for driving the pixels arranged in the non-display unit 7. Can be switched.

  The comparator 904 performs a comparison operation between the maximum accumulated luminance value P (i, j) max of the current frame that is the output of the peak hold circuit 901 and the maximum accumulated luminance value Pmax of the immediately preceding frame that is the output of the latch circuit 902. Do. Then, a maximum value update flag signal indicating whether or not the maximum accumulated luminance value P (i, j) max is updated is output. Then, the latch circuit 905B latches and outputs the maximum value update flag signal at an arbitrary timing of the frame period (vertical synchronization signal period).

  The accumulated luminance value P (i, j) is calculated based on the luminance value obtained by correcting the deterioration characteristics of each pixel by the correction processing circuit 10.

  The non-display unit 7 does not display a video signal, but is used for monitoring temporal changes of the driving transistor Tr2 and the organic EL element OLED, and includes at least one pixel and a measurement circuit.

  The pixels arranged in the non-display portion 7 are preferably formed simultaneously under the same conditions as the pixels arranged in the display portion 6, and a plurality of pixels corresponding to a plurality of emission colors may be arranged. Further, the pixels arranged in the non-display unit 7 may be arranged at any position as long as it is outside the area constituting the m × n matrix of the display unit 6. Further, it may be an individual substrate manufactured under the same conditions in the manufacturing process.

  FIG. 2 is a circuit diagram showing a configuration example of the pixels arranged in the non-display unit 7.

  The pixels arranged in the non-display unit 7 include a driving transistor Tr2 that controls light emission of the organic EL element OLED with a signal potential corresponding to the update value ΔPmax or the reference value.

  Light emitted from the organic EL element is received by a photodiode PD as a light receiving element, a photocurrent corresponding to the amount of received light is converted into a voltage by an IV converter 701, and digitally converted by an A / D converter 702. . By detecting this voltage, the luminance measurement circuit detects the light emission luminance of the organic EL element.

  Digital conversion is performed by a voltage detector 703 and an A / D converter 704 that detect the source voltage of the driving transistor Tr2 or the anode voltage of the organic EL element OLED. By doing in this way, the voltage measurement circuit which detects the voltage between the gate-source of a drive transistor or the forward voltage value of an organic EL element is provided.

  A driving current flowing through the organic EL element controlled by the driving transistor Tr2 is subjected to current-voltage conversion by a transistor 705, a transistor 706, a resistor 707, and a differential amplifier 708 that form a current mirror circuit. Thereafter, a current measurement circuit that detects the drive current by digital conversion by the A / D converter 704 is provided.

  Next, an operation for measuring the characteristics of the pixels of the non-display unit 7 and obtaining a correction value for correcting the video signal (luminance value) will be described.

  FIG. 3 is a flowchart showing a control example of the present embodiment.

  An outline of the operation of the present embodiment will be described.

  After displaying the video signal, it is determined whether or not the process can be executed in the vertical blanking period, the pixels arranged in the non-display unit 7 are measured, the luminance correction data is calculated, and the correction data is written in the lookup table LUT1001. In this way, a correction lookup table is created.

  The signal control circuit 1 detects a maximum value update flag indicating whether or not the maximum cumulative luminance value Pmax is updated. If the maximum cumulative luminance value Pmax is not updated, the signal control circuit 1 ends without executing the subsequent steps (Step S101 / No). ).

  If the maximum accumulated luminance value Pmax has been updated (step S101 / Yes), the process proceeds to step S102.

  The maximum accumulated luminance value Pmax is read (step S102).

  It is determined whether or not the maximum accumulated luminance value Pmax exceeds a desired segmented area (step S103). The desired segment area is not particularly limited as long as the characteristic variation falls within the allowable range.

  That is, if the value of the maximum accumulated luminance value Pmax is within a desired segment area, it is determined that the characteristic is within the allowable range, and the process ends (step S103 / No).

  If the maximum accumulated luminance value Pmax exceeds the desired segmented area (Yes at step S103), it is determined that the characteristic variation needs to be confirmed, and the subsequent correction data generation routine is executed.

  Hereinafter, the correction data generation routine will be described.

  By switching the control signal of the switch 906 to the reference value, a signal for driving and controlling the pixels of the non-display unit 7 is set as a desired reference value (step S201).

  The luminance with respect to the reference value of the organic EL element OLED provided in the pixel of the non-display unit 7 is detected by the luminance measuring circuit described above (step S202).

  By switching the control signal of the switch 906 to the update value ΔPmax, the signal for controlling the driving of the pixels of the non-display section 7 is made equal to the driving stress condition of the pixels of the display section 6 (step S203).

  As a means for correcting the light emission efficiency deterioration of the organic EL element OLED, the ratio Lo / L calculated from the initial value Lo set at the time of factory shipment and the luminance value L detected by the luminance measuring circuit is used as the correction value ( Step S204).

  The correction value obtained in step S204 is stored in an address corresponding to the section area of the lookup table LUT1001 (step S205).

  As described above, by measuring the deterioration characteristics of the pixels of the non-display unit 7 that have been driven in the same manner as the pixels having the severest stress conditions among the pixels arranged in the display unit 6, a highly accurate luminance correction value can be obtained. Can be obtained.

  Next, a method for correcting the video signal will be described.

  The correction processing circuit 10 for correcting the luminance of the video signal includes a look-up table LUT 1001 and a multiplier 1002.

  In the lookup table LUT1001, the ratio for correcting the luminance deterioration according to the accumulated luminance value is recorded as described above.

  For this reason, the multiplier 1002 multiplies the correction value of the lookup table LUT1001 and the video signal (luminance value) to obtain a video signal in which the deterioration characteristics of each pixel are corrected.

  By transferring the corrected video signal to the data line driving circuit 4, it is possible to display a video with little luminance fluctuation on the display unit 6.

  In addition, the corrected video signal is transferred to the cumulative arithmetic processing circuit 8. In this way, the cumulative calculation value is calculated and recorded, and the pixels arranged in the non-display portion 7 are driven by the non-display portion drive control circuit 9, and the stress condition is the most severe among the pixels of the display portion 6. Drive equivalent to the pixel is performed.

  FIG. 4 is a diagram showing a pseudo display unit in which 2 × 3 matrix pixels are arranged on the display unit 6 of the organic EL display device according to the present embodiment and pseudo video signals (luminance values) for five frames.

  The display frame shifts from VF (1) => VF (2) => VF (3) => VF (4) => VF (5), and the video signal of each frame is described as the luminance value of 2 × 3 matrix pixels. is there.

  FIG. 5 is a schematic diagram showing a memory map concept of the lookup table LUT 1001 using the pseudo parameter and the virtual parameter of FIG.

  The look-up table LUT 1001 performs address mapping assuming that the divided areas of accumulated luminance values are divided areas such as 0 to 6, 7 to 12, 13 to 18, 19 to 24, and so on.

  FIG. 6-8 is a timing chart showing an operation when the pseudo parameters shown in FIGS. 4 and 5 are used.

  Hereinafter, a description will be given with reference to FIGS.

  In order to display the first display frame VF (1), the addresses of the frame memory 3 and the cumulative calculation memory 801 are set in the pixel (1, 1) according to the vertical synchronizing signal and the horizontal synchronizing signal.

  Data is output by a read signal RD that is an output control signal.

  The frame memory 3 outputs the luminance value “3” of the pixel (1, 1) of the first display frame VF (1), and the cumulative calculation memory 801 outputs the cumulative luminance value “0”.

  The accumulated luminance value “0” that is the output of the accumulated calculation memory 801 is input to the adder 802 arranged in the accumulated calculation processing circuit and the lookup table LUT 1001 arranged in the correction processing circuit 10.

  The look-up table LUT1001 is in an initial state at the time of shipment from the factory as shown in FIG. 6, and a correction value “1.0” is set for the input cumulative luminance values “0” to “6”. ing. Therefore, the lookup table LUT 1001 outputs a correction value “1.0” for the input cumulative luminance value “0”.

  A luminance value obtained by multiplying the correction value “1.0” and the luminance value “3” from the frame memory 3 by the multiplier 1002 and correcting the deterioration characteristic of the pixel (1, 1) arranged in the display unit 6. Get “3”.

  The luminance value obtained by correcting the deterioration characteristic which is the output of the multiplier 1002 is supplied to the data line driving circuit 4 and transferred to the adder 802 arranged in the cumulative arithmetic processing circuit 8.

  The adder 802 adds and calculates the accumulated luminance value “0”, which is the output of the accumulated calculation memory 801, and the luminance value “3”, which is the output of the multiplier 1002, with the deterioration characteristic of the pixel (1, 1) corrected. (1,1) = “3” is obtained. Then, it is recorded in the cumulative calculation memory 801 by a write signal WR that is a control signal of the cumulative calculation memory 801.

  The accumulated luminance P (1, 1) = “3”, which is the calculation result of the adder 802, is input to the peak hold circuit 901 disposed in the non-display unit drive control circuit 9. Now, since the value of the peak hold circuit 901 is “0”, the maximum accumulated luminance value P (i, j) max that is the output is updated and held at “3”. At this time, the maximum accumulated luminance value Pmax of the previous display frame, which is the output of the latch circuit 902, is “0”. Therefore, the subtraction value {P (i, j) max−Pmax}, which is the output of the subtractor 903, is “3”, and the output of the comparator 904 indicating that the maximum accumulated luminance value has been updated is “H”. Become.

  Subsequently, in order to process the next pixel, the addresses of the frame memory 3 and the cumulative calculation memory 801 are set in the pixel (1, 2) according to the horizontal synchronization signal, and data is output by the read signal RD which is an output control signal.

  The frame memory 3 outputs the luminance value “2” of the pixel (1, 2) of the first display frame VF (1), and the cumulative calculation memory 801 outputs the cumulative luminance value “0”.

  The accumulated luminance value “0” that is the output of the accumulated calculation memory 801 is input to the adder 802 arranged in the accumulated calculation processing circuit and the lookup table LUT 1001 arranged in the correction processing circuit 10.

  The look-up table LUT 1001 outputs a correction value “1.0” for the input cumulative luminance value “0”.

  The multiplier 1002 multiplies the luminance value “2” from the frame memory 3 and the correction value “1.0” to obtain a luminance value “2” in which the deterioration characteristic of the pixel (1, 2) is corrected. This luminance value is supplied to the data line driving circuit 4 and transferred to an adder 802 arranged in the cumulative arithmetic processing circuit 8.

  The adder 802 adds and calculates the accumulated luminance value “0” that is the output of the accumulated calculation memory 801 and the luminance value “2” that is the output of the multiplier 1002 and that corrects the deterioration characteristic of the pixel (1, 2). (1,2) = “2” is obtained. Then, it is recorded in the cumulative calculation memory 801 by a write signal WR that is a control signal of the cumulative calculation memory 801.

  Also, the accumulated luminance P (1,2) = “2”, which is the calculation result of the adder 802, is input to the peak hold circuit 901 disposed in the non-display unit drive control circuit 9. Now, since the maximum accumulated luminance value P (i, j) max of the peak hold circuit 901 is “3”, the value is held and no change with respect to the subsequent output stage occurs.

  Since the same operation as pixel (1,3) → (2,1) → (2,2) → (2,3) is repeated, the description is omitted.

  In the case of the pixel (2, 1) in which the maximum accumulated luminance value P (i, j) max within one frame period is updated, the same operation as that of the pixel (1, 1) is performed. For the other pixels (1, 3), (2, 2), and (2, 3), the maximum accumulated luminance value P (i, j) max within one frame period is not updated, and the pixel ( 1 and 2).

  The above operation is performed on all the pixels of the first display frame VF (1). Then, in the vertical blanking period after VF (1) is displayed on the display unit 6, a latch signal is output from the signal control circuit 1 at an arbitrary timing of the frame period (vertical synchronization signal period). This latch signal is a control signal for controlling the latch operation of each of the latch circuits 902, 905A and 905B.

  The latch circuit 905A latches the subtraction value {P (i, j) max−Pmax} = “4”, which is the output of the subtractor 903, by this latch signal, and obtains the update value ΔPmax = “4”.

  The updated value ΔPmax is supplied to the driving transistor Tr2 disposed in the non-display unit 7 via the switch 906, the D / A converter 907, and the output circuit 908. Then, light emission control of the organic EL element is performed according to the signal potential, and this state is maintained for one frame period (one vertical synchronization period).

  The latch circuit 905B latches the output of the comparator 904 indicating whether or not the maximum cumulative update value is updated, and sets the maximum value update flag signal to “H”.

  The latch circuit 902 latches the maximum accumulated luminance value P (i, j) max and updates the maximum accumulated luminance value Pmax of the previous display frame. Then, the latch circuit 902 resets the subtraction value {P (i, j) max−Pmax} which is the output of the subtractor 903 and the output of the comparator 904 indicating whether or not the maximum cumulative update value is updated.

  In the vertical blanking period after the display of the first display frame VF (1), the signal control circuit 1 that has output the latch signal executes the above-described software processing of FIG.

  The maximum value update flag, which is the output of the latch circuit 905B, is read and is “H” indicating that the maximum cumulative luminance value has been updated (step S101 / Yes), so the process proceeds to the next step.

  The maximum accumulated luminance value Pmax is read (step S102).

  Since the maximum accumulated luminance value Pmax = “4” does not exceed the desired section area “0 to 6”, this operation is terminated (step S103 / No).

  The signal control circuit 1 performs a display operation on the second display frame VF (2) after the vertical blanking period has elapsed. In order to simplify the description, the description of the operation similar to that of VF (1) is omitted.

  Now, the cumulative luminance value of all the pixels recorded in the cumulative calculation memory 801 is a value equal to or less than the maximum cumulative luminance value “4”. Therefore, all correction values output from the lookup table LUT 1001 are “1.0”, and the luminance value of the frame memory 3 and the luminance value obtained by correcting the deterioration characteristics of the multiplier 1002 have the same value.

  The signal control circuit 1 outputs a latch signal for controlling the latch operation of the latch circuits 902, 905A and 905B in the vertical blanking period after the second display frame VF (2) is displayed.

  With this latch signal, the latch circuit 905A obtains the update value ΔPmax = “5” of the maximum accumulated luminance value of the current frame VF (2) and the previous frame VF (1). The latch circuit 905B sets the maximum value update flag signal to “H”.

  The signal control circuit 1 executes the above-described software processing of FIG. 3 in the vertical blanking period after displaying the second display frame VF (2).

  The maximum value update flag, which is the output of the latch circuit 905B, is read and is “H” indicating that the maximum cumulative luminance value has been updated (step S101 / Yes), so the process proceeds to the next step.

  The maximum accumulated luminance value Pmax is read (step S102).

  Since the maximum accumulated luminance value Pmax = “9” exceeds the desired segment area “0 to 6”, the correction data generation routine after step S201 is executed (step S103 / Yes).

  Assuming that the correction value obtained from the deterioration characteristics of the pixel with respect to the reference value is “1.1” (steps S201 to S204), the correction value “1” is set in the address space corresponding to the division area “7 to 12” of the lookup table LUT1001. .1 "is recorded (step S205).

  The signal control circuit 1 performs a display operation on the third display frame VF (3) after the vertical blanking period has elapsed.

  Now, the cumulative brightness value of all the pixels recorded in the cumulative calculation memory 801 is a value equal to or less than the maximum cumulative brightness value “9”. The look-up table LUT 1001 outputs “1.0” as a correction value when the cumulative luminance value is “0” to “6”, and “1.1” as a correction value when the cumulative luminance value is “7” to “12”. To do.

  Therefore, the luminance value of the frame memory 3 and the luminance value obtained by correcting the deterioration characteristic of the multiplier 1002 may take different values.

  However, in the pseudo parameter used, the calculation result of the multiplier 1002 is within the rounding error range, so that the luminance value of the frame memory 3 and the luminance value corrected for the deterioration characteristic of the multiplier 1002 are the same value. Yes.

  The signal control circuit 1 outputs a latch signal for controlling the latch operation of the latch circuits 902, 905A and 905B in the vertical blanking period after the display of the third display frame VF (3).

  With this latch signal, the latch circuit 905A obtains the update value ΔPmax = “6” of the maximum accumulated luminance value of the current frame VF (3) and the previous frame VF (2). The latch circuit 905B sets the maximum value update flag signal to “H”.

  The signal control circuit 1 executes the above-described software processing in FIG. 3 in the vertical blanking period after the third display frame VF (3) is displayed.

  The maximum value update flag, which is an output of 905B, is read and is “H” indicating that the maximum accumulated luminance value has been updated (step S101 / Yes), and the process proceeds to the next step.

  The maximum accumulated luminance value Pmax is read (step S102).

  Since the maximum accumulated luminance value Pmax = “15” exceeds the desired segment area “7 to 12”, the correction data generation routine after step S201 is executed (step S103).

  Assuming that the correction value obtained from the deterioration characteristic of the pixel with respect to the reference value is “1.2” (steps S201 to S204), the correction value “1” is set in the address space corresponding to the section area “13 to 18” of the lookup table LUT1001. .2 "is recorded (step S205).

  The signal control circuit 1 performs a display operation on the fourth display frame VF (4) after the vertical blanking period has elapsed.

  Now, the cumulative luminance value of all the pixels recorded in the cumulative calculation memory 801 is a value equal to or less than the maximum cumulative luminance value “15”. The look-up table LUT 1001 is “1.0” when the accumulated luminance value is “0” to “6”, “1.1” when the accumulated luminance value is “7” to “12”, and the accumulated luminance value is In the case of “13” to “18”, “1.2” is output as a correction value.

  Therefore, the luminance value of the frame memory 3 and the luminance value obtained by correcting the deterioration characteristic of the multiplier 1002 may take different values.

  However, in the pseudo parameter used, the calculation result of the multiplier 1002 is within the rounding error range, so that the luminance value of the frame memory 3 and the luminance value corrected for the deterioration characteristic of the multiplier 1002 are the same value. Yes.

  The video signal of the fourth display frame VF (4) has the same maximum accumulated luminance value as that of the previous display frame VF (3) and is not updated.

  The signal control circuit 1 outputs a latch signal for controlling the latch operation of the latch circuits 902, 905A and 905B in the vertical blanking period after the display of the fourth display frame VF (4).

  Based on this latch signal, the latch circuit 905A obtains the update value ΔPmax = “0” of the maximum accumulated luminance value of the current frame VF (4) and the previous frame VF (3). The latch circuit 905B sets the maximum value update flag signal to “L”.

  The signal control circuit 1 executes the above-described software processing of FIG. 3 in the vertical blanking period after the display of the fourth display frame VF (4).

  The maximum value update flag, which is an output of 905B, is read and is “L” indicating that the maximum accumulated luminance value has not been updated (No in step S101), and thus this operation ends.

  The signal control circuit 1 performs a display operation on the fifth display frame VF (5) after the vertical blanking period has elapsed.

  Now, the cumulative luminance value of all the pixels recorded in the cumulative calculation memory 801 is a value equal to or less than the maximum cumulative luminance value “15”. The look-up table LUT 1001 is “1.0” when the accumulated luminance value is “0” to “6”, “1.1” when the accumulated luminance value is “7” to “12”, and the accumulated luminance value is In the case of “13” to “18”, “1.2” is output as a correction value.

  Therefore, the brightness value of the frame memory 3 and the brightness value obtained by correcting the deterioration characteristic of the multiplier 1002 may be different.

  At this time, with the pseudo parameters used for other than the pixel (1, 1), the calculation result of the multiplier 1002 is within the rounding error range, so the luminance value of the frame memory 3 and the deterioration characteristic of the multiplier 1002 are corrected. The luminance value is the same value.

  In the case of the pixel (1, 1), the deterioration characteristic of the multiplier 1002 from the luminance value “8” from the frame memory 3 and the correction value “1.2” for the accumulated luminance value “13” from the lookup table LUT1001. The luminance value obtained by correcting is obtained as “9”.

  The luminance value “9” is transferred to the data line driving circuit 4 and is also transferred to the adder 802 arranged in the cumulative calculation processing circuit 8.

  The adder 802 adds and calculates the accumulated luminance value “13”, which is the output of the accumulated calculation memory 801, and the luminance value “9”, which is the output of the multiplier 1002, which corrects the deterioration characteristic of the pixel (1, 1). (1,1) = “22” is obtained. Then, it is recorded in the cumulative calculation memory 801.

  The accumulated luminance value P (1,1) = “22”, which is the calculation result of the adder 802, is input to the peak hold circuit 901 disposed in the non-display unit drive control circuit 9. Now, since the value of the peak hold circuit 901 is “15”, the maximum accumulated luminance value P (i, j) max that is the output is updated and held at “22”.

  At this time, since the maximum accumulated luminance value Pmax of the previous frame VF (4) is “15”, the subtraction value {P (i, j) max−Pmax}, which is the output of the subtractor 903, becomes “7”. At the same time, the output of the comparator 904 indicating that the maximum accumulated luminance value has been updated becomes “H”.

  Subsequently, the signal control circuit 1 that has processed other pixels outputs a latch signal for controlling the latch operation of the latch circuits 902, 905A, and 905B in the vertical blanking period after the display of the fifth display frame VF (5). .

  With this latch signal, the latch circuit 905A obtains the update value ΔPmax = “7” of the maximum accumulated luminance value of the current frame VF (5) and the previous frame VF (4). The latch circuit 905B sets the maximum value update flag signal to “H”.

  The signal control circuit 1 executes the above-described software processing of FIG. 3 in the vertical blanking period after the display of the fifth display frame VF (5).

  The maximum value update flag, which is an output of 905B, is read and is “H” indicating that the maximum accumulated luminance value has been updated (step S101 / Yes), and the process proceeds to the next step.

  The maximum accumulated luminance value Pmax is read (step S102).

  Since the maximum accumulated luminance value Pmax = “22” exceeds the desired section area “13 to 18”, the correction data generation routine after S201 is executed (step S103 / Yes).

  Assuming that the correction value obtained from the deterioration characteristic of the pixel with respect to the reference value is “1.3” (steps S201 to S204), the correction value “1” is set in the address space corresponding to the division area “19 to 24” of the lookup table LUT1001. .3 "is recorded (step S205).

  FIG. 9 is a schematic diagram for explaining changes in the video signal using the virtual parameters used in FIGS. 4-8.

  FIG. 9 shows the following six values.

(1) Luminance value that is a video signal of display frames VF (1) to VF (5) (2) Correction value for accumulated luminance value P (i, j) of lookup table LUT1001 (3) With output of multiplier 1002 Luminance value corrected for certain deterioration characteristics (4) Cumulative luminance value P (i, j) of each pixel arranged in the display unit 6
(5) Maximum accumulated luminance value P (i, j) max for each frame period
(6) Update value ΔPmax
Here, the pixel with the highest driving stress that takes the maximum cumulative luminance value P (i, j) max is the pixel (2, 1) in the display frames VF (1) to VF (4), but the display frame VF ( 5) is the pixel (1, 1).

  As described above, the pixels having the maximum cumulative luminance value P (i, j) max are all the pixels arranged in the display unit 6.

  Further, since the pixels arranged in the non-display unit 7 are driven by the update value ΔPmax, the cumulative calculation value of the update value ΔPmax of the non-display unit pixel is the same as the maximum cumulative luminance value P (i, j) max of the display unit 6. Value. This indicates that the driving conditions are equivalent.

  In addition, the luminance value “8” of the pixel (1, 1) of the display frame VF (5) becomes the luminance value “9” corrected for deterioration. This indicates that the luminance correction control performed by the correction processing circuit is also reflected in the accumulated luminance value.

  Further, the correlation between the accumulated luminance value and the deterioration characteristic is obtained by the correction data generation routine executed during the vertical blanking period. Therefore, luminance correction can be performed on all the pixels arranged on the display unit 6 based on the accumulated luminance value.

(Embodiment 2)
FIG. 10 shows another circuit configuration example for obtaining the update value ΔPmax in the non-display portion drive control circuit 9, and FIG. 11 shows a timing chart for explaining the operation, which will be described below.

  The non-display unit drive control circuit 9 includes a switch 909, two peak hold circuits 901A and 901B, a subtractor 903, and a latch circuit 905A.

  In accordance with a vertical synchronization signal (not shown) of the signal control circuit 1, the cumulative luminance value P (i, j) is transferred from the cumulative arithmetic processing circuit 8 and input to the switch 909 during a vertical display period in which video is displayed on the display unit 6. To do.

  The switch 909 is controlled by the frame selection signal from the control signal circuit 1 and transfers the accumulated luminance value P (i, j) to one of the two peak hold circuits 901A and 901B.

  This frame selection signal is a signal obtained by dividing the vertical synchronization signal by ½, and the accumulated luminance value P (i, j) is alternately output to the two peak hold circuits 901A and 901B in units of frames.

  When the frame selection signal is valid among the two peak hold circuits 901A and 901B, the maximum accumulated luminance value P (i, j) max of the accumulated luminance value P (i, j) transferred in one frame period is updated. Hold.

  When the frame selection signal becomes invalid, the maximum accumulated luminance value P (i, j) max is automatically held as the accumulated luminance value Pmax of the previous frame.

  The subtractor 903 subtracts the maximum accumulated luminance value P (i, j) max of the current frame of the two peak hold circuits 901A and 901B and the maximum luminance value Pmax of the previous frame. As a result, an update value ΔPmax = {P (i, j) max−Pmax} is obtained.

  In the vertical blanking period in which the transfer of the accumulated luminance value P (i, j) in one frame period of the display unit 6 is completed, the signal control circuit 1 outputs a latch signal at an arbitrary timing in one frame period (vertical synchronization signal period). Output.

  The latch circuit 905 holds the update value ΔPmax for one frame period in accordance with the latch signal.

(Embodiment 3)
FIG. 12 shows another circuit configuration example for obtaining a maximum value update flag for determining whether or not the update value ΔPmax is updated in the non-display portion drive control circuit 9, and FIG. 13 shows a timing chart for explaining the operation. explain.

  The non-display unit drive control circuit 9 includes a peak hold circuit 901, a latch circuit 902, a subtracter 903, a latch circuit 905, and a comparator 910.

  In accordance with a vertical synchronization signal (not shown) of the signal control circuit 1, the cumulative luminance value P (i, j) is transferred from the cumulative arithmetic processing circuit 8 during the vertical display period in which video is displayed on the display unit 6, and is sent to the peak hold circuit 901. input.

  The peak hold circuit 901 updates / holds the maximum accumulated luminance value P (i, j) max of the transferred accumulated luminance value P (i, j). The maximum accumulated luminance value P (i, j) max is input to the latch circuit 902 and the subtracter 903.

  Here, the latch signal for controlling the latch operation of the latch circuit 902 and the latch circuit 905 is output from the signal control circuit 1 at an arbitrary timing of one frame period (vertical synchronization signal period) in the vertical blanking period. During the vertical blanking period, the transfer of the accumulated luminance value P (i, j) for one frame period of the display unit 6 is completed.

  The latch circuit 902 holds the maximum accumulated luminance value P (i, j) max as the maximum accumulated luminance value Pmax of the previous frame for one frame period by the latch signal from the signal control circuit 1.

  The subtractor 903 outputs a subtraction value {P (i, j) max−Pmax} between the maximum accumulated luminance value P (i, j) max that is the output of the peak hold circuit 901 and the maximum accumulated luminance value Pmax of the previous frame. And is reset by a latch signal.

  This subtraction value {P (i, j) max−Pmax} is latched by the latch circuit 905 and held as the update value ΔPmax for one frame period.

  This updated value ΔPmax is input to the comparator 910.

  The comparator 910 can determine whether or not the accumulated luminance value is updated based on the input update value ΔPmax. When the update value ΔPmax is “0”, the comparator 910 outputs “L”, and other than “0”. Outputs “H”.

(Embodiment 4)
In the non-display portion drive control circuit 9, another circuit configuration example for improving the accuracy of the correction process for the accumulated luminance value is shown in FIG.

  In order to improve the luminance correction capability using the accumulated luminance value, it is effective to use a Lagrange interpolation method, an interpolation method using a spline function, an Aitken method or an interpolation method represented by the Aitken Neville method.

  In order to use this interpolation method, it is necessary to obtain at least a plurality of data having different accumulated luminance values, and this circuit configuration is configured in view of this. Further, the same contents as those of the above-described embodiment are omitted, and differences will be described below.

  In order to monitor deterioration characteristics, the non-display unit 7 includes a plurality of pixels including a driving transistor 710, an organic EL element 711, a measurement circuit 712, and a multiplexer circuit 713 for reading measurement values.

  The non-display unit drive control circuit 9 includes a normalization circuit 911 that standardizes the update value ΔPmax and sets a standard value, and a plurality of drive circuits 906 to 908 corresponding to the pixels arranged in the non-display unit 7.

  The normalization circuit 911 is standardized and driven at the same magnification, 3/4 times, 1/2 times, and 1/4 times as reference values for normalizing the update value ΔPmax.

  Switching signals #A to #D (not shown) are interlocked with the multiplexer circuit 713 disposed in the non-display section 7 and the switch 706 disposed in the non-display section drive control circuit 9, and the correction data generation routine described above Similar operations are possible.

  Therefore, it is possible to obtain a plurality of deterioration characteristics having different accumulated luminance values, normalized by the maximum accumulated luminance value which is a pixel having the severest driving stress condition among the pixels arranged in the display unit 6.

  By using this data and a known technique of interpolation, more accurate brightness correction data generation and brightness correction processing can be performed.

  In the above embodiment, an organic EL display device is used as the display device, but the present invention is not limited to this, and can be applied to a plasma display device, an FED (field emission display), and the like.

  The present invention can be used for a display device, and in particular, can be used for an organic EL display device.

1 is a block diagram illustrating a configuration of an active matrix display device as one embodiment of the present invention. 4 is a circuit diagram illustrating a configuration example of pixels arranged in a non-display unit 7. FIG. It is a flowchart which shows the example of control of the active matrix type display apparatus as one embodiment of this invention. It is a figure which shows the pseudo | simulation display part which arranged the 2 * 3 matrix pixel in the display part of the organic electroluminescent display apparatus as one embodiment of this invention, and the pseudo | simulation video signal (luminance value) for 5 frames. FIG. 5 is a schematic diagram showing a memory map concept of a lookup table LUT1001 using pseudo parameters and virtual parameters of FIG. FIG. 6 is a timing chart showing an operation when the pseudo parameters shown in FIGS. 4 and 5 are used. FIG. 6 is a timing chart showing an operation when the pseudo parameters shown in FIGS. 4 and 5 are used. FIG. 6 is a timing chart showing an operation when the pseudo parameters shown in FIGS. 4 and 5 are used. It is a schematic diagram for demonstrating a change to the video signal using the virtual parameter used in FIGS. 4-6. It is a figure which shows the other structural example of a non-display part drive control circuit. 11 is a timing chart illustrating an operation of the non-display unit drive control circuit illustrated in FIG. 10. It is a figure which shows the other structural example of a non-display part drive control circuit. 13 is a timing chart illustrating an operation of the non-display unit drive control circuit illustrated in FIG. 12. It is a figure which shows the other structural example of a non-display part drive control circuit. It is the figure which showed the structural example of the conventional organic electroluminescent display apparatus. 2 is a block diagram illustrating a configuration example of a scanning line driving circuit 5. FIG. 17 is a timing chart showing drive timings of the scanning line drive circuit 5 shown in FIG. 3 is a block diagram illustrating a configuration example of a data line driving circuit 4. FIG. 19 is a timing chart showing drive timing of the data line drive circuit 4 shown in FIG. 3 is a circuit diagram illustrating a specific configuration example of pixels arranged in a display unit 6. FIG. It is a block diagram which shows the structural example of the organic electroluminescence display described in patent document 1. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Signal control circuit 2 Power supply circuit 3 Frame memory 4 Data line drive circuit 5 Scan line drive circuit 6 Display part 7 Non-display part 8 Accumulation calculation processing circuit 801 Accumulation calculation memory 802 Adder 9 Non-display part drive control circuit 901 Peak hold circuit 902 Latch circuit 903 Subtractor 904 Comparator 905 Latch circuit 906 Switcher 907 D / A converter 908 Output circuit 909 Switcher 910 Comparator 911 Multiplier 10 Correction processing circuit 1001 Look-up table (LUT)
1002 Multiplier 11 Image data correction circuit

Claims (8)

A plurality of pixels each having a light emitting element are disposed, and a display unit for displaying an image;
A non-display portion that does not display an image, wherein a pixel including a light emitting element and a measurement circuit that measures the luminance of the light emitting element are disposed;
A cumulative calculation processing circuit for calculating and storing a cumulative luminance value of each pixel of the display unit;
A non-display portion drive control circuit that controls pixels arranged in the non-display portion based on the accumulated luminance value;
In a display device comprising: a correction processing circuit that corrects the luminance of pixels arranged in the display unit based on the accumulated luminance value;
The non-display portion drive control circuit includes a peak hold circuit that detects a maximum value of the accumulated luminance value;
A latch circuit that holds the maximum value of the accumulated luminance value detected by the peak hold circuit at an arbitrary timing of the frame period;
A subtractor that calculates an update value that is the difference between the maximum value of the accumulated luminance value of the previous frame and the maximum value of the accumulated luminance value of the current frame;
A display device comprising: a drive circuit that drives pixels arranged in the non-display portion based on the updated value. The non-display portion drive control circuit further includes a normalization circuit that normalizes the update value,
The non-display portion includes a plurality of light emitting elements,
The display device according to claim 1, wherein the drive circuit drives the pixels of the non-display portion based on a standard value of the normalization circuit. The non-display unit drive control circuit further includes a comparator that compares the maximum value of the cumulative luminance value of the immediately preceding frame with the maximum value of the cumulative luminance value of the current frame,
The display device according to claim 1, wherein whether or not the update value is updated is determined based on a result of comparison by the comparator. The non-display portion drive control circuit further includes a comparator that compares the updated value with 0,
The display device according to claim 1, wherein whether or not the update value is updated is determined based on a result of comparison by the comparator. The non-display portion includes a light receiving element that receives light emitted by a light emitting element disposed in the non-display portion;
A measurement circuit that measures the amount of light received by the light receiving element, and
5. The display device according to claim 1, wherein the accumulated luminance value and the light emission characteristic are detected during a vertical blanking period of a video signal indicating the video. 6. The display device according to claim 5, wherein correction data of a video signal for the maximum value of the accumulated luminance value is generated based on the detected accumulated luminance value and light emission characteristics during the vertical blanking period. The correction processing circuit further includes a lookup table that records correction data of a video signal for the accumulated luminance value,
7. The display device according to claim 1, wherein correction data of the video signal with respect to the accumulated luminance value is recorded in the look-up table during a vertical blanking period of the video signal indicating the video. . The display device according to claim 1, wherein the cumulative calculation processing circuit calculates a cumulative luminance value of each pixel arranged in the display unit based on the luminance value corrected by the correction processing circuit.