JP2009269458A - Electric power steering device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric power steering device quickly and positively storing failure analysis data without increasing a processing load of software. <P>SOLUTION: In a normal state, a memory switching part 203 selects a first memory region 103a of a RAM 103 as a region used for normal processing, and when failure is detected by a failure detecting part 202, the memory switching part 203 switches to a second memory region 103b of the RAM 103 as a region used for normal processing, and sets the first memory region 103a as a storage region of the failure analysis data. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electric power steering apparatus, and more particularly to an electric power steering apparatus that records failure analysis data of the electric power steering apparatus.

  In order to reduce the steering force of vehicles such as passenger cars and trucks, there is a so-called electric power steering (EPS) device that assists steering by a steering assist motor. In the electric power steering apparatus, the driving force of the steering assist motor is applied to the steering shaft or the rack shaft by a transmission mechanism such as a gear or a belt via a speed reducer. Such an electric power steering apparatus performs feedback control of motor current in order to accurately generate steering assist torque. In feedback control, the motor applied voltage is adjusted so that the difference between the current command value and the detected motor current value is small. Generally, the adjustment of the motor applied voltage is a duty ratio of PWM (pulse width modulation) control. It is done by adjusting.

  In the electric power steering apparatus, various data are generated in the drive control, and necessary data is recorded in a nonvolatile memory provided in the electric power steering apparatus. As a technique related to data recording in such an electric power steering apparatus, for example, when a storage memory is configured by an overwriting memory and a non-volatile memory for permanent storage, and the data size exceeds a set range, that is, Proposed to store data useful for analysis of abnormalities and failures over a long period of time by adding additional storage to non-volatile memory for permanent storage only when there is a high possibility that some abnormality has occurred (For example, refer to Patent Document 1).

  As described above, in the conventional electric power steering device, when a failure occurs, failure analysis data (failure record data) is automatically stored in the nonvolatile memory in the electric power steering device. ing. Such failure analysis data is also called freeze frame data, and when an electronic control device fails for some reason, in order to make it easier to analyze the cause of the failure, software input / output signals and control algorithm calculation process This is the information that stores the data.

  However, since the failure analysis data needs to be saved at high speed and with certainty, it must be processed with priority even if other software functions are temporarily stopped. For this reason, there is a problem that the processing load of the entire software increases rapidly and reaches the maximum level.

  FIG. 8 is a diagram for explaining a conventional method for storing failure analysis data when a failure is detected. In the figure, reference numeral 301 denotes a reference memory, and 302 denotes a failure analysis memory. The reference memory 302 temporarily stores data detected by a sensor, CPU calculation result data, and the like. When a failure is detected, the data stored in the reference memory 301 is copied to the failure analysis memory 302. In this case, as the amount of data increases, the entire process is locked for a longer period, and thus the load increases inevitably. In the conventional method, if the copy element is about 10 to 20 bytes, the processing load is not so large, but if it is about several hundred bytes, a system problem may occur due to the real-time property of the software and the processing load.

  FIG. 9 is a timing chart for explaining the prior art of the software processing load at the time of failure detection. In the figure, a case will be described in which Tasks (tasks) 1 to 4 are executed within a predetermined period T1 and failure analysis data storage processing is incorporated in Task2.

  In the figure, conventionally, when failure analysis data is stored, for example, when a failure is detected by the failure diagnosis function of Task 2 at time t1, failure analysis data storage processing is started at time t2. At time t3, the failure analysis data storage process ends. In this case, the conventional method requires a long time T2 for the storage process of the failure analysis data. For this reason, the processing load of Task 2 increases, and the subsequent processes (Task 3, Task 4) cannot be processed at the designed timing. Therefore, Task 1 is started / started at the specified timing due to the delay of the processing of Task 3, 4. A situation that cannot be handled may occur. As a result, there is a possibility that the steering assist process (hereinafter referred to as “assist process”) fails and develops to assist stop because the process cannot be performed at the designed timing.

JP 2000-337977 A

  The present invention has been made in view of the above problems, and an object of the present invention is to provide an electric power steering device capable of storing failure analysis data quickly and reliably without increasing the software processing load. And

  In order to solve the above-described problems and achieve the object, the present invention provides a steering assist command value calculated based on the steering torque generated in the steering system of the vehicle and the speed of the vehicle, and the steering assist force in the steering system. In the electric power steering apparatus for controlling the steering assist motor based on the detected current value of the steering assist motor for providing the control, the control means for controlling the steering assist motor, and a work area for the control means, Random access memory for storing data, calculation results of the control means, and the like, and failure detection means for detecting a failure of the electric power steering, the random access memory has at least two memory areas, When one memory area is used for normal processing and an abnormality is detected by the failure detection means, Switch to a region using a memory area in the normal process, characterized by a storage area of the data failure analysis of the one memory area.

  Further, according to a preferred aspect of the present invention, the switching between the two memory areas is performed by an index system in which memory areas are arrayed and addressed, an offset system in which a predetermined value is added to or subtracted from a fixed address, or a physical area It is desirable to use a bank method for selecting a memory area.

  According to a preferred aspect of the present invention, there is provided a non-volatile storage unit for recording the failure analysis data, and the control unit stores the failure analysis data stored in the random access memory in a free time. It is desirable to store in the non-volatile storage means.

  According to a preferred aspect of the present invention, each time a failure is detected by the failure detection means, the normal processing area and the failure analysis data storage area are divided into the one memory area and the other memory area. It is desirable to switch alternately.

  According to the present invention, the steering assist command value calculated based on the steering torque generated in the steering system of the vehicle and the speed of the vehicle, and the current detection value of the steering assist motor that applies the steering assist force to the steering system. On the basis of this, in the electric power steering apparatus for controlling the steering assist motor, the control means for controlling the steering assist motor and the work area of the control means are used to store sensor data, the calculation result of the control means, etc. Random access memory and failure detection means for detecting a failure of the electric power steering, the random access memory has at least two memory areas, one memory area is used for normal processing, If an error is detected by the failure detection means, the other memory area is set as an area used for normal processing. In addition, since the one memory area is used as a storage area for failure analysis data, electric power that can quickly and reliably store failure analysis data without increasing the software processing load. There is an effect that a steering device can be provided.

  Embodiments of an electric power steering apparatus according to the present invention will be described below in detail with reference to the drawings. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably.

  FIG. 1 is a diagram illustrating a general configuration of an electric power steering apparatus. In FIG. 1, a column shaft 2 of a steering handle 1 is connected to a tie rod 6 of a steering wheel via a reduction gear 3, universal joints 4a and 4b, and a pinion rack mechanism 5. The column shaft 2 is provided with a torque sensor 10 that detects the steering torque T of the steering handle 1, and a steering assist motor 20 that assists the steering force of the steering handle 1 is connected to the column shaft via the reduction gear 3. 2 is connected. Here, the steering assist motor 20 is, for example, a brushless motor or a brush motor. The control unit 30 that controls the electric power steering device is supplied with electric power from the battery 14 via the built-in power supply relay 13 and is supplied with an ignition signal from the ignition key 11. Further, the control unit 30 calculates a current command value for the steering assist motor 20 based on the steering torque T detected by the torque sensor 10 and the vehicle speed V detected by the vehicle speed sensor 12, and the current of the steering assist motor 20 is calculated. Based on the detected value and the current command value, the steering assist motor 20 is drive-controlled so that the current detected value of the steering assist motor 20 follows the current command value.

  FIG. 2 is a diagram showing a hardware configuration of the control unit 30 of FIG. As shown in FIG. 2, the control unit 30 includes an MCU (micro control unit) 100, an FET pre-driver circuit 110, a motor drive circuit (inverter) 120, a current detection circuit 130, a position detection circuit 140, and the like. ing.

  The MCU 100 includes a CPU (control means) 101, a ROM 102, a RAM 103, an EEPROM (nonvolatile memory) 104, an A / D converter 105, an interface 106, a bus 107, and the like. The CPU 101 executes a program stored in the ROM 102 and controls the electric power steering apparatus.

  The ROM 102 stores various programs executed by the CPU 101. Specifically, the ROM 102 includes a program for executing an assist process (steering assist process) for controlling the steering assist motor 20 that performs steering assist (assist), and a failure detection for detecting a malfunction of the electric power steering apparatus. A program for executing processing, a program for executing processing for saving failure analysis data when a failure is detected, and the like are stored.

  The RAM 103 is used as a work area when the CPU 101 executes a program, and is necessary for sensor data (steering torque T, vehicle speed V, current detection value Im of the steering assist motor 20, motor rotation angle signal θ, etc.) and processing steps. And data such as processing results are temporarily stored. The RAM 103 includes a first memory area 103a and a second memory area 103b, and its use is switched when a failure is detected, as will be described later (see FIGS. 3 to 7).

  The EEPROM 104 is a non-volatile memory that can retain stored contents even after the power is shut off, and stores control data, failure analysis data, and the like that are used by the CPU 101 to control the electric power steering apparatus. Here, the EEPROM is used as the non-volatile memory. However, the present invention is not limited to this, and other non-volatile memories such as a FLASH-ROM may be used.

  The A / D converter 105 inputs the steering torque T from the torque sensor 10, the current detection value Im of the steering assist motor 20 from the current detection circuit 130, the motor rotation angle signal θ from the position detection circuit 140, and the like. Convert to digital signal. The interface 106 is for receiving the vehicle speed V (pulse) from the vehicle speed sensor 12 by CAN communication.

  In the above configuration, the CPU 101 functions as a failure detection unit and a memory switching unit by executing a program stored in the ROM 102.

  The FET pre-driver circuit 110 converts the PWM control signal for each phase of UVW input from the main MCU 100 into positive and negative energization signals (Up, Un, Vp, Vn, Wp, Wn) for each phase, and the motor drive circuit 120. Output to.

  The motor drive circuit 120 includes a bridge circuit composed of a pair of FET switching elements for three phases for the U phase, the V phase, and the W phase, and a reflux diode is connected in parallel to each FET switching element. A DC voltage is applied to the bridge circuit from the battery 14 via the power relay 13. An energization signal is input from the FET pre-driver circuit 110 to the control terminal (gate terminal) of each FET switching element. The DC voltage applied to the motor drive circuit 120 is converted into a three-phase AC voltage by the switching operation of the FET switching element in the motor drive circuit 120, thereby driving the steering assist motor 20. Shunt resistors R1 and R2 are connected to this bridge circuit. A current detection circuit 130 is connected to the shunt resistors R1 and R2, and the current detection value Im of the steering assist motor 20 is thereby detected.

  The position detection circuit 140 outputs the output signal from the position sensor 21 to the A / D converter 105 as a motor rotation angle signal θ.

  Next, with reference to FIG. 3 to FIG. 7, processing for storing failure analysis data when a failure is detected will be described. In this embodiment, the CPU 101 uses the first area 103a of the RAM 103 for normal processing in a normal state. In the normal processing, when the CPU 101 executes assist processing or the like, reading (R) / writing (R) / writing of sensor data, data required in the processing process, and data such as processing results with respect to the first area 103a ( W) is performed. When a failure is detected, the second memory area 103b is switched to an area used for normal processing, and the first memory area 103a is switched to a storage area for failure analysis data, so that the CPU 101 (software) Failure analysis data is quickly and reliably stored without increasing the processing load.

  FIG. 3 is a functional configuration diagram of the MCU 100 related to the failure analysis data storage process. In the figure, the MCU 100 includes a control unit 201 that executes assist processing and the like, a failure detection unit 202 that detects a failure based on sensor data, and a first memory area 103a and a second memory area 103b of the RAM 103. A memory switching unit 203 for switching is provided.

  The failure detection unit 202 detects a failure of the electric power steering device based on the sensor data, and outputs a failure detection signal to the memory switching unit 203 when a failure is detected. Here, the failure is detected based on the sensor data, but the failure detection is not limited to the failure detection based on the sensor data, and a failure of the memory (ROM 102, EEPROM 104), CPU 101, etc. may be detected. .

  When performing normal processing, the control unit 201 reads (R) / writes (W) sensor data, data required in the processing process, and data such as processing results with respect to the RAM 103.

  The memory switching unit 203 switches between the first memory region 103a and the second memory region 103b of the RAM 103 based on the failure detection signal input from the failure detection unit 202. As a memory access method when switching between the first and second memory areas 103a and 103b, for example, an index method in which memory areas are arrayed and addressed, and an offset method in which a predetermined value is added to or subtracted from a fixed address Alternatively, a bank method for selecting a physical memory area or the like can be used. An embodiment in which the index method is used will be described later (see FIGS. 6-1 to 6-6).

  FIG. 4 is a schematic diagram for explaining switching of the memory area of the memory switching unit 203. In the figure, the memory switching unit 203 selects the first memory area 103a in the normal state. The control unit 103 performs normal processing using the first memory area 103a (S1). That is, the first memory area 103a is used as a simple data transfer area.

  When a failure is detected by the failure detection unit 202 and a failure detection signal is input, the memory switching unit 203 switches the region where normal processing is performed to the second memory region 103b. The control unit 103 performs normal processing using the second memory area 103b (S2). In the first memory area 103a, data is not updated, and data at the time of failure stored in the first memory area 103a is stored in the EEPROM 104 as failure analysis data in the free time of the control unit 201 or the like. Thereby, even if the power of the control unit 30 is turned off, the failure analysis data can be confirmed later.

  After a failure is minor and recovered by fail-safe processing, if a failure is further detected, the area for normal processing is switched to the first memory area 103a. The control unit 103 performs normal processing using the first memory area 103a (S3). In the second memory area 103b, the data is not updated, and the data at the time of the failure occurrence stored in the second memory area 103b is stored in the EEPROM 104 as the failure analysis data in the free time of the control unit 201. If a failure is further detected after the recovery, the second memory area 103 is switched to an area where normal processing is performed, and the first memory area 103a is switched to a storage area for failure analysis data (S2). In this way, every time a failure is detected, the failure analysis is performed by alternately switching the normal processing region and the failure analysis data storage region between the first memory region 103a and the second memory region 103b. It is possible to repeatedly store data for use. Further, by storing the failure analysis data in the EEPROM 104 during the idle time of the control unit 201, the processing load on the control unit 201 can be reduced.

  FIG. 5 is a flowchart for explaining the outline of the operation of the MCU 100 of FIG. With reference to FIG. 5, the outline of the operation of the MCU 100 of FIG. 3 will be described. In the figure, first, when the IG is turned on (step S11), an initial diagnosis is executed (step S12). After completion of the initial diagnosis, the sensor data is input to the failure detection unit 202 and stored in the first memory area 103a of the RAM 103 (step S13). The failure detection unit 202 detects a failure based on the sensor data (step S14). The failure detection unit 202 determines whether or not a failure has been detected (step S15). If no failure is detected by the failure diagnosis unit 202 ("No" in step S15), the control unit 201 determines whether the failure is detected in the first RAM1. The memory area 103 is used to perform normal processing, control calculation is performed (step S16), and a current command value for the steering assist motor 20 is output (step S17). If the IG is not turned off (“No” in step S18), the process returns to step S13. If the IG is turned off (“Yes” in step S18), the steering assist motor 20 is stopped. The predetermined stop process is performed (step S19), and the flow ends.

  On the other hand, if a failure is detected by the failure detection unit 202 in step S15 (“Yes” in step S15), the failure analysis data storage process described above is performed (step S20), and then a fail-safe process is performed (step S20). Step S21). In the fail-safe process, if the failure is minor, a recovery process is performed, and the process proceeds to step S16. On the other hand, when the failure is serious, a predetermined stop process for stopping the steering assist motor 20 is performed.

  Next, referring to FIGS. 6-1 to 6-5, in the failure analysis data saving process described above, the memory switching unit 203 uses the index method to store the first memory area 103a and the second memory area 103 in the RAM 103. An example in which the memory area 103b is switched will be described.

  In FIG. 6A, a plurality of memory spaces having the same configuration are created by pseudo-multidimensionally arranging an address space that is originally a one-dimensional array, and these arrays are switched at high speed by an index, and read / write is performed. The RAM 103 is configured so that it can be accessed. Mem [0], Mem [1], WriteIndex, and ReadIndex are prepared (in the following description, the first area 103a is Mem [0] = M0, the second area 103b is Mem [1] = M1, WriteIndex = WI, ReadIndex = RI.

  In the initial state, WI = 0 and RI = 0 are set, and the memory spaces of M0 and M1 are initialized with appropriate values. Access of Mem [0] and Mem [1] can be switched according to the values set in WI and RI.

  As shown in FIG. 6B, when failure analysis data is not stored (normal state), WI = 0 and RI = 0 are set, and M0 is set as a simple data transfer area.

  As shown in FIG. 6-3, when the failure analysis data is stored (when a failure is detected by the failure detection unit 202), first, WI = 1 and RI = 0 are set, and switching to M1 data update is performed. , M0 data is held. If there is no high priority processing even in the failure analysis data storage processing, WI and RI may be switched simultaneously.

  As shown in FIG. 6-4, WI = 1 and RI = 1 are set, and M1 is a simple data transfer area. Thereby, M0 is not updated, and acquisition of failure analysis data is completed in M0. The failure analysis data acquired in M0 is saved in the EEPROM 104 by a predetermined method during the idle time of the control unit 201, so that the failure analysis data is confirmed later even if the control unit 30 is turned off once. It becomes possible.

  When failure analysis data is repeatedly stored, for example, when failure detection → failure analysis data storage → return before failure determination → failure detection → failure analysis data storage, as shown in FIG. If WI and RI are changed, the latest failure analysis data can be easily acquired any number of times. In the figure, first, (1) WI = 0 and RI = 0 are set, and M0 is set as a simple data transfer area. (2) When a failure is detected by the failure detection unit 202, WI = 1 and RI = 0 are set, the data is switched to M1 data update, and the data of M0 is held. The data held in M0 is stored in the EEPROM 104 while the control unit 201 is idle. Thereafter, (3) and (4) WI = 1 and RI = 1 are set, and M1 is set as a simple data transfer area. While the processing of the control unit 201 is idle, the data written to M0 is stored in the EEPROM 104.

  Next, after returning before the failure is confirmed, (5) when the failure is detected by the failure detection unit 202, WI = 0 and RI = 1 are set, the data is updated to M0, and the data of M1 is held. To do. Note that the data held in M0 is stored in the EEPROM 104 during the idle time of the control unit 101. (6) WI = 0 and RI = 0 are set, and the first area M0 is set as a simple data transfer area. Thereafter, when an abnormality is detected, the process returns to (1). The latest failure analysis data can be acquired any number of times simply by switching between M0 and M1.

  As described above, a large amount of failure analysis data can be stored at high speed and reliably only by manipulating the two index variables WI and RI. If this method is used, the effect increases as the number of elements of the failure analysis data increases. Depending on the timing of periodic input / output, the purpose can be achieved even if a plurality of indexes for array access are operated simultaneously. Further, depending on the timing of periodic input / output, even one index for array access can sufficiently fulfill its purpose.

  FIG. 7 is a timing chart for explaining the processing load of the CPU 101 (software) when a failure is detected in this embodiment. In the figure, a case will be described in which Tasks (tasks) 1 to 4 are executed within a predetermined period T1 and failure analysis data storage processing is incorporated in Task2.

  In the figure, when failure analysis data is stored, for example, when a failure is detected by the failure detection function of Task 2 at time t1, failure analysis data storage processing is started at time t2, and time t3 This completes the failure analysis data storage process. In this case, in this embodiment, since only the first and second memory areas 103a and 103b of the RAM 103 are switched, conventionally, the storage process of the failure analysis data requires a long time T2 (see FIG. 9). However, in this embodiment, a short period of T3 is sufficient, and subsequent processing (Task3, Task4) can be processed at the timing as designed. In other words, failure analysis data can be stored quickly and reliably without increasing the software processing load, and can be processed at the timing as designed. Therefore, the original diagnosis / control effect can be exhibited.

  As described above, according to the present embodiment, the control unit 201 that controls the steering assist motor 20 and the work area of the control unit 201 are used to store the sensor data, the calculation result, and the like. RAM 103 having a region 103a and a second memory region 103b, a failure detection unit 202 for detecting a failure of the electric power steering device, and in a normal state, the first memory region 103a is selected as a region used for normal processing, When a failure is detected by the failure detection unit 202, the memory switching unit 203 switches the second memory area 103b to an area used for normal processing, and uses the first memory area 103a as a storage area for failure analysis data. With this feature, failure analysis data can be saved quickly and reliably without increasing the processing load on the software (CPU). It becomes possible.

  Further, the memory switching unit 203 switches between the first and second memory areas 103a and 103b by using an index system in which memory areas are arrayed and addressed, an offset system in which a predetermined value is added to or subtracted from a fixed address, or Since the bank method for selecting a physical memory area is used, the first and second memory areas 103a and 103b can be switched by a simple method.

  In addition, since the EEPROM 104 for recording the failure analysis data is provided and the failure analysis data stored in the RAM 103 is stored in the EEPROM 104 during the idle time of the control unit 202, the processing load of the software (CPU) is reduced. It is possible to permanently store failure analysis data without increasing it.

  Each time the failure detection unit 202 detects a failure, the normal processing region and the failure analysis data storage region are alternately switched between the first memory region 103a and the second memory region 103b. As a result, failure analysis data can be stored repeatedly.

  In the above embodiment, the area of the RAM 103 is divided into two areas. However, the number of areas to be divided is not limited to this, and may be divided into three or more areas.

  Further, although the failure detection processing is executed by the CPU 101, a device for performing failure detection may be provided separately.

  The electric power steering apparatus according to the present invention is useful when storing failure analysis data.

It is a figure which shows the general structure of an electric power steering apparatus. It is a figure which shows the hardware constitutions of the control unit of FIG. It is a functional block diagram of MCU regarding the preservation | save process and assist process of the data for failure analysis. It is a schematic diagram for demonstrating switching of the memory area of RAM in a memory switching part. It is a flowchart for demonstrating the outline of operation | movement of an electric power steering apparatus. It is explanatory drawing (the 1) for demonstrating an Example in case a memory switching part switches the memory area of RAM using an index system. It is explanatory drawing (the 2) for demonstrating an Example in case a memory switching part switches the memory area of RAM using an index system. It is explanatory drawing (the 3) for demonstrating an Example in case a memory switching part switches the memory area of RAM using an index system. It is explanatory drawing (the 4) for demonstrating an Example in case a memory switching part switches the memory area of RAM using an index system. It is explanatory drawing (the 5) for demonstrating an Example in case a memory switching part switches the memory area of RAM using an index system. It is a timing chart for demonstrating the processing load of the software in the data storage process for failure analysis at the time of the failure detection of a present Example. It is a figure for demonstrating the data storage method for failure analysis at the time of the conventional failure detection. It is a timing chart for demonstrating the processing load of the software in the data storage for failure analysis at the time of the conventional failure detection.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Steering handle 2 Column shaft 3 Reduction gear 4a, 4b Universal joint 5 Pinion rack mechanism 6 Tie rod 10 Torque sensor 12 Vehicle speed sensor 14 Battery 20 Steering auxiliary motor 30 Control unit 100 MCU (micro control unit)
101 CPU (control means)
102 ROM
103 RAM
103a first memory area 103b second memory area 104 EEPROM
105 A / D converter 106 Interface 107 Bus 110 FET pre-driver circuit 120 Motor drive circuit (inverter)
130 current detection circuit 140 position detection circuit

Claims (4)

Based on the steering assist command value calculated based on the steering torque generated in the steering system of the vehicle and the speed of the vehicle, and the current detection value of the steering assist motor that applies the steering assist force to the steering system, the steering assist In the electric power steering device for controlling the motor,
Control means for controlling the steering assist motor;
Random access memory that is used as a work area of the control means, and stores sensor data, calculation results of the control means, and the like,
A failure detecting means for detecting a failure of the electric power steering device;
With
The random access memory has at least two memory areas, and one memory area is used for normal processing, and when a failure is detected by the failure detection means, the other memory area is used for normal processing. The electric power steering apparatus according to claim 1, wherein the memory area is switched to an area and the one memory area is used as a storage area for failure analysis data.   The switching between the two memory areas is performed by an index system in which memory areas are defined and addressed, an offset system in which a predetermined value is added to or subtracted from a fixed address, or a bank system in which a physical memory area is selected. The electric power steering apparatus according to claim 1, wherein the electric power steering apparatus is characterized. Non-volatile storage means for recording the failure analysis data,
3. The electric power steering apparatus according to claim 1, wherein the control unit stores the failure analysis data stored in the random access memory in the non-volatile storage unit during an idle time. .   Each time a failure is detected by the failure detection means, a normal processing region and a failure analysis data storage region are alternately switched between the one memory region and the other memory region. The electric power steering apparatus according to any one of claims 1 to 3.

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