JP2009268004A - Impedance conversion circuit, high-frequency circuit, and impedance conversion characteristic adjusting method for impedance conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To configure an impedance conversion circuit which reversibly and finely adjust the characteristics of qn impedance conversion, without having to add a dielectric chip, or the like, or using an open stab having a long stab length, and a high-frequency circuit with the same. <P>SOLUTION: When the length of a stab ST1 is reduced, while the length of a stab ST2 is fixed, impedance Zb is moved on an admittance chart, in the direction represented by an arrow A1. Furthermore, when the length of the stab ST2 is reduced, while fixing the length of the stab ST1, the impedance Zb is moved on an equal conductance circuit on the admittance chart as shown representatively by an arrow A2. Hence, inside a circle with an interval between the center of a smith chart and a short-circuit point as a diameter, regarding an impedance track, impedance can be mutually adjusted reversibly by trimming the stabs ST1, ST2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an impedance conversion circuit such as an impedance matching circuit, an output circuit and a feedback circuit, and a high frequency circuit such as an amplifier circuit / multiplier circuit, a mixing circuit and an oscillation circuit provided with the same.

Conventionally, in a high-frequency circuit, an open stub is adjusted to adjust its characteristics.
Patent Document 1 discloses that an open stub for adjustment is provided in an output circuit section of a high-frequency oscillation circuit. The high-frequency oscillation circuit disclosed in Patent Document 1 will be described with reference to FIG.

  As shown in FIG. 1, in the high-frequency oscillation circuit 100, the gate end of the FET 9 is connected to a line 7 composed of a microstrip line whose one end is grounded through a resistor 8. A dielectric resonator 3 is coupled to a predetermined position of the line 7. A line 20 having one end opened is coupled to the dielectric resonator 3. A variable capacitance diode 4 is connected between the line 20 and the ground, and a resistor 5 is connected between the control voltage input terminal 6 and the line 20.

  The source of the FET 9 is grounded through one of the coupled lines 11. An attenuator 12 is provided between the other line of the coupled line 11 and the output terminal 13. An open stub 10 is connected to the source of the FET 9.

Connected between the drain of the FET 9 and the drain bias terminal 19 are a line 15 having a line length of approximately λ / 4, an open stub 16 having a line length of approximately λ / 4, and a resistor 17. The drain bias terminal 19 is grounded via a capacitor 18. These circuit portions constitute a drain bias circuit. An adjustment open stub 14 having a line length of about λ / 4 is connected to the drain of the FET 9.
JP 2006-42010 A

  As described above, in the high-frequency oscillation circuit disclosed in Patent Document 1, an open stub 14 for adjustment having a line length of approximately ¼ wavelength is provided at the drain end of the FET, and the open stub 14 is trimmed. Can raise the oscillation frequency. However, in order to lower the oscillation frequency, a dielectric chip must be disposed at the open end of the adjustment open stub 14, which increases the circuit area. In addition, new work such as mounting a dielectric chip using a mounter is required.

  If the length of the open stub is set to ½ wavelength or more in advance so that there are two or more points where the reflection phase is the same in the middle of the cut of the open stub, if the trimming amount is excessive, Although there is an opportunity to match the stub length with which desired characteristics can be obtained, the circuit board becomes larger correspondingly. Moreover, fine adjustment in the reverse direction is not possible. Further, as the stub length is longer, the line loss becomes larger and the output voltage is lowered, and a portion having a gain is generated in a low frequency band, and the possibility of causing parasitic oscillation is increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an impedance conversion circuit that is capable of reversibly and finely adjusting impedance conversion characteristics without adding a dielectric chip or the like, a high-frequency circuit including the impedance conversion circuit, and an impedance conversion circuit An object of the present invention is to provide a method for adjusting impedance conversion characteristics.

In order to solve the above problems, the present invention is configured as follows.
(1) An impedance conversion circuit connected between an input terminal or an output terminal and an active element,
First and second open stubs;
A circuit element that is a line or an inductance element connected in series between a connection point of the first open stub and a connection point of the second open stub,
The first and second open stubs are arranged so that the impedance viewed from the connection point of one of the first and second open stubs falls within a circle whose diameter is the center of the Smith chart and the short point. The stub length and circuit element constant / size are defined.

  Thereby, the frequency characteristic can be reversibly adjusted by a simple method of cutting (trimming) an open stub.

(2) The impedance viewed from the connection point of one of the first and second open stubs is lower than the impedance of the circuit connected to the input terminal or the output terminal, and is substantially pure resistance. The lengths of the first and second open stubs and the constants and sizes of the circuit elements are determined.

  In this way, in the region where the impedance is lower than the impedance of the circuit connected to the input terminal or the output terminal and becomes substantially pure resistance, the locus of the impedance when the two open stubs are cut is almost in the opposite direction. Reversible adjustment becomes possible.

(3) The first open stub and the second open stub are capacitive open stubs.

  As a result, the π-type circuit composed of the first and second open stubs and the circuit elements becomes a low-pass filter, so that the connection point of one open stub of the first and second open stubs can be simplified. The impedance seen from the circuit can be made lower than the impedance of the circuit connected to the input terminal or the output terminal.

(4) The circuit element is constituted by a line having a length of about 1/8 wavelength at a desired frequency, for example.
As a result, at the desired frequency, the impedance viewed from the connection point of one of the first and second open stubs can be made substantially pure.

(5) The first open stub and the second open stub are, for example, open stubs whose line length is less than ¼ wavelength.
Thereby, the adjustment range which can be reversibly adjusted can be widened, without increasing the occupation area of an open stub formation part.

(6) The circuit element is composed of, for example, a chip capacitor whose impedance is inductive at the frequency to be transmitted.
Thereby, by making a circuit element into a capacitor | condenser, it can serve as a cut of DC component.

(7) If necessary, a phase adjustment line is provided between the output terminal and the first open stub or between the second open stub and the active element.
Thereby, while adjusting to a predetermined phase, the impedance can be reversibly adjusted.

(8) A high frequency circuit is configured by including at least one active element and providing the impedance conversion circuit between at least one terminal of the active element and the input terminal and / or the output terminal.
Thereby, the frequency characteristic adjustment of the high frequency circuit can be adjusted with high accuracy and high efficiency.

(9) A method for adjusting impedance conversion characteristics of an impedance conversion circuit connected between an input terminal or an output terminal and an active element,
A line or an inductance element connected in series between the first and second open stubs and a connection point of the first open stub and a connection point of the second open stub to the impedance conversion circuit. A circuit element,
The first and second open stubs are arranged so that the impedance viewed from the connection point of one of the first and second open stubs falls within a circle whose diameter is the center of the Smith chart and the short point. The length of the stub and the constant / size of the circuit element are determined (by trimming the stub), thereby enabling reversible adjustment.

  According to the present invention, the frequency characteristic can be reversibly adjusted by a simple method of cutting an open stub. In addition, a high-frequency circuit having desired frequency characteristics can be obtained efficiently.

<< First Embodiment >>
The impedance conversion circuit according to the first embodiment and the method for adjusting the impedance conversion characteristic will be described with reference to FIGS.
FIG. 4A is a circuit diagram of the impedance conversion circuit 30. The impedance conversion circuit 30 includes a line SL1 corresponding to a “circuit element” according to the present invention between a connection point of a first open stub (hereinafter simply referred to as a stub) ST1 and a connection point of a second stub ST2. Are connected in series to form a π-type.

  The characteristic changes when the lengths of the first stub ST1, the second stub ST2, and the line SL1 of the impedance conversion circuit 30 are changed will be described in order.

  FIG. 2 shows a Smith chart (generally including an admittance chart and an impedance chart) when the line length of the line SL1 is changed from 0 to ¼ wavelength (hereinafter, the wavelength is represented by λ). It can also be referred to as an “immittance chart.” In this case, since it is a chart focusing on admittance, it is a diagram showing how the impedance changes in the following “admittance chart”).

  FIG. 2A shows the impedance Za as seen from the connection point of the stub ST2 of the impedance conversion circuit 30 in the direction of the terminal T1.

  2B and 2C show how the impedance changes on the admittance chart when the line length of the line SL1 is changed from 0 to λ / 4.

  In the example shown in FIG. 2B, both ends of the circuit are terminated by 50Ω terminators Z1 and Z2. The stub ST1 is fixed with a characteristic impedance Zc = 50Ω and a length L = λ / 8, the line SL1 has a width W = 0.42 mm, and the length L is changed from 0 to λ / 4.

  When the length L of the line SL1 is 0, the impedance Za at a frequency of 24 GHz viewed from the broken line shown in FIG. 2A is represented by a point P0 in FIG.

  When the length L of the line SL1 is sequentially increased, the point moves as shown by an arrow in FIG. 2C, and when the length L of the line SL1 is λ / 8, the impedance is represented by the point P1. The When the length L of the line SL1 is λ / 4, the impedance is represented by a point P2. Since the length of the line SL1 changes only the phase of the propagating signal, this impedance locus is an arc centered on the center O of the admittance chart.

  FIG. 3 is a diagram showing how the impedance changes on the admittance chart when the length L of the stub ST1 is changed from λ / 4 to 0.

  FIG. 3A shows the impedance Za as seen from the connection point of the stub ST2 of the impedance conversion circuit 30 in the direction of the terminal T1, as in FIG.

  3B and 3C show how the impedance changes on the admittance chart when the length of the stub ST2 is changed from λ / 4 to 0. FIG.

  As shown in FIG. 3B, at this time, the length L of the line SL1 is fixed to λ / 8 in the 24 GHz band. When the length L of the stub ST1 = λ / 4, the impedance Za is represented by a point P2 in FIG. When the length L of the stub ST1 is L = λ / 8, the impedance Za is represented by a point P1 in FIG. Further, assuming that the length L of ST1 is 0, the impedance Za is represented by a point P0.

  Such an impedance locus is obtained by rotating a locus on an isoconductance circle caused by a change in the length of the stub ST1 by a phase corresponding to the length of the line SL1.

  FIG. 4 is a diagram showing how the impedance changes depending on the length of the stubs ST1 and ST2 of the impedance conversion circuit 30. As shown in FIG.

  4A shows the impedance Zb when the right side is viewed from the broken line including the stub ST2 of the impedance conversion circuit 30. FIG.

  FIGS. 4B and 4C show the impedance on the admittance chart when the length of the stub ST1 is changed from λ / 4 to 0 and the length of the stub ST2 is changed from λ / 8 to 0. How it changes.

  As shown in FIG. 4B, the length of the line SL1 is fixed at λ / 8 in the L24 GHz band, and the length L of the stubs ST1 and ST2 is changed in the range from λ / 4 to 0, respectively.

  When the length of the stub ST1 is λ / 4 and the length of the stub ST2 is λ / 8, the impedance Zb is represented by a point P20 in FIG. When the length of the stub ST2 is shortened while the length of the stub ST1 is λ / 4, the impedance Zb moves counterclockwise on the isoconductance circle, and when the length of the stub ST2 is shortened to 0, the impedance Zb is represented by a point P2 in FIG.

  When the length of the stub ST1 is λ / 8 and the length of the stub ST2 is λ / 8, the impedance Zb is represented by a point P10 in FIG. 4C. When the length of the stub ST2 is set to 0 while the length of the stub ST1 is λ / 8, the impedance Zb moves to a position indicated by a point P1 in FIG.

  When the length of the stub ST1 is 0 and the length of the stub ST2 is λ / 8, the impedance Zb is represented by a point P00 in FIG. If the length of the stub ST2 is shortened to 0 while the length of the stub ST1 is 0, the impedance Zb moves to a point P0 in FIG.

  As described above, when the length of the stub ST2 is shortened, the impedance Zb rotates counterclockwise on the equiconductance circle as shown by the arrow A2 in FIG. 4C.

  Further, when the length of the stub ST1 is shortened, the impedance Zb moves in a direction indicated by an arrow A1 represented in FIG. Therefore, in the region indicated by a broken line, particularly an ellipse, the impedances change in substantially opposite directions due to the trimming of the stubs ST1 and ST2.

  FIG. 5 shows the range in which the impedance can be adjusted reversibly. The impedance viewed from the connection point of the open stub ST2 moves due to the trimming of the stubs ST1 and ST2. As is apparent from the locus of the impedance, the line connecting the center O of the admittance chart and the short point S is the diameter. If the impedance viewed from the connection point of the open stub ST2 is included in the circle C, the impedance conversion characteristic adjustment can be performed reversibly. Therefore, the length of the stubs ST1 and ST2 and the constant and size of the line SL1 may be determined so that the impedance viewed from the connection point of the open stub ST2 falls within the circle C.

  More preferably, the length of the first stub ST1 and the second stub ST2 and the constant and size of the line SL1 are determined so as to be lower than the impedance of the circuit connected to the terminal T1 and to have a substantially pure resistance. Thereby, since the locus | trajectory of the impedance at the time of cutting two open stubs becomes a reverse direction, ideal reversible adjustment is attained.

  Specifically, if the first stub ST1 and the second stub ST2 are capacitive, it is possible to easily achieve an impedance lower than the impedance of the circuit connected to the terminal T1, and the length of the line SL1 is 24 GHz. In the case of λ / 8, substantially pure resistance can be obtained. If the lengths of the first stub ST1 and the second stub ST2 are less than λ / 4, the area occupied by the open stub forming portion can be reduced.

<< Second Embodiment >>
FIG. 6 is a circuit diagram of a high-frequency oscillation circuit according to the second embodiment. The high-frequency oscillation circuit 101 includes a resonance circuit 1 and an amplification (feedback) circuit 2.

  The resonant circuit 1 includes a line SL4, a dielectric resonator DR coupled to the line SL4, and a line SL5 coupled to the dielectric resonator DR. The end of the line SL4 is terminated with a resistor R2. A variable capacitance diode VD is connected to the line SL5, and a resistor R3 and a control voltage input terminal Vc are provided as a bias circuit.

  The amplifier circuit 2 includes an amplifier circuit using an active element FET Q1, an impedance conversion circuit 30, and an attenuator AT. A line SL3 as a feedback circuit is provided at the source of the FET Q1. A bias circuit including a resistor R1, an open stub ST3, a line SL2, and a bypass capacitor C2 is connected to the drain. A drain bias voltage is applied to the drain bias terminal Vd.

  The impedance conversion circuit 30 is the same as that shown in the first embodiment, and includes a first stub ST1, a second stub ST2, and a line SL1. An output signal from the drain of the FET Q1 is output from the output terminal T1 via the impedance conversion circuit 30, the DC cut capacitor C1, and the attenuator AT.

  The impedance conversion circuit 30 sees from the drain of the FET Q1 and transmits the part of the signal output from the drain of the FET Q1 and reflects the other impedance (phase, reflection intensity) to the resonance circuit 1 side. The impedance is converted so that it can be seen. That is, the impedance conversion circuit 30 can also be called a feedback circuit or an output circuit that adjusts reflection and transmission in a high-frequency oscillation circuit.

  FIG. 7 shows an example in which a chip capacitor is used instead of the line SL1 of the impedance conversion circuit 30 shown in FIG. As shown in FIG. 7A, in terms of direct current, the chip capacitor CC acts as a capacitor for cutting direct current, becomes inductive in a high frequency region exceeding the self-resonance frequency, and is predetermined as shown in FIG. 7B. Acts as an inductance element L1 for inductance. When the capacitance of the capacitor is sufficiently large, the equivalent inductance value of L1 depends substantially on the chip size regardless of the capacitance value.

  For example, if a chip capacitor of 0603 (600 μm × 300 μm) is used, this chip capacitor has an equivalent inductance value of about 0.5 nH on the printed circuit board. In combination with the mounting land, an equivalent role to a transmission line of about 0.8 to 1.0 mm can be obtained, so at a high frequency of about 10 to 30 GHz, two open stubs ST1 and ST2 and an equivalent provided therebetween The impedance of the π-type circuit consisting of inductance satisfies the condition that allows reversible adjustment. At a lower frequency, by providing transmission lines at both ends of the chip capacitor or using a capacitor having a large chip size, it is possible to appropriately select a condition allowing reversible adjustment. At higher frequencies, a 0402 (400 μm × 200 μm) size chip capacitor having a smaller parasitic inductance may be used. A 0402 size chip capacitor can be used up to about 40 GHz to 50 GHz.

  Therefore, if the chip capacitor CC is used in the line SL1 portion of the impedance conversion circuit 30, the DC cut capacitor C1 shown in FIG. 6 is not necessary. Accordingly, the number of parts can be reduced, and the printed circuit board can be reduced.

<< Third Embodiment >>
FIG. 8 is a circuit diagram of a multiplier according to the third embodiment. The multiplier 102 generates a harmonic signal of a predetermined order based on the fundamental wave input from the input terminal Ta, and outputs it to the output terminal Tb. An impedance conversion circuit 31 serving as a matching circuit is provided between the gate of the active element FET Q2 and the input terminal Ta. An impedance conversion circuit 32 as a matching circuit is provided between the drain of the FET Q2 and the output terminal Tb.

  The impedance conversion circuit 31 matches the impedance of the circuit on the input terminal Ta side with the impedance of the gate input portion of the FET Q1 at the frequency of the fundamental wave. The impedance conversion circuit 32 matches the impedance on the drain side of the FET Q2 with the impedance of the circuit connected to the output terminal Tb.

  The output section (FET Q2 side) of the impedance matching circuit 31 is provided with an open stub ST13 for harmonic reflection so that the harmonic signal is not transmitted to the input terminal Ta side. An open stub ST23 for reflecting the fundamental wave is provided on the input side (FET Q2 side) of the impedance conversion circuit 32 so that the fundamental wave signal does not pass to the output terminal Tb side.

Here, the operation of the impedance conversion circuit 32 for matching harmonic signals will be described with reference to FIG.
The impedance conversion circuit 32 shown in FIG. 8 is connected to the right side from the connection point of the stub ST22 (the impedance seen from the output terminal Tb side changes in the same manner as that of the first embodiment by trimming the stubs ST21 and ST22. In FIG. 9, the broken ellipse OA1 and arrows A1 and A2 indicate the operation.

  In FIG. 8, a line SL24 is a phase adjusting line. The impedance when the output terminal Tb side is viewed from the left side of the line SL24 rotates clockwise on the admittance chart for the phase of the line SL24. In FIG. 9, broken ellipses OA10 and arrows A11 and A12 represent such a state.

  In FIG. 9, the impedance locus ZC indicates the output reflection characteristic S (2, 2) of the FET Q2 when the frequency is changed. Here, a matching circuit at the frequency indicated by the marker M1 is considered as an example. In the small signal design, the impedance matching circuit is generally designed so that the impedance viewed from the drain of the FET Q2 is a complex conjugate with respect to M2, as indicated by a marker M2 in FIG. When the stub ST21 is trimmed in the impedance conversion circuit 32 shown in FIG. 8, the impedance when the right side is viewed from the drain of the FET Q2 rotates in the direction of the arrow A11. That is, it moves in a direction where matching can be achieved at a higher frequency. On the other hand, when the stub ST22 is trimmed, it rotates in the direction indicated by the arrow A12. That is, it moves in a direction where matching can be achieved at a lower frequency. In this way, by applying the impedance conversion circuit of the present invention to the output matching circuit section of the multiplier, the frequency at which the gain becomes maximum can be adjusted reversibly.

<< Fourth Embodiment >>
FIG. 10 is a circuit diagram of the mixer 103 according to the fourth embodiment. The mixer 103 mixes the local signal LO input from the input terminal Tc and the high frequency signal RF input from the input terminal Td, and outputs an intermediate frequency signal IF from the output terminal Te. An impedance conversion circuit 33 as an impedance matching circuit is provided on the path from the input terminal Tc to the gate of the FET Q3 which is an active element. An impedance conversion circuit 34 as an impedance matching circuit is provided on the path from the input terminal Td to the drain of the FET Q3.

  A bias circuit including lines SL42 and SL43 and a stub ST43 is connected to the drain of the FET Q3, and a circuit is configured to output the intermediate frequency signal IF through the capacitor Co.

  A drain bias voltage is applied to the bias terminal Vd, and a gate bias voltage is applied to the Vg.

  Thus, also in the mixer 103, the impedance conversion circuits 33 and 34 achieve impedance matching between the input terminals Tc and Td and the FET Q3. At that time, the input level of the impedance conversion circuit 33 changes according to the frequency of the local signal LO, and the input level of the impedance conversion circuit 34 changes according to the frequency of the RF signal. The configurations of the two impedance conversion circuits 33 and 34 are the same as those shown in the first embodiment, and two stubs and lines are configured in a π type. Therefore, the frequency characteristics of the impedance can be reversibly adjusted, and the frequency characteristics of the frequency conversion gain as the mixer can be reversibly adjusted by the frequency characteristics of these impedance conversion circuits 33 and 34.

<< Fifth Embodiment >>
FIG. 11 is a circuit diagram of the distributor 104 according to the fifth embodiment. The distributor 104 distributes the input signal from the input terminal Tf and outputs it to the output terminals Tg and Th.

  FETs Q4 and Q5, which are active elements, amplify the distributed signals, respectively, and output drain output signals via impedance conversion circuits 35 and 36, respectively. The configurations of the two impedance conversion circuits 35 and 36 are the same as those shown in the first embodiment, and two stubs and lines are configured in a π type. Therefore, the frequency characteristic of the impedance can be reversibly adjusted, and the distribution characteristic with respect to the frequency can be reversibly adjusted according to the frequency characteristics of the impedance conversion circuits 35 and 36.

1 is a circuit diagram of a high-frequency oscillation circuit disclosed in Patent Document 1. FIG. It is a figure showing how an impedance changes on an admittance chart when changing line length of line SL1 from 0 to ¼ wavelength. It is a figure which shows how an impedance changes on an admittance chart when the length L of stub ST1 is changed from (lambda) / 4 to 0. FIG. It is a figure which shows how an impedance changes with the length of stub ST1, ST2 of the impedance conversion circuit 30. FIG. It shows the range where the impedance can be reversibly adjusted. It is a circuit diagram of the high frequency oscillation circuit concerning a 2nd embodiment. FIG. 7 is a diagram illustrating an example in which a chip capacitor is used instead of the line SL1 of the impedance conversion circuit 30 illustrated in FIG. 6. It is a circuit diagram of the multiplier which concerns on 3rd Embodiment. It is a figure which shows the example of the impedance matching by the line | wire SL24 and the impedance conversion circuit 32 in FIG. It is a circuit diagram of the mixer 103 which concerns on 4th Embodiment. It is a circuit diagram of the divider | distributor 104 which concerns on 5th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Resonance circuit 2 ... Amplifier circuit 30-36 ... Impedance conversion circuit 100, 101 ... High frequency oscillation circuit 102 ... Multiplier 103 ... Mixer 104 ... Distributor AT ... Attenuator SL1 ... Line ST1, ST21, ST31, ST41, ST51, ST61: first open stubs ST2, ST22, ST32, ST42, ST52, ST62 ... second open stubs ST3, ST13, ST23, ST43 ... open stubs T1, T2 ... terminals Z1, Z2 ... terminator Q1 ... FET

Claims (9)

An impedance conversion circuit connected between an input terminal or an output terminal and an active element,
First and second open stubs;
A circuit element that is a line or an inductance element connected in series between a connection point of the first open stub and a connection point of the second open stub,
The first and second open stubs are arranged such that the impedance viewed from the connection point of one of the first and second open stubs falls within a circle whose diameter is the center of the Smith chart and the short point. An impedance conversion circuit characterized in that a stub length and circuit element constant / size are defined.   The first and second open stubs are arranged so that an impedance viewed from a connection point of one of the first and second open stubs is lower than an impedance of a circuit connected to the input terminal or the output terminal and is substantially pure resistance. An impedance conversion circuit characterized in that a length of a second open stub and a constant / size of a circuit element are determined.   The impedance conversion circuit according to claim 1, wherein the first open stub and the second open stub are capacitive open stubs.   The impedance conversion circuit according to claim 1, wherein the circuit element is a line having a line length of approximately ８ wavelength.   The impedance conversion circuit according to claim 3 or 4, wherein the first open stub and the second open stub are open stubs having a line length of less than ¼ wavelength.   The impedance conversion circuit according to claim 1, wherein the circuit element is a chip capacitor whose impedance becomes inductive at a frequency to be transmitted.   The phase adjustment line is provided between the output terminal and the first open stub, or between the second open stub and the active element, according to any one of claims 1 to 6. Impedance conversion circuit. Comprising at least one active element,
A high-frequency circuit comprising the impedance conversion circuit according to claim 1 provided between at least one terminal of the active element and the input terminal and / or the output terminal. An impedance conversion characteristic adjustment method for an impedance conversion circuit connected between an input terminal or an output terminal and an active element,
A line or an inductance element connected in series between the first and second open stubs and a connection point of the first open stub and a connection point of the second open stub to the impedance conversion circuit. A circuit element,
The first and second open stubs are arranged so that the impedance viewed from the connection point of one of the first and second open stubs falls within a circle whose diameter is the center of the Smith chart and the short point. A method for adjusting impedance conversion characteristics of an impedance conversion circuit, characterized by determining a length of a stub and a constant / size of a circuit element.

Images