JP2009267699A - Digital data transmission apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital data transmission apparatus that is intended to limit the occurrence of asymmetric strain such as a signal amplitude variation or jitter which may be caused due to variation in a supply voltage and/or a ground level. <P>SOLUTION: Digital data output from a system LSI is provided to a waveform shaping circuit 4 via a buffer circuit 3(1). Then, digital data with rising and trailing parts subjected to overshooting is provided to a transmission path from a driving power supply line 25, and at this point a voltage on the driving power supply line 25 is adjusted by an adjusted voltage generation circuit 31 to obtain overshooting suitable for removing effect of waveform strain on a transmission system. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a digital data transmission apparatus using a system LSI, and in particular, a digital data that allows high-capacity digital data to be transmitted to an external memory at high speed during processing of system LSI data on a substrate. The present invention relates to a data transmission apparatus.

  In a system LSI, a processor is usually arranged inside, and data is written to and read from an external memory under the control of the processor during data processing. At this time, if the processing data is high-speed and large-capacity data such as video signals, the data transmission between the system LSI and the external memory is also high-speed and large-capacity, and transmission that can perform high-speed and large-capacity data transmission A system is required.

An example of a transmission system capable of performing such high-speed and large-capacity data transmission will be described with reference to FIG.
First, FIG. 10A shows a first transmission system in which two memories 72 (1), 72 (72) coupled to the system LSI 71 (1) through transmission paths 73 (1), 73 (2). 2).
Next, FIG. 10B shows a second transmission system, which includes a system LSI 71 (2) and two memories 72 (3) and 72 (4), which are connected to transmission lines 73 (3) and 73 (73). Combined in 4).
FIG. 10C shows a third transmission system in which a system LSI 71 (3) and two memories 72 (5) and 72 (6) coupled by transmission paths 73 (5) and 73 (6). It consists of and.

At this time, first, data of 8 bits and a clock frequency of 100 MHz is transmitted in the transmission lines 73 (1) and 73 (2) of the first transmission system.
Next, in the transmission paths 73 (3) and 73 (4) of the second transmission system, high-speed data is transmitted with a clock frequency of 200 MHz, although it is also 8 bits.
In the transmission lines 73 (5) and 73 (6) of the third transmission system, although the clock frequency is 100 MHz, the number of bits is 16 bits, and the data bus width is expanded to transmit a large amount of data. .

By the way, when data transmission is performed using such a transmission system, a large number of data and control signals to be transmitted can be switched between a high level and a low level at high speed. As a result, in the system LSI, the high level and the low level of the data and the control signal may be shaken with respect to the reference value due to the influence of the switching.
Then, the reason will be described next.

FIG. 11 is a waveform diagram for explaining the reason why the voltage level is fluctuated. FIG. 11A is a waveform of a clock signal, and FIG. 11B is an address signal, a control signal, Waveform of digital control signal supplied to external memory such as digital data, (c) is power supply voltage waveform, (d) is ground voltage waveform, (e) is a clock signal that temporarily fluctuates between high level and low level It is a waveform.
According to FIG. 11, when the digital control signal supplied to the external memory is formed inside the system LSI as shown in FIG. 11B, the power supply voltage, the ground voltage, It can be seen that each level of the clock signal fluctuates as shown in (c), (d), and (e) of FIG.

  In addition, FIG. 11 shows a case where the digital control signal appears only once, but in reality, as described above, the digital control signal includes a large number of address signals, control signals, digital data, and the like. Therefore, they are turned on / off at the same timing or close timing. For this reason, at the instant of turning on / off, the power supply voltage slightly decreases from the specified voltage value, and thereafter, a jumping voltage that transiently increases slightly from the specified voltage value is generated.

In the system LSI, various terminals including a power supply terminal and a ground terminal are derived for connection to an external circuit. The space between these terminals and the LSI chip is shown in the equivalent circuit of FIG. Thus, it is inevitable that the inductance La is included. For this reason, in the system LSI, the power supply voltage level and the ground voltage level fluctuate depending on the strength of the current flowing through the internal power supply line and the ground line.
Although the potential difference between the power supply voltage level and the ground potential level of such a clock system should originally be constant, it varies as described above, so the amplitude of the formed clock signal is also intermittent. When this change is abrupt, the signal waveform becomes asymmetrical in the vertical direction, causing jitter.

FIGS. 13 (a) and 13 (b) are signal waveform diagrams in which a clock signal waveform changes due to a digital control signal, for example, a CAS signal being changed on / off, on the display surface of an oscilloscope. (A) is a case where the amplitude of a part of the clock signal shown in the lower part is small when the CAS signal shown in the upper part is turned on / off, and (b) in FIG. This is a case where the duty is also changed due to the decrease in the amplitude of.
When such a decrease in amplitude or a change in part of duty occurs in the clock signal, there arises a problem that data cannot be read correctly.

  To solve this problem, this type of system prevents the occurrence of a power supply voltage drop due to a large amount of current flowing at one time by shifting the rising and falling timings of transmission data and control signals. In order to suppress level fluctuations in these layers by strengthening the power supply layer and the ground layer in the system LSI package, or to reduce the equivalent inductance formed between the LSI terminal and the LSI chip in an apparent manner. By using the LSI terminal as a power supply terminal and a ground terminal, a protection means that suppresses the occurrence of adverse effects may be employed.

  On the other hand, apart from the transmission system equipped with these protection means, when high-frequency data is transmitted between two LSIs at high speed, the occurrence of ringing in the data waveform due to parasitic inductance and parasitic capacitance of the transmission line is suppressed, Conventionally, pulse transmission means capable of performing highly reliable data transmission has been proposed (see, for example, Patent Document 1).

  In the pulse transmission means according to this proposal, when high-frequency data is transmitted at high speed between two LSIs, the transmission data changes from a low level to a high level, and the high level changes to a low level after a certain period of time. A rectangular wave that changes to a low level after the high level of the rectangular wave has continued for a certain period of time, and a deformed rectangular wave that has been deformed so that the high level duration of the rectangular wave is slightly shorter By using the formed stepped rectangular wave and transmitting this stepped rectangular wave between LSIs, the vibration due to the ringing of the rectangular wave and the vibration due to the ringing of the deformed rectangular wave cancel each other, and pulse transmission with high reliability is achieved. It is what was done.

Japanese Patent Laid-Open No. 07-327054

However, in the transmission system including the above-described defense means, when the number of transmission data and control signals used is several tens and the data and control signals are transmitted at high speed, the respective data In addition, there is a limit to shifting the rising timing and falling timing of the control signal from each other.
Also, since system LSIs used in this type of transmission system are usually large-scale, a plurality of power supply layers such as 1.2V, 2.5V, and 3.3V and a plurality of ground layers corresponding thereto are used. Therefore, there is a limit to strengthening the power supply layer and the grounding layer.

Furthermore, in this case, the number of terminals that can be derived from the system LSI is limited. Therefore, even if the system LSI becomes large-scale, these terminals are connected to more power supply terminals than ever before. It is becoming difficult to distribute and use the ground terminal.
On the other hand, in the case of the proposed pulse transmission means, occurrence of ringing can be suppressed, but improvement of digital signal distortion caused by power supply fluctuation in the LSI, particularly asymmetric distortion generated in the clock signal cannot be expected. .

  The present invention has been made in view of such circumstances, and its purpose is digital data that can suppress the occurrence of asymmetric distortion such as signal amplitude fluctuation and jitter accompanying fluctuations in power supply voltage and ground potential level. It is to provide a transmission apparatus.

  In order to achieve the above object, in a digital data transmission apparatus that supplies digital data output from a system LSI to an external memory via a transmission line, an overshoot is applied to the waveform output from the system LSI to the transmission line. A waveform shaping unit to be applied, and an adjustment voltage generation unit that feedback-controls the amount of overshoot by the waveform shaping unit based on the output of the waveform shaping unit, so that the influence of the waveform distortion generated by the transmission path is removed. It is characterized by.

  At this time, the data supplied from the system LSI to the external memory via the transmission path is a digital control signal including digital data, a clock signal, etc., and the waveform shaping means and the adjustment voltage generating means are first and first Two systems of 2 may be provided.

  Here, when the digital data is output from the system LSI to the transmission line, the waveform shaping circuit monitors the fluctuation of the power supply voltage, and if there is a possibility that the digital data waveform may be distorted by the monitoring, The distortion generated in the digital data waveform may be removed by adjusting the supplied signal current value. Similarly, when the waveform shaping circuit outputs a clock signal from the system LSI to the transmission line, When the fluctuation is monitored and there is a possibility that the fluctuation of the clock signal amplitude or jitter may occur by the monitoring, the fluctuation of the clock signal amplitude or jitter may be removed by adjusting the fluctuation amount of the power supply voltage. .

  Further, at this time, the waveform shaping circuit controls the driving transistor for supplying the input digital signal to the transmission path amplified, the current adjusting transistor for supplying the driving transistor with the power supply voltage, and the current adjusting transistor. An adjustment voltage generation circuit that supplies a current adjustment voltage to the electrode may be provided, wherein the adjustment voltage generation circuit in the waveform shaping circuit is configured to detect rising and falling edges of the digital signal waveform output to the transmission line. A first circuit that forms a first voltage that represents dullness; a second circuit that forms a second voltage when an overshoot is excessively applied to the digital signal waveform output to the transmission line and when the power supply voltage fluctuates; A third circuit that forms a current adjustment voltage by adding, subtracting, and integrating the first voltage and the second voltage may be used.

According to the present invention, the waveform shaping circuit is provided in the system LSI, and the waveform shaping circuit shapes the digital data and the digital control signal supplied to the transmission path between the system LSI and the external memory in an optimum state. Thus, the waveform change can be improved.
Therefore, according to the present invention, it is possible to transmit a large amount of data and control signal at high speed without distortion, and the amplitude fluctuation of the digital control signal, particularly the clock signal, accompanying the fluctuation of the power supply voltage and the ground level. And asymmetric distortion such as jitter can be suppressed.

Hereinafter, a digital data transmission apparatus according to the present invention will be described in detail using embodiments.
FIG. 1 is a block diagram showing an embodiment of the present invention. In this case, the system LSI 1 functions to write and read data to and from the external memory 2 for signal processing. When the system LSI 1 performs signal processing and writes the digital data to the external memory 2, the data is input from the first buffer circuit 3 (1) to the first waveform shaping circuit 4 (1).

Therefore, in the first waveform shaping circuit 4 (1), as will be described later, the waveform of the input digital data is shaped so as to have a predetermined shape, and then supplied to the first transmission / reception selector switch 5.
When the write enable signal WE is supplied via the control line, the first transmission / reception change-over switch 5 switches the contact to the transmission side, and the data supplied to the first transmission / reception switch 5 is configured by a printed circuit board or the like. It is transmitted to the external memory 2 through the existing transmission line 6 (1).

  When the system LSI transmits a digital control signal other than digital data, for example, an address signal or a clock signal that is a control signal of the external memory 2, to the external memory 2, the control signal is transmitted to the third buffer circuit 3 ( 3) is input to the second waveform shaping circuit 4 (2), and the second waveform shaping circuit 4 (2) shapes the digital control signal so as to have a predetermined shape. The data is transmitted to the external memory 2 via the configured transmission path 6 (2), and the external memory 2 is controlled.

  First, the first waveform shaping circuit 4 (1) will be described in detail with reference to FIG. 2. As shown in the drawing, the first driving transistor 9 (1) and the second driving transistor 9 (2) are illustrated. And the third driving transistor 9 (3), the first inverter 10 (1), the second inverter 10 (2) and the third inverter 10 (3), the delay circuit 12, and the first current adjusting transistor 11 ( 1), a second current adjusting transistor 11 (2) and a third current adjusting transistor 11 (3).

  The first waveform shaping circuit 4 (1) includes a first comparator 13, a second comparator 14, a third comparator 15 (1), a fourth comparator 15 (2), a fifth comparator 16, and a first reference. Voltage 17, second reference voltage 18, third reference voltage 19, fourth reference voltage 20 and fifth reference voltage 21, EXOR circuit (exclusive OR circuit) 22, first adder circuit 23 (1) and second An adjustment voltage generation circuit 31 including an addition circuit 23 (2), an addition / subtraction circuit 30, a first integration circuit 24 (1), a second integration circuit 24 (2), and a third integration circuit 24 (3) is provided.

First, the input of the first inverter circuit 10 (1) is connected to the output terminal of the first buffer circuit 3 (1) at the preceding stage, and the output is connected to the second inverter circuit 10 (2) and the resistor R3. Are connected to the gate of the first driving transistor 9 (1).
Next, the second inverter circuit 10 (2) has its input connected to the output of the first inverter circuit 10 (1) and its output connected to the input of the delay circuit 12.
At this time, the input of the delay circuit 12 is connected to the output of the second inverter circuit 10 (2), and the output is connected to the second driving transistor 9 ((2) via the input of the third inverter circuit 10 (3) and the resistor R8. Each is connected to the gate of 2).

The third inverter circuit 10 (3) has its input connected to the output of the delay circuit 12, and its output connected to the gate of the third driving transistor 9 (3) via the resistor R4.
On the other hand, the first driving transistor 9 (1) has a gate connected to the output of the first inverter circuit 10 (1) via the resistor R3, a source connected to the driving power supply line 25, and a drain connected to the resistor R10. And connected to the power line (3) 29.
Next, the gate of the second driving transistor 9 (2) is connected to the output of the delay circuit 12 via the resistor R8, and the source is then connected to the first current adjusting transistor 11 (1) via the resistor R9. At this time, the drain is connected to the ground (common potential point).

The third drive transistor 9 (3) has a gate connected to the output of the third inverter circuit 10 (3) via a resistor R4, a source connected to the power supply line (2) 28, and a drain The resistor R6 is connected to the source of the second current adjusting transistor 11 (2).
On the other hand, the gate of the first current adjustment transistor 11 (1) is connected to the adjustment voltage 26 (2) via the resistor R7, the source is connected to the drive power supply line 25, and the drain is connected to the second voltage via the resistor R9. Each is connected to the source of the driving transistor 9 (2).

The second current adjusting transistor 11 (2) has a gate connected to the adjusting voltage 26 (1) via the resistor R5, and a source connected to the drain of the third driving transistor 9 (3) via the resistor R6. The drains are connected to the drive power supply line 25, respectively.
The third current adjustment transistor 11 (3) has a gate connected to the adjustment voltage 26 (3) via the resistor R2, a source connected to the power supply line (1) 27 via the resistor R1, and a drain connected to the power supply line (1) 27. It is connected to the drive power line 25.

Next, the adjustment voltage generation circuit 31 will be described.
First, the first comparator 13 has a non-inverting input (+) connected to the drive power supply line 25, an inverting input (−) connected to the first reference power supply 17, and an output connected to one input of the EXOR circuit 22. It is connected.
The second comparator 14 has a non-inverting input (+) connected to the drive power supply line 25, an inverting input (−) connected to the second reference voltage 18, and an output connected to the other input of the EXOR circuit 22. It is connected.

Next, the third comparator 15 (1) has a non-inverting input (+) connected to the driving voltage 25, an inverting input (−) connected to the third reference voltage 19, and an output from the first adding circuit 23. It is connected to the input terminal of (1).
The fourth comparator 15 (2) has a non-inverting input (+) connected to the fourth reference voltage 20, an inverting input (−) connected to the drive voltage line 25, and an output from the second adding circuit 23. Connected to the input terminal in (2).
The fifth comparator 16 has a non-inverting input (+) connected to the fifth reference voltage 21, an inverting input (−) connected to the power supply line (1) 27, and an output as a subtraction terminal of the addition / subtraction circuit 30. (-)It is connected to the.

Next, the first adder circuit 23 (1) has one input connected to the output of the EXOR circuit 22, the other input connected to the output of the third comparator 15 (1), and the output is the first integration. It is connected to the circuit 24 (1).
The second adder circuit 23 (2) has one input connected to the output of the EXOR circuit 22, the other input connected to the output of the fourth comparator 15 (2), and the output of the second adder circuit 23 (2). 24 (2).
The addition / subtraction circuit 30 has the addition input (+) connected to the output of the EXOR circuit 22, the subtraction input (−) connected to the output of the fifth comparator 16, and the output thereof as the third integration circuit 24 (3). It is connected to the.

Next, the input of the first integrating circuit 24 (1) is connected to the output of the first addition / subtraction circuit 23 (1), and the output is connected to the gate of the first current adjusting transistor 11 (1) via the resistor R7. Thus, the adjustment voltage 26 (2) is supplied to the gate of the first current adjustment transistor 11 (1).
The second integration circuit 24 (2) has an input connected to the output of the second addition / subtraction circuit 23 (2) and an output connected to the gate of the second current adjusting transistor 11 (2) via the resistor R5. Thereby, the adjustment voltage 26 (1) is supplied to the gate of the second current adjustment transistor 11 (2).

The third integration circuit 24 (3) has an input connected to the output of the addition / subtraction circuit 30, and an output connected to the gate of the third current adjusting transistor 11 (3) via the resistor R2, thereby adjusting the adjustment voltage. 26 (3) is supplied to the gate of the third current adjusting transistor 11 (3).
At this time, the EXOR circuit 22 has one input connected to the output of the first comparator 13 and the other input connected to the output of the second comparator 14. The output is connected to the first addition circuit 23 (1), the second addition circuit 23 (2), and the addition input (+) of the addition / subtraction circuit 30.

Next, the second waveform shaping circuit 4 (2) in FIG. 1 will be described. This is the same as the first waveform shaping circuit 4 (1) described above, except that the input is the third buffer. Only the point that is the output of the circuit 3 (3) and the point that the drive voltage 25 is directly connected to the transmission line 6 (2). Therefore, a detailed description of the configuration is omitted.
As a result, the first waveform shaping circuit 4 (1) and the second waveform shaping circuit 4 (2) have the same operation except for the input signal and the output signal.
Therefore, hereinafter, the operations of the first waveform shaping circuit 4 (1) and the second waveform shaping circuit 4 (2) will be described together with the first waveform shaping circuit 4 (1) as a representative.

First, as shown in FIG. 1, digital data is input to the first waveform shaping circuit 4 (1) from the first buffer circuit 3 (1).
At this time, the digital data input from the first buffer circuit 3 (1) is a signal having a waveform shown in FIG. 4A, which is supplied to the input of the first inverter circuit 10 (1).
Therefore, as shown in FIG. 4B, the first inverter circuit 10 (1) outputs digital data in which the waveform of FIG. 4A is inverted, and this digital data is output as the second inverter circuit. 10 (2) and simultaneously input to the gate of the first driving transistor 9 (1) via the resistor R3.

At this time, the power supply voltage Vcc1 of the power supply line (1) 27, the power supply voltage Vcc2 of the power supply line (2) 28, and the power supply voltage Vcc3 of the power supply line (3) 29 have the relationship shown in FIG. (Vcc1>Vcc2>E> Vcc3).
Therefore, if the signal shown in FIG. 4 (b) is input from the first inverter circuit 10 (1), the first driving transistor 9 (1) is turned on when this signal is at a high level, and at the low level. Turn off. Therefore, the source of the first driving transistor 9 (1) has an inverted relationship as shown in FIG.

The voltage V1 at the high level at this time is determined by the resistance value R1 and the drain current of the third current adjusting transistor 11 (3), and the drain current is ID3.
V1 = Vcc1-ID3 ・ R1
It becomes.
On the other hand, when the voltage at the low level is V4, this is determined by the resistance value R1, the resistance value R10, the power supply voltage Vcc1 of the power supply line (1) 27, and the power supply voltage Vcc3 of the power supply line (3) 29.
V4 = R10 / (R1 + R10). (Vcc1-Vcc3)
It becomes.

On the other hand, the output of the second inverter circuit 10 (2) has the same waveform as FIG. 4C because the signal of FIG. 4B is inverted, and this is input to the delay circuit 12, where Since a delay of time τ is given, the output waveform thereof is as shown in FIG. 4 (d), which is input to the third inverter circuit 10 (3), and is connected to the second drive transistor 9 via the resistor R8. It is also input to the gate in (2).
The second driving transistor 9 (2) is turned on when the gate is at a high level and turned off when the gate is at a low level.
Therefore, if there is no third drive transistor 9 (3), resistor R6, and second current adjustment transistor 11 (2), the voltage of the drive power supply line 25 has a waveform as shown in FIG. 4 (e). It becomes.

Here, when the drain current of the first current adjusting transistor 11 (1) is ID1, the voltage V2 of the driving power supply line 25 when the second driving transistor 9 (2) is ON is determined by the resistor R9 and the current ID1. ,
V2 = Vcc1-ID3 / R1-ID1 / R9
It becomes.
At this time, as is apparent from FIG. 4 (e), the voltage V1 is overshooted at the rising edge of the waveform, and the level of this overshoot is given by the difference between the voltage V1 and the voltage V2, and therefore, It can be adjusted by the drain current ID1 of the one-current adjusting transistor 11 (1).

Since the input waveform of the third inverter circuit 10 (3) at this time is (d) of FIG. 4, the output is inverted and becomes as shown in (f) of FIG.
The output of the third inverter circuit 10 (3) is supplied to the gate of the third driving transistor 9 (3) via the resistor R4. Here, since the third driving transistor 9 (3) is turned on when the input is high and turned off when the input is low, the voltage of the driving power supply line 25 at this time is as shown in FIG. It becomes a waveform.

The voltage V3 in the ON state is determined by the current flowing through the resistor R6 and the second current adjusting transistor 11 (2). That is, when the drain current of the second current adjusting transistor 11 (2) is ID2,
V3 = R10 / (R1 + R10) * (Vcc1-Vcc3) + ID2 * R6
Therefore, also in this case, it is possible to determine the overshoot level of the falling portion by adjusting the drain current ID2 of the second current adjusting transistor 11 (2).

  In this way, the voltage level is controlled, and as shown in FIG. 4G, the digital data of the drive power supply line 25 in which overshoot is given to both the rising and falling portions of the waveform is shown in FIG. As will be apparent, it is supplied to the transmission / reception selector switch 5 (in the case of the second waveform shaping circuit 4 (2), it is supplied to the transmission line 6 (2)). The voltage is further taken into the non-inverting input (+) of each of the first comparator 13, the second comparator 14, and the third comparator 15 (1), and is inverted by each of the fourth comparator 15 (2) and the fifth comparator 16. Captured to the input terminal (-).

  Here, the reference voltage Va is input from the first reference power supply 17 to the inverting input (−) of the first comparator 13, and the reference voltage Vb is input from the second reference power supply 18 to the inverting input (−) of the second comparator 14. However, the voltage Va and the voltage Vb at this time are selected so as to satisfy the relationship of Vb> intermediate voltage> Va with respect to the intermediate voltage between the high level and the low level of the drive power supply line 25. In the case where the voltage of the drive power supply line 25 is digital data in which the rising part and the falling part are not upright but the waveform is blunted with no overshoot as shown in FIG. There is a difference in the detection timing of the digital data in 13 and the second comparator 14.

In other words, since the reference voltage Va is lower than the intermediate voltage, the output of the first comparator 13 rises from the low level to the high level near the rising start portion of the digital data as shown in FIG. Since it falls from the high level to the low level near the end of falling, the rectangular wave has a slightly wider width.
On the other hand, since the reference voltage Vb is higher than the intermediate voltage, the output of the second comparator 14 rises from the low level to the high level near the rising end portion of the digital data as shown in FIG. Since the digital data falls from the high level to the low level in the vicinity of the falling start portion of the digital data, the rectangular wave has a slightly narrow width.

The outputs of the first comparator 13 and the second comparator 14 are input to the EXOR circuit 22, and as a result, the output of the EXOR circuit 22 is supplied to the rising and falling parts of the digital data as shown in FIG. 5 (d). Two corresponding pulses are generated and input to the addition terminal (+) of the first addition circuit 23 (1), the second addition circuit 23 (2), and the addition / subtraction circuit 30. The pulse width obtained here becomes wider as the waveform dullness at the rising and falling portions of the digital data of the drive voltage 25 increases.
If overshoot is applied to the digital data of the drive power supply line 25 at this time and the waveform is as shown in FIG. 5 (e), the dullness of the waveform generated in the transmission system 6 (1) is corrected, and FIG. As indicated by the broken line in (e), it is possible to return to a waveform close to the original digital data (details will be described later).

Next, in the case of the third comparator 15 (1), a part of the digital data of the drive power supply line 25 is inputted to the non-inverting input (+), and the voltage Vc is outputted to the inverting input (−). When the voltage of the drive power supply line 25 becomes a voltage level lower than the voltage Vc as shown in FIG. 6 (a), as shown in FIG. 6 (b). At the same time, the output level of the third comparator 15 (1) becomes a low level.
That is, in the digital data of the drive power supply line 25, when an overshoot is excessively applied to the rising portion, the pulse width is derived from the output of the third comparator 15 (1) at the overshoot portion. Therefore, the third comparator 15 (1) detects that an excessive overshoot that is lower than the voltage Vc in the digital data of the drive power supply line 25 occurs.

At this time, a part of the digital data of the drive power supply line 25 is input to the inverting input (−) of the fourth comparator 15 (2), and the voltage Vd is output to the non-inverting input (+). A reference voltage 20 is connected.
Therefore, when the voltage of the reference power supply 25 becomes higher than the voltage Vd as shown in FIG. 6 (c), the output level of the fourth comparator 15 (2) is shown in FIG. 6 (d). And so on.
That is, when the overshoot of the falling portion is excessively applied to the digital data of the drive power supply line 25, a pulse is derived from the output of the fourth comparator 15 (2) in the overshoot portion.
Therefore, the fourth comparator 15 (2) detects that excessive overshoot has occurred in the digital data of the drive power supply line 25 when it becomes higher than the voltage Vd.

Here, when the digital data as shown in FIG. 7A is output to the drive power supply line 25, the power supply voltage Vcc1 of the power supply line is changed as shown in FIG. May fluctuate transiently and may be temporarily lower than the fifth reference voltage Ve.
At this time, the fifth comparator 16 has its inverting input (-) connected to the power supply line (1) 27 and its non-inverting input (+) connected to the fifth reference power supply 21. When the power supply voltage Vcc1 decreases as shown in (a), the current level changes from the low level to the high level, and a high level pulse shown in FIG. It functions to monitor fluctuations in the voltage Vcc1.

The addition / subtraction output voltage output from the first addition circuit 23 (1) is supplied to the first integration circuit 24 (1). At this time, as described above, the output of the EXOR circuit 22 is also input to the terminal of the first adder circuit 23 (1).
Therefore, when the overshoot of the rising portion of the voltage of the drive power supply line 25 occurs excessively and the first integrating circuit 24 (1) has a waveform as shown in FIG. The operation is performed so as to obtain the waveform output shown in FIG. 8B from (1).
That is, as shown in FIG. 8 (a), there is an overshoot in the voltage changing portion of the drive power supply line 25, so that the output of the third comparator 15 (1) is thin as shown in FIG. 8 (b). It is a pulse. Therefore, the first integrating circuit 24 (1) operates so that the integrated output voltage becomes low.

On the other hand, as shown in FIG. 8C, when the overshoot at the rising portion is insufficient, the output of the third comparator 15 (1) becomes as shown in FIG. Therefore, the integral output works to increase, and the EXOR circuit 22 output operates so that the waveform of the digital data changing portion of the drive power supply line 25 becomes dull, so that the integrated output voltage is also increased. To do.
The integrated output voltage of the first integrating circuit 24 (1) is supplied to the gate of the first current adjusting transistor 11 (1) via the resistor R7.

In this case, if the integrated output voltage of the first integrating circuit 24 (1) increases, the current flowing through the first current adjusting transistor 11 (1) increases, while the integrated output of the first integrating circuit 24 (1). As the voltage decreases, the current flowing through the first current adjusting transistor 11 (1) decreases.
Accordingly, when the waveform of the change portion of the digital data in the drive power supply line 25 becomes dull, the current flowing through the first current adjustment transistor 11 (1) increases, and as a result, the voltage difference of the overshoot increases and the drive power supply The dullness of the change portion of the digital data waveform of the line 25 is eliminated. On the contrary, when the overshoot is excessive at the rising portion of the digital data, the current flowing through the first current adjusting transistor 11 (1) is reduced. It works in a direction to reduce the occurrence of excessive overshoot at the rising portion in the digital data.

Similarly, the added output voltage output from the second adding circuit 23 (2) is supplied to the second integrating circuit 24 (2) and integrated there. As shown in FIG. 9 (a), the second integrating circuit 24 (2) becomes as shown in FIG. 9 (b) when the overshoot of the falling portion of the voltage of the drive power supply line 25 occurs excessively. , Operates so that its integrated output decreases.
The output of the EXOR circuit 22 is input to the terminal of the second adder circuit 23 (2) and is similarly integrated by the second integrator circuit 24 (2).
The second integration circuit 24 (2) operates so that the integrated output voltage is low because the waveform of the changing portion of the digital data of the drive power supply line 25 stands with a narrow width.

On the other hand, as shown in FIG. 9C, when the overshoot is insufficient, the output of the fourth comparator 15 (2) becomes a wide pulse as shown in FIG. 9D, and the integrated output increases. At this time, in the output of the EXOR circuit 22, the waveform of the changing portion of the digital data of the drive power supply line 25 becomes dull, so that the integrated output is increased.
The integrated output voltage of the second integrating circuit 24 (2) is supplied to the gate of the second current adjusting transistor 11 (2) via the resistor R5.
Therefore, if the integrated output voltage of the second integrating circuit 24 (2) increases, the current flowing through the second current adjusting transistor 11 (2) increases, and if the integrated output voltage decreases, the second current adjusting transistor. The current flowing through 11 (2) decreases.

  Accordingly, when the waveform of the changing portion of the digital data in the drive power supply line 25 becomes dull, the current flowing through the second current adjusting transistor 11 (2) increases, and as a result, the voltage difference of overshoot increases and the drive power supply The dullness of the change portion of the digital data waveform on the line 25 is eliminated. On the other hand, when the overshoot is excessive at the falling portion of the digital data, the current flowing through the second current adjusting transistor 11 (2). This reduces the occurrence of excessive overshoot at the trailing edge of the digital data.

On the other hand, the addition / subtraction output voltage output from the addition / subtraction circuit 30 is supplied to the third integration circuit 24 (3) and integrated there.
Therefore, in the third integration circuit 24 (3), when the voltage Vcc1 of the power supply line (1) 27 is lowered, the pulse width of the output of the fifth comparator 16 is widened as shown in FIG. 7 (c). As a result, the output level of the addition / subtraction circuit 30 is lowered. Therefore, it operates so that the integral output decreases.
On the other hand, the output of the EXOR circuit 22 is input to the addition terminal (+) of the third addition / subtraction circuit 23 (3) and is similarly integrated by the third integration circuit 24 (3).

Therefore, the third integrating circuit 24 (3) operates so that the integrated output voltage of the third integrating circuit 24 (3) becomes high when the waveform of the digital data changing portion of the drive power supply line 25 is dull. To do.
The integrated output voltage of the third integrating circuit 24 (3) is supplied to the gate of the third current adjusting transistor 11 (3) via the resistor R2.
Therefore, if the integrated output voltage of the third integrating circuit 24 (3) increases, the current flowing through the third current adjusting transistor 11 (3) increases, while the integrated output voltage of the third integrating circuit 24 (3). Decreases, the current flowing through the third current adjusting transistor 11 (3) decreases.

  Therefore, when the waveform of the changing portion of the digital data of the drive power supply line 25 becomes dull, the current flowing through the third current adjustment transistor 11 (3) increases, and as a result, the current flowing through the drive power supply line 25 increases. When the change in the waveform of the digital data in the drive power supply line 25 is eliminated, the third current adjustment transistor 11 (3) is reversed when the voltage drop of the voltage Vcc1 in the power supply line (1) 27 is large. ) Is reduced, and excessive overshooting in digital data is eliminated.

As a result, according to the first waveform shaping circuit 4 (1), a feedback loop is configured for the digital data waveform of the drive power supply line 25. Therefore, according to this embodiment, the drive power supply The digital data of the line 25 can always be held in an optimum waveform.
By the way, the operation of the first waveform shaping circuit 4 (1) has been described above. As described above, the operation of the second waveform shaping circuit 4 (2) is performed by changing the target signal of the waveform shaping process from digital data to digital data. Almost the same operation is performed except for the change to the control signal.

  Therefore, according to the digital data transmission apparatus according to this embodiment, when digital data and digital control signals are transmitted from the system LSI 1 to the external memory 2 via the transmission paths 6 (1) and 6 (2), the system LSI 1 Since the first waveform shaping circuit 4 (1) and the second waveform shaping circuit 4 (2) are arranged, the waveform of the transmission data output from the system LSI 1 and the change portion of the control signal is shaped to be steep. At the same time, it is possible to suppress the occurrence of asymmetry such as fluctuations in the amplitude of the control signal and jitter accompanying fluctuations in the power supply voltage and ground level.

It is a block diagram which shows embodiment of the digital data transmission apparatus by this invention. It is a circuit diagram of the waveform shaping circuit in the embodiment of the present invention. It is explanatory drawing of the power supply voltage set to a waveform shaping circuit. It is a wave form diagram for demonstrating the production | generation operation | movement of the overshoot by a waveform shaping circuit. It is explanatory drawing of the detection operation | movement when the rise and fall of a waveform become blunt in a waveform shaping circuit. FIG. 6 is a waveform diagram for explaining an operation of detecting an overshoot at the rise and fall of a waveform in the waveform shaping circuit. It is a wave form diagram for demonstrating the detection operation of the power supply voltage drop by a waveform shaping circuit. It is a wave form diagram for demonstrating the detection operation when the overshoot of the rising part of the waveform by a waveform shaping circuit is excessive and insufficient. It is a wave form diagram for demonstrating the detection operation when the overshoot of the falling part by a waveform shaping circuit is excessive, and when it is insufficient. It is explanatory drawing which shows an example of the transmission system which can perform high-speed large-capacity data transmission. It is a wave form diagram for demonstrating the voltage drop in data transmission, and the level fluctuation of the vibration clock of a ground. It is a circuit diagram which shows the equivalent circuit of the wiring between the terminal in a system LSI, and an LSI chip. It is explanatory drawing which shows an example of the level fluctuation phenomenon in data transmission.

Explanation of symbols

1: System LSI
2: External memory 3, 8: Buffer circuit 4: Waveform shaping circuit 6: Transmission path 9 (1), 9 (2), 9 (3): Driving transistor (Tr)
11 (1), 11 (2), 11 (3): Current adjustment transistor (Tr)
13, 14, 15 (1), 15 (2), 16: Comparator 22: EXOR circuit 23 (1), 23 (2): Adder circuit 30: Adder / subtracter circuit 24 (1), 24 (2), 24 (3 ): Integration circuit 25: Drive power line

Claims (2)

In a digital data transmission apparatus of a method for supplying digital data output from a system LSI to an external memory via a transmission path,
Waveform shaping means for overshooting the waveform output from the system LSI to the transmission line;
Provided is an adjustment voltage generating means for feedback-controlling the amount of overshoot by the waveform shaping means based on the output of the waveform shaping means,
A digital data transmission apparatus configured to eliminate the influence of waveform distortion generated by the transmission path. The digital data transmission apparatus according to claim 1,
The data output from the system LSI includes the digital data and digital control data different from the digital data,
A data transmission apparatus comprising the first and second systems of the waveform shaping means and the adjustment voltage generating means.