JP2009267410A - Area optimized esd protection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ESD (electrostatic discharge) protection circuit in which the gap between an operating voltage range and a protection voltage is reduced and thereby a necessary area is small. <P>SOLUTION: This ESD protection circuit (40) includes a first terminal (12) and a second terminal (14), and an ESD current path (42) which is coupled between the first terminal (12) and the second terminal (14). The ESD current path is conducted through the operating current range of an ESD transistor (44), and the ESD transistor (44) is controlled depending on a voltage at the intermediate tap (46) of a voltage divider (48), and the voltage divider is coupled between the first terminal (12) and the second terminal (14). In this ESD protection circuit (40), the ESD transistor (44) is controlled through a transistor (49), and the transistor (49) is controlled by an inverter (50) with the inversion potential of the intermediate tap (46). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an ESD protection circuit including a first terminal, a second terminal, and an ESD current path between the first terminal and the second terminal, the ESD current path being an ESD transistor. The ESD transistor is controlled depending on the potential of the intermediate tap of the voltage divider, and the voltage divider is connected between the first and second terminals.

  Such an ESD protection circuit is known, for example, from US 5,465,188.

  Further, in this specification, the abbreviation “ESD” means “electrostatic discharge” as is well known. The ESD protection circuit protects a circuit connected to the ESD protection circuit from a potential destructive electrostatic discharge. The ESD protection circuit can be connected in series or in parallel with the circuit to be protected. A series circuit arrangement with the features mentioned at the outset is known from US 5,465,188. According to this publication, an ESD transistor is connected in series with a load to be protected from overcurrent and is controlled by an operational amplifier. This operational amplifier measures the voltage drop across the ESD transistor with a voltage divider and compares it with a reference voltage. This reference voltage is generated by a bandgap reference. The advantage of such a circuit is that it is insensitive to temperature effects according to US 5.465,188. The operational amplifier and the bandgap reference each include a number of transistors (eg, about 20). Furthermore, the large area required of the known circuit is a disadvantage.

  It is also known per se that an ESD protection circuit having a bandgap reference and an operational amplifier is connected in parallel to the circuit to be protected.

  The first and second terminals further include a first ESD current path and a second ESD current path, and each ESD current path is a circuit to be protected. ESD protection circuits connected in parallel are known. Under normal conditions without faults, the two ESD current paths are high resistance so as not to impair the function of the circuit to be protected as much as possible. However, when an electrostatic discharge occurs in one of the two terminals, at least one of the two ESD current paths becomes low resistance, releasing excess charge in the circuit to be protected to the other terminal.

  In general, ESD protection is divided into dynamic protection and static protection. For dynamic protection, a high transient current of the ESD pulse is used. This ESD pulse, for example, controls an ESD transistor in the first ESD current path in parallel with the circuit to be protected, via its mirror capacitance, so that a high lateral current passes through the circuit to be protected. enable.

  Static ESD protection is achieved in the simplest case by a Zener diode in the second current path. The zener diode is connected in parallel with the first current path and the circuit to be protected. Such Zener diodes have a high resistance at low voltages and therefore do not act electrically. On the other hand, when the voltage value is relatively high, a larger lateral current can be passed in the circuit to be protected.

  Such protection is also referred to as an ESD clamp. This combination with dynamic protection is also referred to as an active ESD clamp.

  Furthermore, the ESD protection circuit itself is known. The ESD protection circuit is connected in parallel with the circuit to be protected, and has first and second terminals and an ESD current path between the first and second terminals. This ESD current path is guided over the operating current section of the ESD transistor.

  The ESD transistor is controlled by an operational amplifier. This operational amplifier is controlled depending on the output of the band gap reference and the potential of the intermediate tap of the voltage divider. The voltage divider is connected between the first and second terminals.

  Basically, the protection voltage at which the ESD protection circuit acts should have as little spacing as possible relative to the normal operating voltage generated at the terminals of the circuit to be protected during normal operation.

  Here, the “snapback” action will be described. In this case, it works for the first time when the lateral current (that is, the current that flows laterally through the circuit to be protected) exceeds the “ignition voltage”, and disappears only when it falls below the “extinguishing voltage” or “extinguishing current”. . The voltage adjusted here must likewise vary between the operating voltage and the protection voltage.

  In semiconductor technology, it is not possible to arbitrarily select a Zener voltage of a Zener diode that can be realized. Thus, a circuit comprising a plurality of series-connected Zener diodes is used for static ESD protection when the value of the protection voltage is much higher than the individual Zener voltage. In order to increase the switching speed for dynamic ESD protection, implementations with current mirrors and Darlington transistor circuits are known.

  It is also a conventional technique to integrate a plurality of input terminals or circuits to be protected by a single ESD terminal using a coupling diode.

  It is also prior art to divide ESD protection into positive ESD pulse protection and negative ESD pulse protection, each with one separate ESD circuit.

  When realizing the ESD protection circuit, there is a first problem that the interval between the operating region and the protection voltage is undesirably large due to the temperature effect on the specification data of the electronic components. This problem is particularly noticeable with sub-micrometer technology that is too small for the required spacing for “standard” ESD protection mechanisms.

  The second problem is that long-term manufacturing certainty and possible technical compatibility must be ensured. Thus, only components that can reproduce the parameters and can be inspected in the manufacturing process can be used. Therefore, a series of ESD protection circuits based on interesting physical effects are not well suited for mass production.

  A third problem arises from the fact that normal semiconductor technology is based on the use of integrated diode pockets, in which individual components are separated from one another by PN junctions. Therefore, for an input terminal that can take a negative voltage value with respect to the substrate, the selection of connectable components that do not include such a PN junction is very limited.

  A fourth problem is that two ESD protection mechanisms are required for the two polarities of the ESD pulse.

The fifth problem occurs when the protection voltage is so large that a circuit in which a plurality of Zener diodes are connected in series is impossible, or when the protection voltage is smaller than a realizable Zener voltage. Further, the required area of the ESD protection circuit is Should be as small as possible.

US 5,465,188

  With these backgrounds, the problem of the present invention is that the distance between the operating voltage region and the protection voltage is reduced, and the ESD protection circuit with a small required area, that is, the ESD protection that reduces the required area and solves the first problem. To provide a circuit.

  This problem is solved by the features of claim 1. Further advantages emerge from the dependent claims, the description and the attached drawings.

  The ESD protection circuit of the present invention requires significantly fewer components than the known circuit described at the beginning with an operational amplifier and a bandgap reference. Since the number of constituent elements is small, the risk of circuit failure due to constituent element errors is reduced. Therefore, reliability is improved. Furthermore, the required area of the ESD protection circuit is significantly reduced due to the reduction in the number of components. The advantage that the temperature dependence of the electrical properties in the ESD protection circuit known from US 5,465,188 is small is also maintained in the present invention.

  It will be understood that the features described above, and further described below, can be used not only in the combinations described, but also in other combinations or alone, without departing from the scope of the present invention.

  In the following, embodiments of the invention will be described in detail with reference to the drawings.

A known ESD protection circuit with a bandgap reference and an operational amplifier is shown, which ESD protection circuit is connected in parallel to the circuit to be protected. 1 shows a first embodiment of an ESD protection circuit according to the present invention; 2 shows a second embodiment of an ESD protection circuit according to the present invention. The structure of the voltage source used in FIG. 3 is shown. It is a diagram which shows the relationship between the actual voltage between ESD protection circuit terminals, and a hypothetical voltage. FIG. 5 is a diagram showing the relationship between various voltages whose characteristics are additionally shifted depending on temperature. An embodiment is additionally provided with an acceleration transistor that dynamically switches. An example in which an additional capacitor is provided between the drain and gate of the acceleration transistor and the configuration of the bleeder resistor is changed will be described. An embodiment is shown in which the voltage divider and the transistor are alternatively configured separately. Another embodiment is shown in which the voltage divider and the inverter are alternatively configured separately. It is a figure which compares the required area of a well-known ESD protection circuit and the ESD protection circuit of this invention.

  As shown in detail in FIG. 1, a circuit 10 to be protected is connected between a first terminal 12 and a second terminal 14. The ESD protection circuit 16 is connected in parallel to the circuit 10 and has a voltage divider 18 composed of resistors 20 and 22. The potential adjusted to the intermediate tap 24 of the voltage divider 18 is supplied to the inverting input terminal of the operational amplifier 26. A bandgap reference voltage source 28 is connected between the second terminal 14 and the non-inverting input terminal of the operational amplifier 26. The output terminal of the operational amplifier 26 controls the gate G of the PMOS-ESD transistor 30, the source S is connected to the first terminal 12, and the drain D is connected to the second terminal 14.

  In the normal operating region, i.e. when the voltage level between the first terminal 12 and the second terminal 14 is acceptable, only a small current flows through the voltage divider 18. The resistors 20 and 22 are selected so that the potential of the intermediate tap 24 is lower than the potential of the band gap reference 28 in this case. As a result, the output signal of the operational amplifier 26 is positive, and the resistance of the PMOS-ESD transistor 30 is large. Therefore, the PMOS-ESD transistor 30 hardly acts electrically.

  When electrostatic discharge is generated at the first terminal 12, the voltage via the voltage divider 18 increases, and the potential of the intermediate tap 24 also increases. As a result, the potential difference between the input terminals of the operational amplifier 26, which was initially positive, becomes small or becomes negative. As a result, the output signal that was initially positive is similarly reduced or even negative. As a result, the conduction of the PMOS-ESD transistor 30 is controlled, and the electrostatic discharge generated at the first terminal 12 passes through the circuit 10 to be protected and flows to the second terminal 14 via the ESD transistor 30. The protection circuit equivalent to FIG. 1 uses an NMOS transistor instead of the PMOS transistor 30. Here, the inverting input terminal and the non-inverting input terminal of the operational amplifier 26 are interchanged.

  FIG. 2 shows in detail an ESD protection circuit 40 comprising a first terminal 12 and a second terminal 14. There is an ESD current path 42 between the first terminal 12 and the second terminal 14, and this current path is guided through the operating current section of the ESD transistor 44. The ESD transistor 44 is conduction controlled depending on the potential of the intermediate tap 46 of the voltage divider 48. The voltage divider is connected between the first terminal 12 and the second terminal 14. The ESD protection circuit 40 is characterized in that the ESD transistor 44 is controlled via a transistor 49. The transistor 49 is controlled by an inverter 50 having an inverted potential of the intermediate tap 46.

  The voltage divider 48 has two resistors 52, 54, or two groups 52, 54 consisting of individual resistors 56, 58, 60, 62. The resistor can be realized as an ohmic resistor or a diode.

  The inverter 50 has a CMOS transistor pair including an NMOS transistor 64 and a PMOS transistor 66. Each of these gate terminals is connected to the intermediate tap 46. The output terminal 58 of the inverter 50 is connected to the gate terminal of the transistor 49. The transistor 49 is connected in series with the bleeder resistor 70 between the first terminal 12 and the second terminal 14. The bleeder resistor 70 is between the current terminal of the transistor 49 and the second terminal 14. A gate terminal 45 between the transistor 49 and the bleeder resistor 70 is connected to the gate of the ESD transistor 44.

  In this embodiment, a dynamically switching ESD transistor 44 is used as the base for dynamic ESD protection. To supplement with static protection, active circuits are used rather than passively switching zener diodes. The active circuit includes a transistor 49 (here configured as a P-channel MOSFET) and an amplification inverter 50. The amplification inverter controls the conduction of the transistor 49 when the voltage divider 48 exceeds the switch voltage. In this voltage divider, a part of the individual path is replaced by a voltage stable diode.

  Its function is based on the amplification action of the inverter 50. Thereby, the space | interval between an operating voltage and a protection voltage can be shortened. If the supply voltage between the first terminal 12 and the second terminal 14 is less than the allowable operating voltage, the voltage divider 48 will maintain its intermediate tap 46 and the amplification inverter will still keep the transistor 49 switched off. The voltage value to be sent is sent out. In this case, the ESD transistor 44 is switched off and does not conduct or conducts very little. When a relatively large positive voltage is generated between the first terminal 12 and the second terminal 14, a value that causes the amplification inverter 50 to control the conduction of the transistor 49 is generated in the intermediate tap 46 of the voltage divider 48. As desired, the ESD transistor 44 is similarly controlled to conduct, and most of the electrostatic discharge generated at the first terminal 12 passes through the circuit 10 to be protected through the switched-on ESD transistor 44 and passes through the first one. 2 terminal 14.

  This embodiment is particularly characterized in that the distance between the operating voltage and the protective voltage is very small.

  Advantageously, only components are required that have reproducible electrical parameters and can be tested in the manufacturing process. This ensures long-term manufacturing certainty and possible technical compatibility.

  It is likewise advantageous that the protection voltage does not depend on the achievable Zener voltage. Thus, arbitrarily small values are possible with the voltage divider.

  Furthermore, this circuit is advantageous because it is basically suitable for ESD protection in both polarities of the ESD pulse. This is because the selection of components can be limited to elements that are manufactured with integrated diode pockets but do not have a parasitic error function at negative potentials.

  It is also advantageous to reduce the maximum voltage at which an ESD pulse is generated in the circuit 10 and the power induced in the circuit 10 by reducing the protection voltage that switches on the ESD transistor 44. This allows the use of relatively small “non-robust” components in the circuit 10 to be protected. As a result, the required area of the entire circuit composed of the circuit 120 to be protected and the ESD protection circuit 40 is further reduced, and the overall cost is correspondingly reduced.

  By proper selection of the two resistors 52, 54 of the voltage divider 48 or the two groups 52, 54 of individual resistors 56, 58, 60, 62, the temperature dependence can be minimized and thus The interval between the operating voltage and the protection voltage can be further reduced. For example, resistors 56 and 58 with temperature dependence compensated in the opposite direction can be used.

  An advantageous configuration is characterized in that the voltage divider is realized from components 56 and / or 58 and / or 60 and / or 62 of different materials. As a result, voltage dependency and temperature dependency can be minimized. In another configuration, voltage divider 48 or a portion thereof is supplemented by a diode or component with diode function for temperature compensation. As a component having a diode function, a bipolar transistor or a unipolar transistor, for example, a CMOS transistor in which a drain terminal and a gate terminal are short-circuited can be considered.

  The amplification inverter 50 must not have positive feedback. In the case of positive feedback, hysteresis may occur that causes an undesired static voltage state. Such undesired static voltage conditions are those in which the resulting lateral current is too small for switching off, but too large for a sustained load. Points A, B, and C indicate an interface to which the other configurations shown in FIGS. 5 and 6 can be connected.

  FIG. 3 shows an embodiment in which the amplification inverter 50 has its own supply voltage source 75.

  The terminal 76 of the inverter 50 is not directly connected to the second terminal 14 as in the embodiment of FIG. Instead, the terminal 76 is connected to the supply voltage source 75, and this supply voltage source 75 is connected between the first terminal 12 and the second terminal 14.

  Thereby, the supply voltage of the inverter 50 is derived from the ESD voltage pulse. As a result, the operating voltage and the protection voltage do not depend on the generally limited voltage range of the inverter 50. The potential of the second terminal 14 can be made smaller than the substrate voltage.

  Therefore, the embodiment of FIG. 3 is suitable for solving the third problem. As already mentioned, the third problem arises from the fact that conventional semiconductor technology is based on the use of integrated diode pockets, in which the individual components are separated from one another by PN junctions. Therefore, for an input terminal that can take a negative voltage value with respect to the substrate, the selection of connectable components that do not include such a PN junction is very limited.

  According to the embodiment of FIG. 3, the input for negative voltages can be provided in a selectable voltage range up to the technical limit. This advantage is obtained in addition to the advantages already mentioned in connection with the embodiment of FIG. The parasitic problem in the ESD transistor 44 can be considered to have solved the fourth problem as long as no further requirements are imposed on the ESD pulses of opposite polarities.

  FIG. 3a shows a specific configuration of the voltage source 75 of FIG. In this configuration, the voltage source 75 has a series circuit including a Zener diode 72 and an ohmic resistor 74 connected in the blocking direction. The Zener diode 72 and the ohmic resistor 74 are connected between the first terminal 12 and the second terminal 14 in this order. A terminal 76 of the inverter 50 is connected to an intermediate tap 78 between the resistor 74 and the Zener diode 72. As a result, the voltage that drops through the inverter 50 due to the positive charge of the first terminal 12 when ESD occurs is limited to the value of the conduction voltage of the Zener diode.

  FIG. 4 shows the relationship between the various voltages in the circuit 40 and the output voltage U_ver adjusted between the terminals 12 and 14. Here, the value U_ver on the horizontal axis corresponds to the voltage value of an unloaded voltage source that can be connected to the terminals 12 and 14. Here, for the understanding of the present invention, it can be assumed that the low value U_ver << U_s is the normal desired voltage value of the voltage source and the high value U_ver> U_s is due to ESD occurrence.

  When such a voltage source is connected to terminals 12 and 14 of circuit 40, the voltage developed between these terminals 12 and 14 depends on the ohmic internal resistance of the voltage source, as is well known.

  Taking the ideal voltage source as a hypothetical example, the internal resistance of the voltage source is zero. Therefore, the voltage between the terminals 12 and 14 corresponds to the source voltage of the voltage source, and this source voltage may take a high value when ESD occurs.

  The characteristic curve 81 shows the voltage U_ver between the terminals 12 and 14 of the circuit 40 for a virtual example. This voltage U_ver is generated by an ideal voltage source, that is, by an ESD pulse that delivers a current of arbitrary magnitude. The characteristic curve 81 has an inclination of 45 ° in this virtual boundary example, and the length value of the supply voltage value U_ver plotted on the horizontal axis is similarly mapped on the vertical axis.

  This property is actually undesirable. This is because the circuit 10 is destroyed when the ESD current and voltage are large. Rather, what is desirable is represented by a characteristic curve 86 that branches off from the characteristic curve 81.

  This characteristic curve 86 represents the voltage between the terminals 12 and 14 when ESD really occurs and the ESD transistor 44 is activated.

  The characteristic curve 80 shows the relationship between the voltage U_inv at the input end of the intermediate tap 46, that is, the inverter 50, and the supply voltage source U_ver between the terminals 12 and 14 when the ESD transistor 44 is not present. The characteristic curve 80 corresponds to the characteristic curve 81 if it is shifted additively by the forward voltage of the diodes 60 and 62. Therefore, the characteristic curve 80 is generated under the same assumption as the characteristic curve 81.

  A characteristic curve 83 represents a switch voltage necessary for switching the inverter at the input terminal of the inverter 50. This switch voltage is a first order approximation and occurs as an invariant component of the supply voltage U_ver. The voltage value U_min on the horizontal axis represents the supply voltage U_ver necessary for the correct function of the inverter 50.

  If the value of the supply voltage U_ver is less than U_0, the diodes 60 and 62 are still in the blocking state, so no current flows through the voltage divider 48. As soon as U_ver exceeds the forward voltage U_0 of the diodes 60 and 62, the current through the voltage divider 48 rises and the voltage at the intermediate tap 46 rises corresponding to the characteristic curve 80. The characteristic curve 80 first passes below the characteristic curve 83 of the required switch voltage.

  However, the characteristic curve 80 rises steeper than the characteristic curve 83 when the supply voltage U_ver further rises, so the two characteristic curves intersect at the value U_s of the supply voltage U_ver. At this intersection, the voltage at the intermediate tap 46 of the voltage divider 48 exceeds the switch voltage of the inverter 50 that depends on the supply voltage. PMOS 66 is blocked and NMOS 64 is switched on. Correspondingly, the gate potential of the PMOS 49 is determined by the potential of the lower terminal 14. The PMOS transistor 49 is switched on so that operating current can flow through the ESD transistor 44 via the ESD current path 42. The ESD transistor 44 limits the actual supply voltage U_ver by a corresponding lateral current. This prevents further increase of the supply voltage or at least greatly mitigates it.

  In an actual voltage supply unit having an ohmic internal resistance, the supply voltage corresponds to the characteristic curve 86. The voltage actually measurable at the intermediate tap 46 is represented by the characteristic curve branch 85. When the value U_s determined in advance on the horizontal axis is exceeded, the ESD transistor 44 is completely switched on. This value U_s corresponds to the supply voltage when the ESD protection function is turned on on the characteristic curve 86 having the value U_schutz.

  FIG. 4a differs from FIG. 4 by the addition of characteristic curves 82 and 84. FIG. These additional characteristic curves extend in parallel with the characteristic curve 80 shown as a solid line and represent a region of characteristic curve shift depending on temperature. The upper one-dot chain line 82 generally represents the course when the temperature is high, and the lower one-dot chain line 84 represents the course when the temperature is low. Correspondingly, the value of the supply voltage U_ver at which the ESD transistor 44 is switched on completely shifts upward when the temperature is low and downward when the temperature is high. As already mentioned, by properly selecting the components 56, 58, 60, 62, the difference between the characteristic curves 82 and 84 can be minimized.

  The lower value U_a represents the lower limit of the maximum allowable normal operating voltage of the circuit 10. Above U_a, the protection circuit 40 may already act depending on the temperature.

  The upper value U_m represents the upper limit of the maximum allowable normal operating voltage of the circuit 10. Above U_m, the protection circuit 40 operates reliably without depending on the temperature.

  However, these temperature dependences are smaller than in the prior art. Therefore, the value of the protection voltage U_schutz at which the ESD transistor 44 is completely switched on is closer to the operating region of the normal supply voltage of the circuit 10 than in the prior art.

  In the configuration according to FIG. 5, at least one acceleration transistor 47 that dynamically switches is additionally provided between the drain and gate of the ESD transistor 44. This can improve the dynamic characteristics. As used herein, the dynamic characteristic is understood to be the slope d / dU. That is, the increase rate of the supply voltage U_ver.

  The minimum transient of the ESD pulse required to switch on the ESD transistor 44 through its mirror capacitance is assisted by the acceleration transistor and is generally reduced. By increasing the dynamic characteristics, a small ESD transistor 44 can be used even if the ESD phenomenon is the same. This has the advantage of further reducing the required area.

  In another configuration, additional gate-source capacitance or additional gate-drain capacitance is provided for the ESD transformer 44. The additional gate-source capacitance reduces the dynamic characteristics while the additional gate-drain (mirror) capacitance increases the dynamic characteristics accordingly. By appropriately selecting the additional capacitance, the dynamic characteristics can be adapted to the application area of the circuit.

  As shown in FIG. 6, an additional capacitance 43 is provided between the drain and gate of the acceleration transistor 47 that enhances the dynamic characteristics, or between the gate and source, or between the gate and the second terminal 14. Can be connected. As another variant, an additional capacitance bleeder resistor 71 can be connected to the second terminal 14.

  Further advantageously, by controlling the transistor 49 completely, static ESD protection can be interrupted by replacing the inverter 50 or by adding only one digital function (nand / nor gate). This is advantageous when the device is measured or screened under overload for inspection and characterization.

  Further, by controlling the transistor 49 completely, a plurality of voltage dividers and / or inverter circuits can be used. The plurality of voltage dividers and / or inverter circuits function independently and are programmed to switch on and off. If selected appropriately, the spacing between the operating voltage and the protection voltage can be further reduced by using multiple voltage dividers and multiple amplifier circuits simultaneously.

  Furthermore, it is advantageous to configure the voltage divider so that it can be programmed and switched by simple digital control. Thereby, different protection voltages can be adjusted.

  The embodiment described so far includes diodes 60 and 62 in one branch 54 of the voltage divider 48, and includes a PMOS type inverter 50 and a transistor 49. In the configuration shown in FIG. 7, the other branch 52 of the voltage divider 48 is formed by one or more diodes. Further, in this configuration, an NMOS type transistor 49 is used. The function is equivalent to the target function of FIG.

  In the configuration shown in FIG. 8, the other branch path 52 of the voltage divider 48 is formed by a diode. The transistor 49 is a PMOS type. Inverter 50 is replaced by a digital buffer. This digital buffer usually consists of two inverters connected in series. This circuit has a steeper switching point, further reducing the spacing between the operating voltage and the protection voltage.

  FIG. 9 illustrates the area savings achieved by the present invention. The upper row shows the required area of the known ESD circuit 16. This area is relatively large due to the band gap reference 28 and the many transistors of the operational amplifier 26. Here, the size of each rectangle represents the required area of the circuit member to which it belongs. The required area of the known ESD circuit 16 is two to three times larger than the required area of the protection circuit 10.

  The lower row shows the required area of the ESD circuit 40 of the present invention. Here, area savings are achieved by not using a large area module, such as a bandgap reference and an operational amplifier, but instead using one inverter 50 and one transistor amplifier 49. As explained above, the ESD transistor 44 can also be made relatively small, which also saves area. Overall, the required area of the ESD protection circuit of the present invention is smaller than the required area of the circuit 10 to be protected. An important advantage of the present invention is that the area reduction advantage is not associated with a decrease in dynamic properties.

Claims (14)

An ESD protection circuit comprising a first terminal (12) and a second terminal (14), and an ESD current path (42) between the first terminal (12) and the second terminal (14) ( 40)
The ESD current path is led through the operating current section of the ESD transistor (44),
The ESD transistor (44) is controlled depending on the potential of the intermediate tap (46) of the voltage divider (48),
In the ESD protection circuit of the type in which the voltage divider is connected between the first terminal (12) and the second terminal (14),
The ESD transistor (44) is controlled via a transistor (49),
The ESD protection circuit according to claim 1, wherein the transistor (49) is controlled by an inverter 50 having an inversion potential of an intermediate tap (46). The ESD protection circuit according to claim 1,
The voltage divider (48) has two resistors (52, 54) or two groups (52, 54) consisting of individual resistors (56, 58, 60, 62),
An ESD protection circuit, wherein the resistor is realized as an ohmic resistor or a diode. The ESD protection circuit according to claim 1 or 2,
ESD protection circuit, characterized in that at least two resistors (56, 58) of the voltage divider (48) have temperature dependence compensated in opposite directions. The ESD protection circuit according to any one of claims 1 to 3,
An ESD protection circuit, wherein the voltage divider (48) or a part thereof has a diode or a component having a diode function for temperature compensation. In the ESD protection circuit according to any one of claims 1 to 4,
The voltage divider (48) has ohmic resistors (56, 58) and diodes (60, 62) made of different materials, which materials are voltage and temperature dependent of the ohmic resistors and diodes. Is selected to be at least partially compensated. The ESD protection circuit according to any one of claims 1 to 5,
An ESD protection circuit, wherein a diode or a component having a diode function used for temperature compensation is the voltage divider (48) or a part of the voltage divider. The ESD protection circuit according to claim 6,
An ESD protection circuit, wherein a bipolar transistor is used as a component having a diode function, or a CMOS transistor having a drain terminal and a gate terminal short-circuited as a unipolar transistor. The ESD protection circuit according to any one of claims 1 to 7,
An ESD protection circuit, wherein an output terminal (58) of the inverter (50) is connected to a gate terminal of the transistor (49). The ESD protection circuit according to any one of claims 1 to 8,
An ESD protection circuit, wherein the inverter (50) has a non-inverting function. The ESD protection circuit according to any one of claims 1 to 9,
An ESD protection circuit, characterized in that an additional gate-source capacitance or an additional gate-drain capacitance of the ESD transformer (44) is provided. The ESD protection circuit according to any one of claims 1 to 10,
An ESD protection circuit, wherein the inverter (50) has a unique voltage supply. The ESD protection circuit according to any one of claims 1 to 11,
The ESD protection circuit according to claim 1, wherein the ESD transistor (44) includes another transistor (47) for enhancing dynamic characteristics. The ESD protection circuit according to any one of claims 1 to 12,
The ESD protection circuit according to claim 1, wherein the ESD transistor (44) has a capacitance between the first terminal (12) and the gate terminal of the ESD transistor (44) in order to enhance dynamic characteristics. The ESD protection circuit according to any one of claims 1 to 13,
The ESD protection circuit according to claim 1, wherein the ESD transistor (44) has a capacitance between the second terminal (14) and the gate terminal of the ESD transistor (44) in order to reduce dynamic characteristics.

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