DE102009001642B4 - Temperature-compensated area-optimized ESD protection circuit - Google Patents

Abstract

ESD protection circuit (8) having a first terminal (1) and a second terminal (2), a working current path of an ESD transistor (25) lying between the first terminal (1) and the second terminal (2), wherein the ESD transistor (25) is driven in response to a potential at a center tap of a voltage divider (20) located between the first terminal (1) and the second terminal (2), wherein the ESD transistor (25) via an activation Transistor (23) is driven, which is controlled by a switching threshold transistor (47), which is controlled by the potential of the center tap (48) of the voltage divider (20), and that at the center tap (48) of the voltage divider (20) Temperature compensation circuit (38, 46) is mounted, wherein the temperature compensation circuit (38, 46) is realized by a Iptat ring current source (38).

Description

State of the art

The invention relates to an ESD protection circuit according to the preamble of claim 1.

ESD protection circuits protect a connected circuit from potentially destructive electrostatic discharges. The ESD protection circuits are usually placed next to the actual circuit together on the chip.

ESD protection circuits can be connected in series or parallel with the circuit to be protected. A series circuit arrangement with the features mentioned is known from US 5,465,188 A known. According to this document, an ESD transistor with a load to be protected against excessive currents is connected in series and is controlled by an operational amplifier which measures the voltage drop across the ESD transistor with the aid of a voltage divider and compares it with a reference voltage which is determined by a band gap. Reference is provided. The advantage of such a circuit is according to the US 5,465,188 A in a reduced sensitivity to temperature influences. Operational amplifiers and bandgap references each contain a plurality of transistors (eg, about 20). This results in a disadvantageous large area requirement of the known circuit.

From the not previously published font DE 10 2008 001368 A1 Reference is made to the prior art, an ESD protection circuit is known in which the space requirement of the ESD protection circuit can be reduced by the particular configuration compared to conventional ESD protection circuits.

The publication US 2006/0176 626 A1 discloses an ESD protection circuit that includes a transient triggering method and a voltage detection circuit to drive a MOSFET that represents the ESD power clamping.

The publication US 5,946,177 A describes an ESD protection circuit with a shunt device, an RC trigger circuit and an RC delay circuit.

The publication US 2005/0 275 031 A1 discloses an ESD protection circuit having a first MOSFET having a leakage current between a first input node of the circuit to be protected and a second node, and a second MOSFET having a switch connecting the two nodes.

The publication US 6 522 511 B1 describes an ESD protection circuit that can be used in an integrated circuit. The integrated circuit comprises a transistor, an inverter and an ESD detector.

Disclosure of the invention

Advantages of the invention

In contrast to the prior art can be achieved by the construction of the circuit according to the invention, a direct reduction of the influence of temperature, in particular on the tripping voltage.

Furthermore, with the present circuit, a smaller difference between the triggering voltage, above which flows an ESD current, and the short-term maximum allowable voltage, above which damage may occur, feasible.

In general, a reduction in the susceptibility to errors can also be achieved by the reduced number of components.

It is understood that the features mentioned above and those yet to be explained below can be used not only in the particular combination given, but also in other combinations or in isolation, without departing from the scope of the present invention.

list of figures

• 1 the protective circuit with a serial ESD protection circuit;
• 2 the protective circuit with a parallel ESD protection circuit;
• 3 the use of the ESD protection circuit as protection for inputs and outputs;
• 4 two circuits to be protected with only one ESD protection circuit;
• 5 splitting a parallel ESD protection circuit into static triggering, dynamic triggering and ESD transistor circuits;
• 6 a per se known circuit for static release, consisting of voltage divider, voltage reference and operational amplifier;
• 7 the circuit according to the invention of the ESD transistor for explaining the dynamic switching on;
• 8th a dynamic release circuit according to the invention;
• 9 the division of the circuit for the static triggering of the ESD contactor circuit according to the invention in the Iptat generator and threshold generator;
• 10 an example of execution too 9 ,

embodiment

An ESD current is triggered when the voltage at the gate of the ESD transistor (25) or via the gate leakage resistance (27) higher than its threshold voltage. In the static case, this requires the current through the activation transistor (23) be correspondingly large. This current is activated equivalently when its gate-source voltage difference between the point (49) and the first connection (1) exceeds the threshold voltage characteristic of this transistor. For this purpose, the corrector current of the switching threshold transistor (47) larger than that of the upper secondary current source transistor (45) given current. The base current required for this purpose is smaller by the current amplification factor β and becomes essential only when the base-emitter voltage Ube47 exceeds the temperature-dependent threshold voltage. The base-emitter voltage is proportional to the supply voltage Vdd and is calculated with negligible base current and still without consideration of the temperature compensation transistor (46) from the values of the resistances (21) and (22) : $$\mathrm{<figure-callout\; id="47"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U\; </figure-callout>}b{e}_{}{}_{47}=Vdd\cdot \frac{R_{22}}{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}$$

• Berechnung des Iptat - Ringstrom - Generators (38): $$I{\mathrm{<figure-callout\; id="42"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{42}=I{\mathrm{<figure-callout\; id="42"\; label="s"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">s</figure-callout>}}_{42}\cdot \left(e^{\frac{Ub{e}_{42}}{U_T}}-1\right)\Rightarrow U\mathrm{<figure-callout\; id="42"\; label="b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">b</figure-callout>}{e}_{}{}_{42}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{s}_{42}}\right)$$
  
  $$I{\mathrm{<figure-callout\; id="43"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{43}=I{\mathrm{<figure-callout\; id="43"\; label="s"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">s</figure-callout>}}_{43}\cdot \left(e^{\frac{Ub{e}_{43}}{U_T}}-1\right)\Rightarrow Ub{e}_{43}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{I{s}_{43}}\right)$$
  
  $$I{\mathrm{<figure-callout\; id="43"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{43}=m\cdot I{\mathrm{<figure-callout\; id="42"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{42}=m\cdot I{\mathrm{<figure-callout\; id="42"\; label="s"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">s</figure-callout>}}_{42}\cdot \left(e^{\frac{Ub{e}_{42}}{U_T}}-1\right)\Rightarrow Ub{e}_{42}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{m\cdot I{s}_{42}}\right)$$
  
  $$\mathrm{<figure-callout\; id="42"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}b{e}_{}{}_{42}=Ub{e}_{43}+\mathrm{<figure-callout\; id="44"\; label="U\; r"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}{r}_{}{}_{44}.$$
  
  $$U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{c}_{42}}\right)+U_T=U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{m\cdot I{s}_{42}}\right)+U_T+I{\mathrm{<figure-callout\; id="42"\; label="e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">e</figure-callout>}}_{42}\cdot R_{44}$$
  
  $$I{\mathrm{<figure-callout\; id="42"\; label="e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">e</figure-callout>}}_{42}=\frac{U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{s}_{42}}\right)-U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{m\cdot I{s}_{42}}\right)}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}$$
  
  $$I{\mathrm{<figure-callout\; id="42"\; label="e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">e</figure-callout>}}_{42}=\frac{U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{s}_{42}}\frac{m\cdot I{s}_{42}}{I{c}_{43}}\right)}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}$$
  
  $$I{\mathrm{<figure-callout\; id="42"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{42}=h\cdot I{\mathrm{<figure-callout\; id="43"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{43}$$
  
  $$I{\mathrm{<figure-callout\; id="42"\; label="e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">e</figure-callout>}}_{42}=\frac{U_T\cdot \text{ln}\left(h\cdot m\right)}{R_{44}}$$
  
  $$I{\mathrm{<figure-callout\; id="42"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{42}\cong I{e}_{42}$$
  
  $$I{\mathrm{<figure-callout\; id="46"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{46}=n\cdot I{\mathrm{<figure-callout\; id="42"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{42}\cong \frac{n\cdot U_T\cdot \text{ln}\left(h\cdot m\right)}{R_{44}}$$
  
  $$I{\mathrm{<figure-callout\; id="21"\; label="r"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">r</figure-callout>}}_{21}=I{\mathrm{<figure-callout\; id="46"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{46}+I{\mathrm{<figure-callout\; id="22"\; label="r"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">r</figure-callout>}}_{22}$$
  
  $$\frac{Vdd-U{r}_{22}}{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}}=\frac{n\cdot U_T\cdot \text{ln}\left(h\cdot m\right)}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}+\frac{U{r}_{22}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}$$
  
  $$Vdd=\frac{R_{21}}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(h\cdot m\right)+\frac{R_{21}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}\cdot \mathrm{<figure-callout\; id="22"\; label="U\; r"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}{r}_{}{}_{22}+\mathrm{<figure-callout\; id="22"\; label="U\; r"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}{r}_{}{}_{22}$$
  
  $$\mathrm{<figure-callout\; id="22"\; label="U\; r"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}{r}_{}{}_{22}=\mathrm{<figure-callout\; id="47"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}b{e}_{}{}_{47}$$
  
  $$Vdd=\frac{R_{21}}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(h\cdot m\right)+Ub{e}_{47}\left(\frac{R_{21}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}+1\right)$$
  
  $$\mathrm{<figure-callout\; id="47"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U</figure-callout>}b{e}_{}{}_{47}=\frac{Vdd\cdot R_{22}}{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}-\frac{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}\cdot R_{22}}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(h\cdot m\right)$$
  

The negative temperature response of -2mV / K of Ube47 is achieved by using the Iptate ring current generator (38) via the temperature compensation transistor. (46) compensates:

• Calculation of the Iptat Ring Current Generator (38) : $$I{c}_{42}=I{s}_{42}\cdot \left(e^{\frac{Ub{e}_{42}}{U_T}}-1\right)\Rightarrow Ub{e}_{42}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{s}_{42}}\right)$$
  
  $$I{c}_{43}=I{s}_{43}\cdot \left(e^{\frac{Ub{e}_{43}}{U_T}}-1\right)\Rightarrow Ub{e}_{43}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{I{s}_{43}}\right)$$
  
  $$I{c}_{43}=m\cdot I{c}_{42}=m\cdot I{s}_{42}\cdot \left(e^{\frac{Ub{e}_{42}}{U_T}}-1\right)\Rightarrow Ub{e}_{42}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{m\cdot I{s}_{42}}\right)$$
  
  $$Ub{e}_{42}=Ub{e}_{43}+U{r}_{44},$$
  
  $$U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{c}_{42}}\right)+U_T=U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{m\cdot I{s}_{42}}\right)+U_T+I{e}_{42}\cdot R_{44}$$
  
  $$I{e}_{42}=\frac{U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{s}_{42}}\right)-U_T\cdot \text{ln}\left(\frac{I{c}_{43}}{m\cdot I{s}_{42}}\right)}{R_{44}}$$
  
  $$I{e}_{42}=\frac{U_T\cdot \text{ln}\left(\frac{I{c}_{42}}{I{s}_{42}}\frac{m\cdot I{s}_{42}}{I{c}_{43}}\right)}{R_{44}}$$
  
  $$I{c}_{42}=H\cdot I{c}_{43}$$
  
  $$I{e}_{42}=\frac{U_T\cdot \text{ln}\left(H\cdot m\right)}{R_{44}}$$
  
  $$I{c}_{42}\cong I{e}_{42}$$
  
  $$I{c}_{46}=n\cdot I{c}_{42}\cong \frac{n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)}{R_{44}}$$
  
  $$I{r}_{21}=I{c}_{46}+I{r}_{22}$$
  
  $$\frac{Vdd-U{r}_{22}}{R_{21}}=\frac{n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)}{R_{44}}+\frac{U{r}_{22}}{R_{22}}$$
  
  $$Vdd=\frac{R_{21}}{R_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)+\frac{R_{21}}{R_{22}}\cdot U{r}_{22}+U{r}_{22}$$
  
  $$U{r}_{22}=Ub{e}_{47}$$
  
  $$Vdd=\frac{R_{21}}{R_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)+Ub{e}_{47}\left(\frac{R_{21}}{R_{22}}+1\right)$$
  
  $$Ub{e}_{47}=\frac{Vdd\cdot R_{22}}{R_{21}+R_{22}}-\frac{R_{21}\cdot R_{22}}{\left(R_{21}+R_{22}\right)\cdot R_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)$$
  

For h · m = 1, the second term is omitted, and Ube47 would only depend linearly on Vdd, but is still temperature-dependent. With the usual ignoring of the base current of the switching threshold transistor (47) one obtains the trip voltage exclusively dependent on the supply voltage Vdd:

$$U_T=\frac{k\cdot T}{e_o}$$

$$Vdd=n\cdot \frac{R_{21}}{R_{44}}\cdot \frac{k\cdot T}{e_o}\cdot \text{ln}\left(h\cdot m\right)+Ub{e}_{47}\left(\frac{R_{21}}{R_{22}}+1\right)$$

$$\frac{\partial Vdd}{\partial T}=n\cdot \frac{R_{21}}{R_{44}}\cdot \frac{k}{e_o}\cdot \text{ln}\left(h\cdot m\right)+\frac{\partial }{\partial T}Ub{e}_{47}\left(\frac{R_{21}}{R_{22}}+1\right)=0$$

$$\frac{\partial }{\partial T}Ub{e}_{47}\approx -2mV/K$$

$$n\cdot \frac{R_{21}}{R_{44}}\cdot \frac{k}{e_o}\cdot \text{ln}\left(h\cdot m\right)=2mV/K\left(\frac{R_{21}}{R_{22}}+1\right)$$

$$n\cdot \frac{R_{21}\cdot R_{22}}{\left(R_{21}+R_{22}\right)\cdot R_{44}}\cdot \frac{k}{e_o}\cdot \text{ln}\left(h\cdot m\right)=2mV/K$$

The supply voltage is therefore the sum of a term dependent on Ube47 with a positive temperature coefficient and a term dependent on Iptat current with a negative temperature Coefficients. By suitable choice of the resistance values, the threshold of the tripping voltage can be dimensioned independent of temperature: $$Vdd=\frac{R_{21}}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)+Ub{e}_{47}\left(\frac{R_{21}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}+1\right)$$

$$U_T=\frac{k\cdot T}{e_O}$$

$$Vdd=n\cdot \frac{R_{21}}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot \frac{k\cdot T}{e_O}\cdot \text{ln}\left(H\cdot m\right)+Ub{e}_{47}\left(\frac{R_{21}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}+1\right)$$

$$\frac{\partial Vdd}{\partial T}=n\cdot \frac{R_{21}}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot \frac{k}{e_O}\cdot \text{ln}\left(H\cdot m\right)+\frac{\partial }{\partial T}Ub{e}_{47}\left(\frac{R_{21}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}+1\right)=0$$

$$\frac{\partial }{\partial T}\mathrm{<figure-callout\; id="47"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U\; </figure-callout>}b{e}_{}{}_{47}\approx -2mV/K$$

$$n\cdot \frac{R_{21}}{{\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot \frac{k}{e_O}\cdot \text{ln}\left(H\cdot m\right)=2mV/K\left(\frac{R_{21}}{{\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}}+1\right)$$

$$n\cdot \frac{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}\cdot R_{22}}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot \frac{k}{e_O}\cdot \text{ln}\left(H\cdot m\right)=2mV/K$$

$$I{c}_{47}=j\cdot I{c}_{42}$$

$$Ub{e}_{47}=\frac{Vdd\cdot R_{22}}{R_{21}+R_{22}}-\frac{R_{21}\cdot R_{22}}{\left(R_{21}+R_{22}\right)\cdot R_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(h\cdot m\right)=U_T\cdot \text{ln}\left(\frac{I{c}_{47}}{I{s}_{47}}\right)=U_T\cdot \text{ln}\left(\frac{j\cdot I{c}_{42}}{I{s}_{47}}\right)$$

$$\frac{Vdd\cdot R_{22}}{\left(R_{21}+R_{22}\right)\cdot U_T}=\text{ln}\left(\frac{j\cdot I{c}_{42}}{I{s}_{47}}\right)+\frac{R_{21}\cdot R_{22}}{\left(R_{21}+R_{22}\right)\cdot R_{44}}\cdot n\cdot \text{ln}\left(h\cdot m\right)$$

$$U_T=\frac{k\cdot T}{e_o}$$

$$\frac{Vdd\cdot R_{22}\cdot e_o}{\left(R_{21}+R_{22}\right)\cdot k\cdot T}=\text{ln}\left(j\right)+\text{ln}\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+\frac{R_{21}\cdot R_{22}}{\left(R_{21}+R_{22}\right)\cdot R_{44}}\cdot n\cdot \text{ln}\left(h\cdot m\right)$$

$$Vdd=\frac{\left(R_{21}+R_{22}\right)\cdot k\cdot T}{R_{22}\cdot e_o}\text{ln}\left(j\right)+\frac{\left(R_{21}+R_{22}\right)\cdot k\cdot T}{R_{22}\cdot e_o}\text{ln}\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+\frac{k\cdot T\cdot R_{21}}{e_o\cdot R_{44}}\cdot n\cdot \text{ln}\left(h\cdot m\right)$$

$$\frac{\partial Vdd}{\partial T}=\frac{\left(R_{21}+R_{22}\right)\cdot k}{R_{22}\cdot e_o}\text{ln}\left(j\right)+\frac{\left(R_{21}+R_{22}\right)\cdot k}{R_{22}\cdot e_o}\text{ln}\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+\frac{k\cdot R_{21}}{e_o\cdot R_{44}}\cdot n\cdot \text{ln}\left(h\cdot m\right)=0$$

$$\left(R_{21}+R_{22}\right)\cdot R_{44}\cdot \text{ln}\left(j\right)+\left(R_{21}+R_{22}\right)\cdot {\text{R}}_{44}\cdot n\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+R_{21}\cdot R_{22}\cdot n\cdot \text{ln}\left(h\cdot m\right)=0$$

This type of circuit and its calculation is known and considered state of the art. $$I{c}_{47}=I{s}_{47}\cdot \left(e^{\frac{Ub{e}_{47}}{U_T}}-1\right)\Rightarrow \mathrm{<figure-callout\; id="47"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U\; </figure-callout>}b{e}_{}{}_{47}\cong U_T\cdot \text{ln}\left(\frac{I{c}_{47}}{I{c}_{47}}\right)$$

$$I{c}_{47}=j\cdot I{\mathrm{<figure-callout\; id="42"\; label="c"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">c</figure-callout>}}_{42}$$

$$\mathrm{<figure-callout\; id="47"\; label="U\; b\; e"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">U\; </figure-callout>}b{e}_{}{}_{47}=\frac{Vdd\cdot R_{22}}{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}}-\frac{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}\cdot R_{22}}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot U_T\cdot \text{ln}\left(H\cdot m\right)=U_T\cdot \text{ln}\left(\frac{I{c}_{47}}{I{s}_{47}}\right)=U_T\cdot \text{ln}\left(\frac{j\cdot I{c}_{42}}{I{s}_{47}}\right)$$

$$\frac{Vdd\cdot R_{22}}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot U_T}=\text{ln}\left(\frac{j\cdot I{c}_{42}}{I{s}_{47}}\right)+\frac{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}\cdot R_{22}}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot \text{ln}\left(H\cdot m\right)$$

$$U_T=\frac{k\cdot T}{e_O}$$

$$\frac{Vdd\cdot {\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}\cdot e_O}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot k\cdot T}=\text{ln}\left(j\right)+\text{ln}\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+\frac{{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}\cdot R_{22}}{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot \text{ln}\left(H\cdot m\right)$$

$$Vdd=\frac{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot k\cdot \mathrm{<figure-callout\; id="22"\; label="T\; R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">T\; </figure-callout>}}{R_{}}\text{ln}\left(j\right)+\frac{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot k\cdot \mathrm{<figure-callout\; id="22"\; label="T\; R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">T\; </figure-callout>}}{R_{}}\text{ln}\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+\frac{k\cdot T\cdot R_{21}}{e_O\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot \text{ln}\left(H\cdot m\right)$$

$$\frac{\partial Vdd}{\partial T}=\frac{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot \mathrm{<figure-callout\; id="22"\; label="k\; R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">k\; </figure-callout>}}{R_{}}\text{ln}\left(j\right)+\frac{\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot \mathrm{<figure-callout\; id="22"\; label="k\; R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">k\; </figure-callout>}}{R_{}}\text{ln}\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+\frac{k\cdot R_{21}}{e_O\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}}\cdot n\cdot \text{ln}\left(H\cdot m\right)=0$$

$$\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\mathrm{<figure-callout\; id="44"\; label="R"\; filenames="DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{44}\cdot \text{ln}\left(j\right)+\left({\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}+R_{22}\right)\cdot {\text{<figure-callout id="44" label="R" filenames="DE102009001642B4\_0041.png" state="{{state}}">R</figure-callout>}}_{44}\cdot n\left(\frac{I{c}_{42}}{I{s}_{47}}\right)+{\mathrm{<figure-callout\; id="21"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{21}\cdot {\mathrm{<figure-callout\; id="22"\; label="R"\; filenames="DE102009001642B4\_0038.png,DE102009001642B4\_0041.png"\; state="\{\{state\}\}">R</figure-callout>}}_{22}\cdot n\cdot \text{ln}\left(H\cdot m\right)=0$$

If the resistance values of R21, R22 and R44 are chosen so that this last formula holds, then the temperature response of the switching threshold transistor (47) compensated. Due to the steepness of the response of the circuit, the temperature dependence of the activation transistor drops (23) and the ESD transistor (25) then not particularly significant.

In detail, the shows 1 a circuit to be protected (7) that between a first connection (1) and a second port (2) which is an ESD protection circuit (6) is connected in series, here between the circuit to be protected (7) and the first connection (1) , This arrangement is in the US 5,465,188 A described.

This ESD protection circuit (6) causes an inadmissibly high voltage between the first connection when detecting (1) and the Second Connection (2) an increase in resistance between the first port (1) and the circuit to be protected (7) so that their permissible parameters are not exceeded in the ESD case.

In detail, the shows 2 a circuit to be protected (7) that between a first connection (1) and a second connection (2) which is an ESD protection circuit (8th) is arranged parallel to it. This arrangement is also used in the DE 102008001368 A1 described.

This ESD protection circuit (8th) causes an inadmissibly high voltage between the first connection when detecting (1) and the Second Connection (2) a reduction of the internal resistance between the first terminal (1) and the second port (2) so that an extra ESD current through the ESD protection circuit will reduce the voltage on the circuit being protected (7) not continue to increase or at least significantly weakened.

In the 3 is represented as by using the coupling diodes (9) and (10) a third connection (3) the circuit to be protected (7) on a shared ESD protection circuit (8th) can be switched.

In the ESD case, the ESD current flows from the third port (3) through one of the coupling diodes (9) or (10) either directly to one of the degrees (1) or (2) , or through the ESD protection circuit either to the other terminal (1) or (2) or via a further coupling diode (not shown here) to another terminal (also not shown, since the wiring of the third terminal equivalent).

In the 4 is represented as by using coupling fins (11) . (12) . (13) . (14) a second circuit to be protected (7a) the circuit to be protected (7) on a shared ESD protection circuit (8th) is switched. In this case, the coupling diodes (11) and (13) omitted when the first connection (1) with the fourth connection (4) is identical, as can the coupling diodes (12) and (14) omitted if the second connection (2) with the fifth connection (5) is identical.

In the ESD case between one of the connections (1) or (4) to one of the connections (2) or (5) the ESD current flows through one of the coupling diodes (9) or (10) via the ESD protection circuit (8th) and via one of the coupling diodes (12) or (14) , In all cases, the ESD current should be the voltages on the circuits to be protected (7) and (7a) to a still allowed values.

The 4 is not complete because only one direction of the ESD current is considered.

Specifically, there is the parallel ESD protection circuit (8th) as in 5 represented by a circuit for the static activation of the ESD current (15) , a circuit of the ESD current carrying the ESD transistor (16) and a circuit for additional dynamic activation of the ESD current (17) , All of these circuits are between the first port (1) and the second port (2) arranged and interconnected. Here is the connection between the circuits of static activation of the ESD current (15) and the circuitry for additional dynamic activation of the ESD stream (17) not mandatory. The activation output (24) the circuit (15) acts directly on the gate or base of the ESD transistor (26) , as well as the dynamic signal (31) the circuit (17) , In 5 are for wiring the ESD transistor (16) two separate gate or base connections (26) to illustrate the possibility of separating these two functions by two partial aspects of the circuit of the ESD transistor. In general, it is the same line.

The circuit for additional dynamic activation of the ESD current (17) can be omitted in many applications, since in general the circuit of the ESD transistor (16) already contains a dynamic activation. Otherwise the dynamic signal will work (31) in the case of ESD, directly to the gate or base connection (26) of the ESD transistor

In the ESD case, the high transient causes the voltage increase between the first connection (1) and the second port (2) a proper activation of the ESD transistor (16) via the circuit of the dynamic activation of the ESD current (17) via the activation line (24) directly to the gate or base line (26) of the ESD transistor. At a correspondingly slower voltage increase, the ESD transistor (16) when the tripping voltage is exceeded via the static activation circuit of the ESD current (15) activated.

The 6 describes an embodiment of the circuit for static activation of the ESD current (15) using a voltage divider (20) Using an Operations Amplifier (18) or a comparator (18) the voltage value between the first connection (1) and the second port (2) with a reference voltage source (19) compares and when the tripping voltage is exceeded, an activation signal (24) about turning on the activation transistor (23) generated.

As in 7 illustrated, there is the inventive circuit of the ESD transistor (16) mainly from an ESD transistor (25) , This is provided by a sufficiently high voltage level at its gate or base terminal (26) with respect to the second port (2) and causes an ESD current between the first port (1) and the second port (2) , A gate leakage resistor (27) prevents unwanted charging of the gate and thus unintentional switching on of the ESD transistor (25) , An additional gate-drain capacitance (28) increases the gate voltage with correspondingly high dynamics at the first connection (1) and increases the known as Miller capacitance already existing in the ESD transistor gate-drain capacitance. An additional capacity (29) parallel to the already existing in the ESD transistor gate - source capacitance reduces the dynamic sensitivity accordingly.

Both on the additional gate-drain capacitance (28) as well as the additional gate-source capacitance (29) can be omitted, especially as appropriate parameters of the ESD transistor (25) already known. Using these additional capacitances reduces the dependence on technological variations in the fabrication of the ESD transistor (25) ,

A circuit according to the invention for the additional dynamic activation of the ESD current (17) is in 8th shown. In a first approximation, it is comparable to the circuit of the ESD transistor (16) and consists of an acceleration transistor (30) each with an additional gate-drain capacitance (33) , an additional gate-source capacitance (34) and a gate-to-source leakage resistor (36) , The difference to the circuit of the ESD transistor lies mainly in the use of the source terminal of the acceleration transistor, which serves as a dynamic line (31) to the gate or base terminal of the ESD transistor (26) is directed. Furthermore, an additional gate-ground capacity (35) the function of gate-source capacitance (34) support.

Due to the increased voltage transient in the ESD case, the acceleration transistor experiences (30) via the parallel connection of its Miller capacitance with the additional gate-drain capacitance (33) an activation and thus switches with respect to the second port (2) increased voltage on the dynamics line (31) , This is connected to the gate or base terminal of the ESD transistor (26) connected and switches this, so that the intended ESD - flow can flow.

Alternatively or in addition to the gate-source leakage resistor (36) can be a gate-ground leakage resistor (37) to be used with the same function.

Both on the additional gate-drain capacitance (33) as well as the additional gate-source capacitance (34) as well as the extra gate-ground capacity (35) can be omitted, especially as appropriate parameters of the acceleration transistor (30) already known. Using these additional capacities reduces the dependence on technological variations in the production of the acceleration transistor (30) ,

An alternative or additional use of the circuit for additional dynamic activation of the ESD current (17) takes place as an amplifier, whereby the static activation of the ESD transistor (25) instead of the gate or base terminal of the ESD transistor (26) over the gate or base terminal of the acceleration transistor (30) he follows. Here, the acceleration transistor act (30) together with the ESD transistor (25) similar to a Darlington transistor with correspondingly greater current amplification.

On the functional use of the circuit for additional dynamic activation of the ESD current (17) can be omitted if already the dynamics of the ESD transistor (16) is sufficient to activate the desired ESD current in the ESD case.

In detail, the shows 9 the invention the division of the circuit for the static activation of the ESD - current (15) into a Iptate ring current generator (38) , a threshold generator (39) and an activation transistor (23) , which is an activation signal (24) generated. This will generally be with the gate or base terminal of the ESD transistor (26) connected, alternatively to the gate or base terminal of the acceleration transistor (32) , Both the Iptate ring current generator (38) , as well as the threshold generator (39) are directly between the first connection (1) and the second connection (2) connected and thereby receive their power supply.

An embodiment of the circuit for the static activation of the ESD current (15) is in the 10 shown. The Iptate ring current generator (38) is here by the components (40) . (41) . (42) . (43) and (44) formed, the threshold generator (39) through the components (21) . (22) . (45) . (46) and (47) , The first current source transistor (40) forms a current source whose current value is the lower current mirror reference (42) receives. With the self-adjusting reference voltage, the current mirror transistor (43) driven. The one by the reference resistance (44) limited current through the current mirror transistor (43) goes to the current source reference transistor (41) in turn, as a reference for the current source transistor (40) serves. This circuit with the feedback control in this way to a reference current is known in the literature as a ring current source.

The start-up capacitor (50) is only optional and helps with suitable dimensioning in the ESD case to a faster settling of the current reference of the Iptat ring current generator (38) , Additionally or alternatively, for the same purpose, an alternative starting capacitor (51) parallel to current mirror transistor (43) and reference resistance (44) to be ordered.

In the threshold generator (39) becomes a switching threshold transistor (47) operated as an emitter circuit, wherein the transistor (45) acts as a current source at the collector. The base voltage is through a voltage divider (20) formed from a positive branch (21) and a negative branch (22) consists. The parallel to the negative branch of the voltage divider (22) switching transistor (46) forms a current source, which determines the temperature dependence of the switching threshold transistor (47) compensated. By suitable choice of the ratio ratios of the power source (40) opposite the upper power source reference (41) and the ratio of the current sources (43) and (46) opposite to the lower current mirror reference (42) Also, the temperature influence on both the activation transistor (23) be minimized as well as that of the ESD transistor ( 25 ) and possibly on the amplifier transistor connected as an acceleration (30) ,

The activation transistor (23) then starts to conduct when the voltage difference between the first port (1) and the Second Connection (2) gets so big, that over the voltage divider (20) a sufficiently high base-emitter voltage for switching the switching threshold transistor (47) is produced.

Not shown separately is the possibility for reasons of accuracy to assemble the components used in each case from several individual components.

Not shown separately is the possibility of further increasing the accuracy by further components, whereby parameter dependencies of the components already described further reduced or compensated.

Not shown separately is the possibility to replace the transistors of the P-MOS type used in the embodiments by transistors of the PNP type.

The possibility of replacing the NPN-type transistors used in the exemplary embodiments by transistors of the N-MOS type is not shown separately.

LIST OF REFERENCE NUMBERS

(1)

Erster Anschluss; Positive Versorgungsspannung der zu schützenden Schaltung.

(2)

Zweiter Anschluss; Negative Versorgungsspannung der zu schützenden Schaltung.

(3)

Dritter Anschluss; Weitere Anschlüsse (Ein- oder Ausgangs-Signale) der zu schützenden Schaltung.

(4)

Vierter Anschluss; Positive Versorgungsspannung der zweiten zu schützenden Schaltung.

(5)

Fünfter Anschluss; Negative Versorgungsspannung der zweiten zu schützenden Schaltung.

(6)

ESD- Schutz-Schaltung in serieller Anordnung.

(7)

Zu schützende Schaltung.

(7a)

Zweite zu schützende Schaltung.

(8)

ESD - Schutz-Schaltung in paralleler Anordnung.

(9)

Positive Koppeldiode vom Dritten Anschluss zur ESD - Schutz-Schaltung.

(10)

Negative Koppeldiode vom Dritten Anschluss zur ESD - Schutz-Schaltung.

(11)

Positive Koppeldiode vom Ersten Anschluss zur ESD - Schutz-Schaltung.

(12)

Negative Koppeldiode vom Zweiten Anschluss zur ESD - Schutz-Schaltung.

(13)

Positive Koppeldiode vom Vierten Anschluss zur ESD - Schutz-Schaltung.

(14)

Negative Koppeldiode vom Fünften Anschluss zur ESD - Schutz-Schaltung.

(15)

Schaltung zur statischen Aktivierung des ESD - Stromes.

(16)

Schaltung des ESD - Transistors.

(17)

Schaltung zur zusätzlichen dynamischen Aktivierung des ESD - Stromes.

(18)

Operationsverstärker oder Komparator.

(19)

Referenzspannungs-Quelle.

(20)

Spannungsteiler.

(21)

Positiver Zweig des Spannungsteilers.

(22)

Negativer Zweig des Spannungsteilers.

(23)

Aktivierungs-Transistor.

(24)

Aktivierungs-Leitung beziehungsweise Aktivierungs-Signal.

(25)

ESD - Transistor.

(26)

Gate- oder Basis-Anschluss des ESD - Transistors.

(27)

Gate-Ableit-Widerstand des ESD - Transistors.

(28)

Zusätzliche Gate-Drain-Kapazität („Miller“-Kapazität) des ESD - Transistors.

(29)

Zusätzliche Gate-Source-Kapazität des ESD - Transistors.

(30)

Beschleunigungs-Transistor.

(31)

Dynamik-Leitung beziehungsweise Dynamik-Signal.

(32)

Gate- oder Basis-Anschluss des Beschleunigungs-Transistors.

(33)

Zusätzliche Gate-Drain-Kapazität („Miller“-Kapazität) des Beschleunigungs-Transistors.

(34)

Zusätzliche Gate-Source-Kapazität des Beschleunigungs-Transistors.

(35)

Zusätzliche Gate-Ground-Kapazität des Beschleunigungs-Transistors.

(36)

Gate-Source-Ableit-Widerstand des Beschleunigungs-Transistors:

(37)

Gate-Ground-Ableit-Widerstand des Beschleunigungs-Transistors.

(38)

Iptat - Ringstrom - Generator (positiver temperaturproportionaler Strom).

(39)

Schwellgenerator.

(40)

Erster Stromquellen-Transistor.

(41)

Obere Stromquellen-Referenz.

(42)

Untere Stromspiegel- Referenz.

(43)

Stromspiegel-Transistor.

(44)

Referenz-Widerstand.

(45)

Zweiter Stromquellen-Transistor.

(46)

Temperatur - Kompensations - Transistor.

(47)

Schaltschwellen-Transistor.

(48)

Mittelanzapfung des Spannungsteilers (20).

(49)

Ausgang des Iptat - Ringstrom - Generators.

(50)

Anlauf- Kondensator.

(51)

Alternativer Anlauf- Kondensator.

List of used terms:

(1)

First connection; Positive supply voltage of the circuit to be protected.

(2)

Second connection; Negative supply voltage of the circuit to be protected.

(3)

Third connection; Other connections (input or output signals) of the circuit to be protected.

(4)

Fourth connection; Positive supply voltage of the second circuit to be protected.

(5)

Fifth connection; Negative supply voltage of the second circuit to be protected.

(6)

ESD protection circuit in serial arrangement.

(7)

Protected circuit.

(7a)

Second circuit to be protected.

(8th)

ESD protection circuit in parallel arrangement.

(9)

Positive coupling diode from the third connection to the ESD protection circuit.

(10)

Negative coupling diode from the third connection to the ESD protection circuit.

(11)

Positive coupling diode from the first connection to the ESD protection circuit.

(12)

Negative coupling diode from the second connection to the ESD protection circuit.

(13)

Positive coupling diode from the fourth connection to the ESD protection circuit.

(14)

Negative coupling diode from the fifth connection to the ESD protection circuit.

(15)

Circuit for the static activation of the ESD current.

(16)

Circuit of the ESD transistor.

(17)

Circuit for additional dynamic activation of the ESD current.

(18)

Operational amplifier or comparator.

(19)

Reference voltage source.

(20)

Voltage divider.

(21)

Positive branch of the voltage divider.

(22)

Negative branch of the voltage divider.

(23)

Activation transistor.

(24)

Activation line or activation signal.

(25)

ESD transistor.

(26)

Gate or base terminal of the ESD transistor.

(27)

Gate leakage resistance of the ESD transistor.

(28)

Additional gate-drain capacitance ("Miller" capacitance) of the ESD transistor.

(29)

Additional gate-source capacitance of the ESD transistor.

(30)

Acceleration transistor.

(31)

Dynamic line or dynamic signal.

(32)

Gate or base terminal of the acceleration transistor.

(33)

Additional gate-drain capacitance ("Miller" capacitance) of the acceleration transistor.

(34)

Additional gate-source capacitance of the acceleration transistor.

(35)

Additional gate-ground capacitance of the acceleration transistor.

(36)

Gate-source leakage resistance of the acceleration transistor:

(37)

Gate-ground leakage resistor of the acceleration transistor.

(38)

Iptate Ring Current Generator (Positive Temperature Proportional Current).

(39)

Threshold generator.

(40)

First current source transistor.

(41)

Upper power source reference.

(42)

Lower current mirror reference.

(43)

Current mirror transistor.

(44)

Reference resistor.

(45)

Second current source transistor.

(46)

Temperature compensation transistor.

(47)

Switching threshold transistor.

(48)

Center tap of the voltage divider (20) ,

(49)

Output of the Iptat Ring Current Generator.

(50)

Starting capacitor.

(51)

Alternative start-up capacitor.

List of used variables:

β

Current amplification factor of the switching threshold transistor (47) ,

eo

Electron charge 1.602 • 10 ^-19 As.

IC42

Collector current of the transistor of the lower current mirror reference (42) ,

IC43

Collector current of the current mirror transistor (43) ,

Ic46

Collector current of the transistor (46) ,

Ie42

Emitter current of the transistor (42) ,

Ir21

Current through the resistor (21) ,

Ir22

Current through the resistor (22) ,

Is42

Saturation current of the transistor of the lower current mirror reference (42) ,

Is43

Saturation current of the current mirror transistor (43) ,

H

Size ratio of the transistor (40) to the transistor (41) ,

j

Size ratio of the transistor (45) to the transistor (41) ,

k

Boltzmann constant 1.3803 • 10 ^-23 VAs / K.

m

Size ratio of the transistor (43) to the transistor (42) ,

n

Size ratio of the transistor (46) to the transistor (42) ,

R21

Resistance value of the positive branch (21) of the voltage divider (20) ,

R22

Resistance value of the negative branch (22) of the voltage divider (20) ,

R44

Resistance value of the reference resistor (44) , TS junction temperature of the transistor in Kelvin.

Ube42

Base-emitter voltage difference of the transistor (42) ,

Ube43

Base-emitter voltage difference of the transistor (43) ,

Ube47

Base-emitter voltage difference of the switching threshold transistor (47) ,

Ur22

Voltage drop at the resistor (22) ,

Ur44

Voltage drop at the reference resistor (44) ,

U49

Voltage value at the output (49) of the Iptate ring current generator with respect to (2).

Ut

Temperature voltage Ut = k • T / eo.

Vdd

Supply voltage or voltage difference between (1)

and

(2).

Claims (10)

ESD protection circuit (8) having a first terminal (1) and a second terminal (2), a working current path of an ESD transistor (25) lying between the first terminal (1) and the second terminal (2), wherein the ESD transistor (25) is driven in response to a potential at a center tap of a voltage divider (20) located between the first terminal (1) and the second terminal (2), wherein the ESD transistor (25) via an activation Transistor (23) is driven, which is controlled by a switching threshold transistor (47), which is controlled by the potential of the center tap (48) of the voltage divider (20), and that at the center tap (48) of the voltage divider (20) Temperature compensation circuit (38, 46) is mounted, wherein the temperature compensation circuit (38, 46) is realized by a Iptat ring current source (38). ESD protection circuit (8) according to Claim 1 , characterized in that the ESD transistor is driven via an acceleration transistor (30), which is driven by the activation transistor (23). ESD protection circuit (8) according to one of the preceding claims, characterized by a supplement of the ESD transistor (25) with further acceleration transistors (30) for increasing the dynamics. ESD protection circuit (8) according to Claim 3 characterized by supplementing the further acceleration transistors (30) with a capacitance (33) between the first terminal (1) and the gate or base terminal of the acceleration transistor (30) to increase the dynamics. ESD protection circuit (8) according to Claims 3 or 4 characterized by supplementing the further acceleration transistors (30) with a capacitance (34) between the gate or base terminal of the acceleration transistor (30) and the dynamic line (31) to reduce the dynamics. ESD protection circuit (8) according to one of Claims 3 . 4 or 5 characterized by supplementing the further acceleration transistors (30) with a capacitance (35) between the gate or base terminal of the acceleration transistor (30) and the second terminal (2) for reducing the dynamics. ESD protection circuit (8) according to one of the preceding claims, characterized by a supplement of the ESD transistor (25) with a capacitance (29) between the gate or base terminal of the ESD transistor (25) and the second terminal (2 ) to reduce the dynamics. ESD protection circuit (8) according to one of the preceding claims, characterized by a supplement of the ESD transistor (25) with a capacitance (28) between the first terminal (1) and the gate or base terminal of the ESD transistor (25 ) to increase the dynamics. ESD protection circuit (8) according to one of the preceding claims, characterized in that the voltage divider (20) has two resistors (21, 22) which are realized as ohmic resistors. ESD protection circuit (8) according to one of the preceding claims, characterized in that the voltage divider (20) contains at least one intervention with which the resistance value of at least one of the partial resistors (21, 22) can be changed.

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