DE102009001642A1 - Electrostatic discharge protection device has two connections, where electrostatic discharge transistor is controlled by activation-transistor - Google Patents

Abstract

The electrostatic discharge (ESD) protection circuit (6) has two connections (1,2) and an operating current path of an ESD-transistor located between the two connections. The ESD-transistor is controlled by an activation-transistor controlled by a switching threshold-transistor. The activation-transistor is controlled by the potential of a center tap of a voltage divider.

Description

State of the art

The The invention relates to an ESD protection circuit according to Preamble of claim 1.

ESD protection circuits potentially protect a circuit connected to it destructive electrostatic discharges. It will be the ESD protection circuits usually beside the actual Circuit placed together on the chip.

ESD protection circuits can be connected in series or parallel with the circuit to be protected. A series circuit arrangement with the features mentioned is known from US 5,465,188 known. According to this document, an ESD transistor with a load to be protected against excessive currents is connected in series and is controlled by an operational amplifier, which measures the voltage drop across the ESD transistor with the aid of a voltage divider and compares it with a reference voltage which is supplied by a bandgap. Reference is provided. The advantage of such a circuit is according to the US 5,465,188 in a reduced sensitivity to temperature influences. Operational amplifiers and bandgag references each include a plurality of transistors (eg, about 20). This results in a disadvantageous large area requirement of the known circuit.

From the not previously published font DE 10 2008 001368 A1 Reference is made to the prior art, an ESD protection circuit is known in which the space requirement of the ESD protection circuit can be reduced by the particular configuration compared to conventional ESD protection circuits.

Disclosure of the invention

Advantages of the invention

in the Contrary to the prior art can by the inventive Construction of the circuit a direct reduction of the temperature influence in particular to the trigger voltage can be achieved.

Farther is with the present circuit a smaller difference between the trip voltage above which an ESD current flows and the short-term maximum allowable voltage, above the one Damage may occur, feasible.

Generally can also be reduced by the reduced number of components the error susceptibility can be achieved.

It it is understood that the above and the following yet to be explained features not only in each case specified combination, but also in other combinations or can be used in isolation, without the scope of the present To leave invention.

drawings

1 the protective circuit with a serial ESD protection circuit;

2 the protective circuit with a parallel ESD protection circuit;

3 the use of the ESD protection circuit as protection for inputs and outputs;

4 two circuits to be protected with only one ESD protection circuit;

5 splitting a parallel ESD protection circuit into static triggering, dynamic triggering, and ESD transistor circuits;

6 a per se known circuit for static release, consisting of voltage divider, voltage reference and operational amplifier;

7 the shading of the ESD transistor to explain the dynamic switching;

8th a circuit of dynamic triggering;

9 the division of the circuit for the static triggering of the ESD protection circuit according to the invention in Iptat generator and Schwellgenerator;

10 an example of execution too 9 ,

embodiment

An ESD current is triggered when the voltage at the gate of the ESD transistor ( 25 ) or via the gate-leakage resistor ( 27 ) is higher than its threshold voltage. In the static case, this requires the current through the activation transistor ( 23 ) be correspondingly large. This current is activated equivalently when its gate-source voltage difference between the point ( 49 ) and the first connection ( 1 ) exceeds the threshold voltage characteristic of this transistor. For this, the corrector current of the switching threshold transistor ( 47 ) greater than that of the upper secondary current source transistor ( 45 ) predetermined current. The base current required for this purpose is smaller by the current amplification factor β and becomes essential only when the base-emitter voltage Ube47 exceeds the temperature-dependent threshold voltage. The base-emitter voltage is proportional to the supply voltage Vdd and is calculated with negligible base current and still without consideration of the temperature compensation transistor ( 46 ) from the values of the resistances ( 21 ) and ( 22 ):

The negative temperature response of -2 mV / K of Ube47 is achieved by using the Iptate ring current generator ( 38 ) via the temperature compensation transistor ( 46 ) compensates: Calculation of the Iptate Ring Current Generator (38):

For h · m = 1, the second term is omitted, and Ube47 would only depend linearly on Vdd, but is still temperature-dependent. With the usual ignoring of the base current of the switching threshold transistor ( 47 ) one receives the tripping voltage exclusively from the supply voltage Vdd dependent:
The supply voltage is therefore the sum of a Ube47-dependent term with a positive temperature coefficient and a term dependent on Iptat current with a negative temperature coefficient. By suitable choice of the resistance values, the threshold of the tripping voltage can be dimensioned independent of temperature:

These Type of circuit and its calculation is known and considered as state of the technique.

If the resistance values of R21, R22 and R44 are chosen so that this last formula holds, then the temperature response of the switching threshold transistor ( 47 ) compensated. Due to the steepness of the response of the circuit, the temperature dependence of the activation transistor ( 23 ) and the ESD transistor ( 25 ) then no longer particularly significant.

In detail, the shows 1 a circuit to be protected ( 7 ) between a first port ( 1 ) and a second connection ( 2 ), wherein an ESD protection circuit ( 6 ) is connected in series, here between the circuit to be protected ( 7 ) and the first connection ( 1 ). This anord will be in the US 5,3465,188 described.

This ESD protection circuit ( 6 ) causes an inadmissibly high voltage between the first terminal ( 1 ) and the Second Connection ( 2 ) an increase in resistance between the first terminal ( 1 ) and the circuit to be protected ( 7 ) so that their permissible parameters are not exceeded in the ESD case.

In detail, the shows 2 a circuit to be protected ( 7 ) between a first port ( 1 ) and a second connection ( 2 ), wherein an ESD protection circuit ( 8th ) is arranged parallel thereto. This arrangement is also described in R.319249.

This ESD protection circuit ( 8th ) causes an inadmissibly high voltage between the first terminal ( 1 ) and the Second Connection ( 2 ) a reduction of the internal resistance between the first terminal ( 1 ) and the second connection ( 2 ), so that an additional ESD current through the ESD protection circuit, the voltage at the circuit to be protected ( 7 ) does not continue to increase or at least significantly weakened.

In the 3 is represented as by using the coupling diodes ( 9 ) and ( 10 ) a third connection ( 3 ) of the circuit to be protected ( 7 ) on a shared ESD protection circuit ( 8th ) can be switched.

In the ESD case, the ESD current flows from the third terminal ( 3 ) by one of the coupling diodes ( 9 ) or ( 10 ) either directly to one of the degrees ( 1 ) or ( 2 ) or by the ESD protection circuit either to the other terminal ( 1 ) or ( 2 ) or via a further coupling diode (not shown here) to another terminal (also not shown, since the wiring of the third terminal equivalent).

In the 4 is represented as by using coupling diodes ( 11 ) 12 ) 13 ) 14 ) a second circuit to be protected ( 7a ) of the circuit to be protected ( 7 ) on a shared ESD protection circuit ( 8th ) is switched. The coupling diodes ( 11 ) and ( 13 ) are omitted if the first connection ( 1 ) with the fourth connection ( 4 ) is identical, likewise the coupling diodes ( 12 ) and ( 14 ) are omitted when the second port ( 2 ) with the fifth connection ( 5 ) is identical.

In the ESD case between one of the connections ( 1 ) or ( 4 ) to one of the connections ( 2 ) or ( 5 ), the ESD current flows through one of the coupling diodes ( 9 ) or ( 10 ) via the ESD protection circuit ( 8th ) and via one of the coupling diodes ( 12 ) or ( 14 ). In all cases, the ESD current should be the voltages at the circuits to be protected ( 7 ) and ( 7a ) to a still permitted value.

The 4 is not complete because only one direction of the ESD current is considered.

Specifically, the parallel ESD protection circuit ( 8th ) as in 5 represented by a circuit for the static activation of the ESD current ( 15 ), a circuit of the ESD current carrying the ESD transistor ( 16 ) and a circuit for additional dynamic activation of the ESD stream ( 17 ). All of these circuits are between the first port ( 1 ) and the second connection ( 2 ) arranged and interconnected. In this case, the connection between the circuits of the static activation of the ESD stream ( 15 ) and the circuit of additional dynamic activation of the ESD stream ( 17 ) not mandatory. The activation output ( 24 ) of the circuit ( 15 ) acts directly on the gate or base of the ESD transistor ( 26 ), as well as the dynamic signal ( 31 ) of the circuit ( 17 ). In 5 are for wiring the ESD transistor ( 16 ) two separate gate or base terminals ( 26 ) to illustrate the possibility of separating these two functions by two partial aspects of the circuit of the ESD transistor. In general, it is the same line.

The circuit for additional dynamic activation of the ESD stream ( 17 ) can be omitted in many applications, since in general the circuit of the ESD transistor ( 16 ) already contains a dynamic activation. Otherwise, the dynamic signal ( 31 ) in the ESD case directly to the gate or base terminal ( 26 ) of the ESD transistor

In the ESD case, the high transient causes the voltage increase between the first terminal ( 1 ) and the second connection ( 2 ) a proper activation of the ESD transistor ( 16 ) via the circuit of the dynamic activation of the ESD current ( 17 ) via the activation line ( 24 ) directly to the gate or base line ( 26 ) of the ESD transistor. With a correspondingly slower voltage the ESD transistor ( 16 ) when the tripping voltage is exceeded via the static activation circuit of the ESD current ( 15 ) is activated.

The 6 describes an embodiment of the circuit for the static activation of the ESD current ( 15 ) using a voltage divider ( 20 ) using an operational amplifier ( 18 ) or a comparator ( 18 ) the voltage value between the first terminal ( 1 ) and the second connection ( 2 ) with a reference voltage source ( 19 ) and when the tripping voltage is exceeded, an activation signal ( 24 ) via the activation of the activation transistor ( 23 ) generated.

As in 7 shown, consists of the circuit of the ESD transistor ( 16 ) mainly of an ESD transistor ( 25 ). This is caused by a sufficiently high voltage level at its gate or base terminal ( 26 ) with respect to the second terminal ( 2 ) and causes an ESD current between the first port ( 1 ) and the second connection ( 2 ). A gate leakage resistor ( 27 ) prevents unwanted charging of the gate and thus unintentional switching on of the ESD transistor ( 25 ). An additional gate-drain capacitance ( 28 ) increases the gate voltage with correspondingly high dynamics at the first terminal ( 1 ) and increases the known as Miller capacitance already in the ESD transistor physical existing gate-drain capacitance. An additional capacity ( 29 ) parallel to the already existing in the ESD transistor gate-source capacitance reduces the dynamic sensitivity accordingly.

Both on the additional gate-drain capacitance ( 28 ) as well as the additional gate-source capacitance ( 29 ) can be omitted, especially since corresponding parameters from the ESD transistor ( 25 ) are already known. Using these additional capacities reduces the dependence on technological variations in the production of the ESD transistor ( 25 ).

A circuit for additional dynamic activation of the ESD current ( 17 ) is in 8th shown. It is comparable in first approximation with the circuit of the ESD transistor ( 16 ) and consists of an acceleration transistor ( 30 ) with associated additional gate-drain capacitance ( 33 ), an additional gate-source capacitance ( 34 ) and a gate-source leakage resistor ( 36 ). The difference to the circuit of the ESD transistor lies mainly in the use of the source terminal of the acceleration transistor, which is used as a dynamic line ( 31 ) to the gate or base terminal of the ESD transistor ( 26 ). Furthermore, an additional gate-ground capacitance ( 35 ) the function of the gate-source capacitance ( 34 ) support.

Due to the increased voltage transient in the ESD case, the acceleration transistor ( 30 ) via the parallel connection of its Miller capacitance with the additional gate-drain capacitance ( 33 ) activates and thus switches with respect to the second terminal ( 2 ) increased voltage on the dynamic line ( 31 ). This is connected to the gate or base terminal of the ESD transistor ( 26 ) and switches it, so that the intended ESD current can flow.

Alternatively or in addition to the gate-source leakage resistor ( 36 ), a gate-ground leakage resistor ( 37 ) with the same function.

Both on the additional gate-drain capacitance ( 33 ) as well as the additional gate-source capacitance ( 34 ) as well as the additional gate-ground capacitance ( 35 ) can be omitted, especially since corresponding parameters from the acceleration transistor ( 30 ) are already known. Use of these additional capacities reduces the dependence on technological variations in the production of the acceleration transistor ( 30 ).

An alternative or additional use of the circuit for additional dynamic activation of the ESD current ( 17 ) takes place as an amplifier, wherein the static activation of the ESD transistor ( 25 ) instead of the gate or base terminal of the ESD transistor ( 26 ) across the gate or base terminal of the acceleration transistor ( 30 ) he follows. Here, the acceleration transistor ( 30 ) together with the ESD transistor ( 25 ) similar to a Darlington transistor with correspondingly greater current amplification.

On the functional use of the circuit for additional dynamic activation of the ESD current ( 17 ) can be omitted if the dynamics of the ESD transistor ( 16 ) is sufficient to activate the desired ESD current in the ESD case.

In detail, the shows 9 the classification of the circuit for static activation of the ESD current ( 15 ) into a Iptate ring current generator ( 38 ), a threshold generator ( 39 ) and an activation transistor ( 23 ), which generates an activation signal ( 24 ) generated. This is generally done with the gate or base terminal of the ESD transistor ( 26 ), alternatively to the gate or base terminal of the acceleration transistor ( 32 ). Both the Iptate Ring Current Generator ( 38 ), as well as the threshold generator ( 39 ) are directly between the first connection ( 1 ) and the Second Connection ( 2 ) and thereby receive their power supply.

An embodiment of the circuit for the static activation of the ESD current ( 15 ) is in the 10 shown. The Iptate Ring Current Generator ( 38 ) is here by the components ( 40 ) 41 ) 42 ) 43 ) and ( 44 ), the threshold generator ( 39 ) by the components ( 21 ) 22 ) 45 ) 46 ) and ( 47 ). The first current source transistor ( 40 ) forms a current source whose current value is the lower current mirror reference ( 42 ) receives. With the self-adjusting reference voltage, the current mirror transistor ( 43 ). The one by the reference resistor ( 44 ) limited current through the current mirror transistor ( 43 ) is applied to the current source reference transistor ( 41 ), which in turn is used as reference for the current source transistor ( 40 ) serves. This circuit with the feedback control on this path to a reference current is known in the literature as a ring current source.

The start-up capacitor ( 50 ) is only optional and helps with suitable dimensioning in the ESD case to a faster settling of the current reference of the Iptat ring current generator ( 38 ). Additionally or alternatively, for the same purpose, an alternative starting capacitor ( 51 ) parallel to current mirror transistor ( 43 ) and reference resistance ( 44 ) to be ordered.

In the threshold generator ( 39 ), a switching threshold transistor ( 47 ) is operated as an emitter circuit, wherein the transistor ( 45 ) acts as a current source at the collector. The base voltage is controlled by a voltage divider ( 20 ) formed from a positive branch ( 21 ) and a negative branch ( 22 ) consists. The parallel to the negative branch of the voltage divider ( 22 ) switching transistor ( 46 ) forms a current source, the temperature dependence of the switching threshold transistor ( 47 ) compensated. By suitable choice of the transmission ratios of the power source ( 40 ) relative to the upper current source reference ( 41 ) and the translation ratio of the power sources ( 43 ) and ( 46 ) compared to the lower current mirror reference ( 42 ), the temperature influence on both the activation transistor ( 23 ) as well as to that of the ESD transistor ( 25 ) and optionally on the amplifier transistor connected as an amplifier ( 30 ).

The activation transistor ( 23 ) begins to conduct when the voltage difference between the first terminal ( 1 ) and the Second Connection ( 2 ) becomes so large that over the voltage divider ( 20 ) a sufficiently high base-emitter voltage for switching the switching threshold transistor ( 47 ) is produced.

Not shown separately is the possibility for reasons of accuracy to assemble the components used in each case from several individual components.

Not shown separately is the possibility of further Components further increased the accuracy, causing Parameter dependencies of the components already described be further reduced or compensated.

Not shown separately is the possibility that in the embodiments used transistors of the P-MOS type by transistors of the PNP type to replace.

Not shown separately is the possibility that in the embodiments used NPN-type transistors by transistors of the N-MOS type to replace.

1

first Connection; Positive supply voltage to be protected Circuit.

2

second Connection; Negative supply voltage of the protected Circuit.

3

third Connection; Other connections (egg or output signals) the circuit to be protected.

4

fourth Connection; Positive supply voltage of the second to be protected Circuit.

5

fifth Connection; Negative supply voltage of the second to be protected Circuit.

6

ESD protection circuit in serial arrangement.

7

To protective circuit.

7a

Second circuit to be protected.

8th

ESD protection circuit in parallel arrangement.

9

positive Coupling diode from the third connection to the ESD protection circuit.

10

negative Coupling diode from the third connection to the ESD protection circuit.

11

positive Coupling diode from the first connection to the ESD protection circuit.

12

negative Coupling diode from the second connection to the ESD protection circuit.

13

positive Coupling diode from the fourth connection to the ESD protection circuit.

14

negative Coupling diode from the fifth connection to the ESD protection circuit.

15

circuit for the static activation of the ESD current.

16

circuit of the ESD transistor.

17

circuit for additional dynamic activation of the ESD current.

18

operational amplifiers or comparator.

19

Reference voltage source.

20

Voltage divider.

21

positive Branch of the voltage divider.

22

negative Branch of the voltage divider.

23

Activation transistor.

24

Activation line or activation signal.

25

ESD transistor.

26

gate or base terminal of the ESD transistor.

27

Gate bleeder resistor of the ESD transistor.

28

additional Gate-drain capacity ("Miller" capacity) of the ESD transistor.

29

additional Gate-source capacitance of the ESD transistor.

30

Acceleration transistor.

31

Dynamic line or dynamic signal.

32

gate or base terminal of the acceleration transistor.

33

additional Gate-drain capacity ("Miller" capacity) of the acceleration transistor.

34

additional Gate-source capacitance of the acceleration transistor.

35

additional Gate-ground capacitance of the acceleration transistor.

36

Gate-source bleeder resistor of the acceleration transistor.

37

Gate-ground bleeder resistor of the acceleration transistor.

38

Iptat-ring current generator (positive temperature proportional current).

39

Threshold generator.

40

first Current source transistor.

41

Upper Current source reference.

42

Lower Current mirror reference.

43

Current mirror transistor.

44

Reference resistor.

45

second Current source transistor.

46

Temperature compensating transistor.

47

Switching threshold transistor.

48

Center tap of the voltage divider ( 20 ).

49

output of the Iptate ring current generator.

50

Start capacitor.

51

alternative Start capacitor.

β

Current amplification factor of the switching threshold transistor ( 47 ).

eo

Electron charge 1.602 · 10 ^-19 As.

IC42

Collector current of the transistor of the lower current mirror reference ( 42 ).

IC43

Collector current of the current mirror transistor ( 43 ).

Ic46

Collector current of the transistor ( 46 ).

Ie42

Emitter current of the transistor ( 42 ).

Ir21

Current through the resistor ( 21 ).

Ir22

Current through the resistor ( 22 ).

Is42

Saturation current of the transistor of the lower current mirror reference ( 42 ).

Is43

Saturation current of the current mirror transistor ( 43 ).

H

Size ratio of the transistor ( 40 ) to the transistor ( 41 ).

j

Size ratio of the transistor ( 45 ) to the transistor ( 41 ).

k

Boltzmann constant 1.3803 · 10 ^-23 VAs / K.

m

Size ratio of the transistor ( 43 ) to the transistor ( 42 ).

n

Size ratio of the transistor ( 46 ) to the transistor ( 42 ).

R21

Resistance value of the positive branch ( 21 ) of the voltage divider ( 20 ).

R22

Resistance value of the negative branch ( 22 ) of the voltage divider ( 20 ).

R44

Resistance value of the reference resistor ( 44 ).

T

Junction temperature of the transistor in Kelvin.

Ube42

Base-emitter voltage difference of the transistor ( 42 ).

Ube43

Base-emitter voltage difference of the transistor ( 43 ).

Ube47

Base-emitter voltage difference of the switching threshold transistor ( 47 ).

Ur22

Voltage drop across the resistor ( 22 ).

Ur44

Voltage drop across the reference resistor ( 44 ).

U49

Voltage value at the output ( 49 ) of the Iptate ring current generator with respect to ( 2 ).

Ut

thermal stress Ut = k · T / eo.

Vdd

Supply voltage or voltage difference between ( 1 ) and ( 2 ).

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• - US 5465188 [0003, 0003]
• DE 102008001368 A1 [0004]
• US 53465188 [0024]

Claims (11)

ESD protection circuit ( 8th ) with a first connection ( 1 ) and a second connection ( 2 ), one between the first connection ( 1 ) and the Second Connection ( 2 ) lying working-current path of an ESD transistor ( 25 ), wherein the ESD transistor ( 25 ) in dependence on a potential at a center tap of a voltage divider ( 20 ), which is located between the first port ( 1 ) and the Second Connection ( 2 ), characterized in that the ESD transistor ( 25 ) via an activation transistor ( 23 ), which is controlled by a switching threshold transistor ( 47 ) driven by the potential of the center tap ( 48 ) of the voltage divider ( 20 ) and that at the center tap ( 48 ) of the voltage divider ( 20 ) a temperature compensation circuit ( 38 . 46 ) is attached. ESD protection circuit ( 8th ) according to claim 1, characterized in that the ESD transistor via an acceleration transistor ( 30 ) activated by an activation transistor ( 23 ), which is controlled by a switching threshold transistor ( 47 ) driven by the potential ( 48 ) of the center tap of the voltage divider ( 20 ) and that at the center tap ( 48 ) of the voltage divider ( 20 ) a temperature compensation circuit ( 38 . 46 ) is attached. ESD protection circuit ( 8th ) according to one of the preceding claims, characterized by a supplement of the ESD transistor ( 25 ) with further acceleration transistors ( 30 ) to increase the dynamics. ESD protection circuit ( 8th ) according to claim 3, characterized by a supplementation of the further acceleration transistors ( 30 ) with a capacity ( 33 ) between the first connection ( 1 ) and the gate or base terminal of the acceleration transistor ( 32 ) to increase the dynamics. ESD protection circuit ( 8th ) according to claims 3 and 4, characterized by a supplement of the further acceleration transistors ( 30 ) with a capacity ( 34 ) between the gate or base terminal of the acceleration transistor ( 32 ) and the dynamics line ( 31 ) to reduce the dynamics. ESD protection circuit ( 8th ) according to claims 3, 4 and 5, characterized by a supplement of the further acceleration transistors ( 30 ) with a capacity ( 34 ) between the gate or base terminal of the acceleration transistor ( 32 ) and the Second Connection ( 2 ) to reduce the dynamics. ESD protection circuit ( 8th ) according to one of the preceding claims, characterized by a supplement of the ESD transistor ( 25 ) with a capacity ( 29 ) between the gate or base terminal of the ESD transistor ( 26 ) and the Second Connection ( 2 ) to reduce the dynamics. ESD protection circuit ( 8th ) according to one of the preceding claims, characterized by a supplement of the ESD transistor ( 25 ) with a capacity ( 28 ) between the first connection ( 1 ) and the gate or base terminal of the ESD transistor ( 26 ) to increase the dynamics. ESD protection circuit ( 8th ) according to one of the preceding claims, characterized in that the voltage divider ( 20 ) two resistors ( 21 . 22 ), which are realized as ohmic resistors. ESD protection circuit ( 8th ) according to one of the preceding claims, characterized in that the temperature compensation circuit ( 38 . 46 ) by an itptate ring current source ( 38 ) is realized. ESD protection circuit ( 8th ) according to one of the preceding claims, characterized in that the voltage divider ( 20 ) contains at least one intervention, with which the resistance value of at least one of the partial resistances ( 21 . 22 ) can be changed.