JP2009267011A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a method of manufacturing a semiconductor device, capable of forming a silicide layer with proper resistance value by devising a method of dislodging a silicide block layer. <P>SOLUTION: When a silicide block layer 10 is removed by a reactive-ion etching, it is set up to enhance the voltage amplitude value Vpp of a high-frequency bias electric power for ion drawing-in after detecting an end point of the reactive-ion etching rather than before detecting the end point of the reactive-ion etching. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device using a salicide process.

  Currently, a silicide layer is formed on the surface of a source region, a drain region, and a gate electrode of a semiconductor device from the viewpoint of reducing the wiring resistance of the semiconductor device and improving the contact yield. Such a process of forming a silicide layer in a self-aligned manner only in the source region, the drain region, and the gate electrode region is called a salicide process.

  As the metal material for forming the silicide, Ti, Co, Ni, or the like can be considered. Among these, since the temperature of the silicide formation process is relatively low, and the thin line effect in which the resistance increases as the electrode line width becomes narrower, it is difficult to cause a thin line effect. It is increasingly used as a metal material for forming silicide.

  On the other hand, in a region other than the silicide region in which the silicide layer is formed in the same semiconductor device, there may be a non-silicide region in which no silicide layer is formed in order to obtain a high resistance layer used as a resistance element or the like in the electric circuit. .

  In manufacturing a semiconductor device having a silicide region and a non-silicide region, after forming a source region, a drain region, and a gate electrode for each of the silicide region and the non-silicide region on the semiconductor substrate, A silicide block layer is formed on the entire surface, and the silicide block layer in the silicide region is removed by etching. Thereafter, a salicide process is performed to obtain a semiconductor device having a silicide region and a non-silicide region (Patent Document 1).

  Further, the silicide block layer is often etched using a reactive ion etching apparatus because of the high anisotropy during etching and the high etching rate.

Japanese Patent Laid-Open No. 11-68103

The composition of the silicide layer using Ni includes NiSi or NiSi ₂ . NiSi has advantages such as lower resistance than NiSi ₂ , a thin silicide layer, and good interface morphology.

However, in the conventional method, NiSi ₂ is formed in the source region and the drain region, causing problems such as an increase in resistance of the semiconductor device and an increase in junction leakage.

The inventors of the present invention have considered that the NiSi ₂ formation is caused by the damage generated in the source region and the drain region when the silicide block layer is removed by reactive ion etching, in relation to the above problem.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the problems such as an increase in resistance and an increase in junction leakage of the semiconductor device as described above.

  In the embodiment of the present invention, when reactive ion etching is performed on the silicide block layer, Vpp, which is the voltage amplitude value of the bias high-frequency power for ion pull-in of reactive ion etching after the end point detection is lower than before the end point detection. is doing.

  In another embodiment of the present invention, when reactive ion etching is performed on the silicide block layer, the etching gas is changed to a gas containing hydrogen before the end point is detected, and is switched to a gas not containing hydrogen after the end point is detected.

According to the method for manufacturing a semiconductor device according to the embodiment of the present invention, the formation of NiSi ₂ is suppressed, and the resistance of the semiconductor device is reduced, the junction leakage is reduced, and the like.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIGS. 1A to 1H are cross-sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a reactive ion etching apparatus.

  First, referring to FIGS. 1A to 1H, a normally used formation method of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a silicide region in which a silicide layer is formed and a non-silicide region in which no silicide layer is formed. Indicates. In FIGS. 1A to 1D, since the formation method of the silicide region and the non-silicide region is the same, the formation method of these two regions is depicted without distinction. FIGS. 1E to 1F are drawn separately because the formation method is different between the silicide region and the non-silicide region. In FIG. 1, the sizes of the MISFETs in the silicide region and the non-silicide region are not distinguished, but the thickness of the gate insulating film, the length of the gate length, etc. are the same in the silicide region and the non-silicide region. However, the present invention is not limited. In the description of FIGS. 1A to 1H, a P-type MISFET is used, but the present invention can also be applied to an N-type MISFET. It should be noted that the present invention is not construed as being limited to the MISFET formation flow shown in FIGS.

  First, as shown in FIG. 1A, an element isolation insulating film 2 is formed on a semiconductor substrate 1. Then, after forming the gate insulating film 3 on the semiconductor substrate 1 and the gate electrode 4 on the gate insulating film 3, the gate electrode 4 and the gate insulating film 3 are formed as shown in FIG. To pattern. In addition, as a material used for the gate insulating film 3, a silicon oxide, a silicon oxynitride, a hafnium oxide, etc. can be considered, However It is not restricted to these. The material used for the gate electrode 4 may be polysilicon, amorphous silicon, Ti, Al, or the like, but is not limited thereto.

  Next, as shown in FIG. 1B, an impurity is implanted into the semiconductor substrate 1 using the gate electrode 4 as a mask to form an impurity diffusion region 5 such as a lightly doped drain (LDD).

  Thereafter, a silicon oxide film 6 and a silicon nitride film 7 are formed on the semiconductor substrate 1. Etching back the silicon oxide film 6 and the silicon nitride film 7 forms a sidewall 8 as shown in FIG.

Next, as shown in FIG. 1D, impurities are implanted using the sidewall 8 and the gate electrode 4 as a mask to form an impurity diffusion region 9 which becomes a source region and a drain region. As conditions at this time, for example, the impurity to be implanted is B, the implantation energy is 0.5 to 5 keV, and the implantation amount is 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² .

  Next, the silicide block layer 10 is formed on the silicide region 13 on the semiconductor substrate 1 and the non-silicide region 12 on the semiconductor substrate 1, and the silicide block layer 10 is covered with the photoresist 11. Thereafter, as shown in FIG. 1E, the photoresist 11 on the silicide region 13 is opened by patterning. Here, the material of the silicide block layer 10 is an insulating film such as a silicon oxide film or a silicon nitride film.

  Next, as shown in FIG. 1F, the silicide block layer 10 in the silicide region 13 is etched by reactive ion etching.

  Here, an example of reactive ion etching will be described with reference to FIG. In FIG. 2, 16 is an etching gas introduction port, 17 is an etching gas exhaust port, 18 is a counter electrode, 19 is a reaction tube, 20 is a substrate, 21 is a planar electrode, 22 is a high frequency power source for plasma excitation, and 23 is a substrate bias. , A blocking capacitor 24, and a matching unit 25.

In FIG. 2, when etching the substrate, first, an etching gas is introduced into the reaction tube 19 from the etching gas inlet 16. For example, CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F _8, or a mixed gas thereof is used as the etching gas. Since the pressure of the etching gas needs to be kept low, the etching gas is exhausted from the etching gas exhaust port 17 so as to maintain this pressure.

  After introducing the etching gas, when the high frequency power is applied from the high frequency power source 22 for plasma excitation to the planar electrode 21, bias high frequency power is applied from the high frequency power source 23 for substrate bias. As a result, the plasma is excited, ions in the plasma are accelerated by the bias high frequency power, and the ions are drawn onto the substrate 20 to etch the substrate 20.

  Reactive ion etching is performed as described above as an example, but there are various other methods for generating plasma, such as using a magnetic field. Although not shown in the figure, as an etching end point detection method, a method for detecting the end point of etching by analyzing light emission from plasma, or a method for detecting the end point of etching by analyzing the mass of the etched material. There are methods.

  After the silicide block layer 10 is etched as shown in FIG. 1F by the reactive ion etching shown as an example above, the photoresist 11 is removed, and the metal film 14 is formed on the silicide region 13 and the non-silicide region 12. Sputter. The material used for the metal film 14 is, for example, an alloy of Ni arbitrarily selected from Pt, V, Co, Hf, Ta, Er, Y, Yb, or Ti, or Ni alone.

  Next, heat treatment is performed at a temperature of 250 ° C. to 500 ° C. for 30 seconds to 90 seconds in an inert gas atmosphere such as nitrogen, and the gate electrode 4 in the silicide region and the underlying semiconductor substrate 1 and the metal film in the impurity diffusion region 9 14 is reacted to form a silicide layer 15 as shown in FIG.

  Thereafter, the unreacted metal film 14 is removed by wet etching. A heat treatment at 400 ° C. to 600 ° C. may be applied after removal by wet etching.

  In this embodiment, with respect to the formation of the MISFET performed in FIGS. 1A to 1H, in the reactive ion etching of the silicide block layer 10 performed in the process of FIG. After detecting the end point of reactive ion etching, Vpp, which is the voltage amplitude value of high-frequency power, is set lower than before detecting the end point of reactive ion etching. At this time, it is preferable that the Vpp before the end point detection is about 900V, and the Vpp after the end point detection is 300V or less.

  Here, not only the silicide block layer but the layer to be etched usually does not have a uniform thickness over the entire surface. Therefore, if etching is terminated immediately after the end point of etching is detected, etching is performed. This residue may remain anywhere in the surface and adversely affect the finally manufactured semiconductor device. For this reason, normally, when performing etching, in order to prevent the influence of the residue, the etching is performed for a certain period of time after the end point of etching is detected.

  In addition, in order to detect the end point of reactive ion etching, a method of detecting the end point of etching by analyzing the emission intensity of plasma, or a method of detecting the end point of etching by analyzing the mass of the etched material. Etc. In either case, the end point detection principle is to detect a change in signal due to a change in the etching target.

  In the step of FIG. 1 (f), when the reactive ion etching of the silicide block layer 10 is completed, the impurity diffusion region 9 is etched. Therefore, the change of the object of the reactive ion etching at this time is used as a method for detecting the end point. use.

  Further, as the metal film 14 used in FIG. 1 (g), Ni alone or a material arbitrarily selected from Pt, V, Co, Hf, Ta, Er, Y, Yb or Ti and an alloy of Ni is used. Use. The film thickness of the metal film 14 is preferably 9 nm or more.

According to the present embodiment, when reactive ion etching of the silicide block layer 10 is performed, Vpp is higher before end point detection than after end point detection, thereby increasing the etching rate and improving throughput. By setting the Vpp lower than that before the end point detection after the end point is detected, damage entering the impurity diffusion region is suppressed, the formation of NiSi ₂ is inhibited, the resistance is reduced, the junction leak is reduced, and the like.

  Furthermore, this embodiment provides a method for reducing damage to the source region and the drain region in the lower layer when the silicide block layer 10 is removed by reactive ion etching. If the film formed above is removed by reactive ion etching to damage the source region and drain region in the lower layer of the film, the method of this embodiment is used. Damage can be reduced.

  Specifically, for example, the silicon oxide film 6 and the silicon nitride film 7 are etched back.

(Embodiment 2)
With reference to FIG.1 (f), the manufacturing method of the semiconductor device in Embodiment 2 of this invention is demonstrated. The MISFET formation performed in FIGS. 1A to 1E is performed by the same method as in the first embodiment. In the reactive ion etching of the silicide block layer 10 performed in the step of FIG. 1F, the reactive ion etching is divided into a first reactive ion etching and a second reactive ion etching that follows. Do. More specifically, the first reactive ion etching is performed using a gas containing hydrogen to detect the etching end point of the silicide block layer 10. The second reactive ion etching is performed with a gas not containing hydrogen after the end point of the silicide block layer 10 is detected. As in the first embodiment, the metal film 14 used in FIG. 1G is selected from Ni alone, Pt, V, Co, Hf, Ta, Er, Y, Yb, or Ti. An alloy of material and Ni is used. Furthermore, the thickness of the metal film 14 is preferably 9 nm or more. Further, it is more preferable that Vpp of the second reactive ion etching is lower than Vpp of the first reactive ion etching.

Here, the hydrogen-free gas used in the second reactive ion etching means, for example, CF ₄ , C ₂ F ₆ , C ₄ F _{8, or} a mixed gas thereof, as well as a carrier gas or the like. This means that hydrogen is not included. In addition, the gas containing hydrogen used in the first reactive ion etching means that hydrogen atoms may be included such as CHF ₃ , and hydrogen molecules may be included as a carrier gas or the like.

  In reactive ion etching, etching may be performed using a gas containing hydrogen. This is because, when a gas containing hydrogen is used, the selectivity between the oxide film and the photoresist or other film is good.

However, the inventors of the present patent application, when performing reactive ion etching with a gas containing hydrogen, hydrogen is implanted deeply into the semiconductor substrate, causing crystal defects in the vicinity of the range, and the crystal defects follow. It has been found that the formation of NiSi ₂ is promoted during the formation of a silicide layer using Ni.

  Further, as described above, when etching is performed, after the end point is detected, etching is continuously performed for a certain period of time in order to remove the residue.

For this reason, the silicide block layer 10 is etched by reactive ion etching as in this embodiment, and after the end point is detected, the etching is performed by reactive ion etching with a gas not containing hydrogen, thereby forming NiSi ₂ . Can be inhibited. Further, the formation of NiSi ₂ can be further inhibited by setting Vpp after end point detection to be lower than Vpp before end point detection as in the first embodiment.

It is a figure which shows an example of the manufacturing process of a semiconductor device. It is the figure which showed schematically an example of the apparatus which performs reactive ion etching.

Explanation of symbols

  1 semiconductor substrate, 2 element isolation insulating film, 3 gate insulating film, 4 gate electrode, 5,9 impurity diffusion region, 6 silicon oxide film, 7 silicon nitride film, 8 sidewall, 10 silicide block layer, 11 photoresist, 12 Non-silicide region, 13 silicide region, 14 metal film, 15 silicide layer, 16 etching gas inlet, 17 etching gas outlet, 18 counter electrode, 19 reaction tube, 20 substrate, 21 planar electrode, 22 high frequency power source for plasma excitation , 23 High frequency power supply for substrate bias, 24 blocking capacitor, 25 matching unit.

Claims (10)

Forming a gate electrode on the surface of the channel region disposed on the surface of the semiconductor substrate via a gate insulating film;
Forming a first impurity diffusion region and a second impurity diffusion region so as to sandwich the channel region;
Forming an insulating film so as to cover the semiconductor substrate after forming the first and second impurity diffusion regions;
Removing the insulating film until the end point is detected by first reactive ion etching in a partial region on the semiconductor substrate;
After detecting the end point of the first reactive ion etching, the second reactive ion etching is performed under the condition that the voltage amplitude value (Vpp) of the bias high frequency power for ion attraction is lower than that of the first reactive ion etching. Removing the insulating film and exposing the first impurity diffusion region and the second impurity diffusion region;
Forming a metal film for forming a silicide layer on the first impurity diffusion region and the second impurity diffusion region.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the voltage amplitude value (Vpp) of the second reactive ion etching is 300 V or less.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the first reactive ion etching is performed with a gas containing hydrogen, and the second reactive ion etching is performed with a gas not containing hydrogen. Forming a gate electrode on the surface of the channel region disposed on the surface of the semiconductor substrate via a gate insulating film;
Forming a first impurity diffusion region and a second impurity diffusion region so as to sandwich the channel region;
Forming an insulating film so as to cover the semiconductor substrate after forming the first and second impurity diffusion regions;
Removing the insulating film in a partial region on the semiconductor substrate until the end point is detected by first reactive ion etching using a gas containing hydrogen; and
After the end point of the first reactive ion etching is detected, the insulating film is removed by second reactive ion etching using a gas not containing hydrogen to expose the first impurity diffusion region and the second impurity diffusion region. Process,
Forming a metal film for forming a silicide layer on the first impurity diffusion region and the second impurity diffusion region.   5. The method for manufacturing a semiconductor device according to claim 3, wherein the gas containing hydrogen is a gas containing hydrogen molecules.   5. The method of manufacturing a semiconductor device according to claim 3, wherein the gas containing hydrogen is a gas in which molecules in the gas contain hydrogen atoms.   7. The film thickness of the metal film for forming a silicide layer on the first impurity diffusion region and the second impurity diffusion region is 9 nm or more, according to claim 1. The manufacturing method of the semiconductor device of description.   The method for manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicide block layer.   9. The method of manufacturing a semiconductor device according to claim 1, wherein a material of the metal film for forming the silicide layer is Ni.   The material of the metal film for forming the silicide layer is an alloy of Ni and a material arbitrarily selected from Pt, V, Co, Hf, Ta, Er, Y, Yb or Ti. A method for manufacturing a semiconductor device according to claim 1.

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