JP2009266905A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2009266905A
JP2009266905A JP2008111924A JP2008111924A JP2009266905A JP 2009266905 A JP2009266905 A JP 2009266905A JP 2008111924 A JP2008111924 A JP 2008111924A JP 2008111924 A JP2008111924 A JP 2008111924A JP 2009266905 A JP2009266905 A JP 2009266905A
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semiconductor chip
internal terminal
internal
semiconductor device
wire
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Masahiko Ohiro
雅彦 大広
Yoshiki Takayama
義樹 高山
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Panasonic Corp
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Panasonic Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/041—Stacked PCBs, i.e. having neither an empty space nor mounted components in between
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2018—Presence of a frame in a printed circuit or printed circuit assembly
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that achieves multi-pin formation even if being small while securing bonding strength. <P>SOLUTION: The semiconductor device is provided with a semiconductor chip 1, a package 2 (a base) that has a mounting part, mounted with the semiconductor chip 1, and a plurality of conductors 4 in which internal terminals 8 are arranged oppositely to each other on the outer periphery of the semiconductor chip 1, and each wire 5 that connects between each electrode pad 3 of the semiconductor chip 1 and each internal terminal 8 of the conductors 4. The internal terminal 8 is formed into a shape that the chip side facing the semiconductor chip 1 is expanded. By this, it is possible to surely put a second bond on the internal terminal 8 regardless of the direction of the wire 5 extended from the electrode pad 3, thereby ensuring bonding strength. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は半導体チップを基台に搭載しワイヤボンドした半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a base and wire-bonded.

従来の半導体装置を図１０および図１１に示す。半導体装置は、半導体チップ１と、半導体チップ１を搭載した凹状のパッケージ（基台）２と、半導体チップ１の電極パッド３とパッケージ２に配列された導体４とを接続したワイヤ５と、パッケージ２の上面に封着剤６により接着されパッケージ２内を保護するガラス７とを有している。パッケージ２において、導体４の内部端子８は内周の段差部に並び、外部端子９は下面に並んでいる。   A conventional semiconductor device is shown in FIGS. The semiconductor device includes a semiconductor chip 1, a concave package (base) 2 on which the semiconductor chip 1 is mounted, a wire 5 that connects an electrode pad 3 of the semiconductor chip 1 and a conductor 4 arranged in the package 2, and a package. 2 and a glass 7 that is bonded to the upper surface of the package 2 with a sealant 6 to protect the inside of the package 2. In the package 2, the internal terminals 8 of the conductors 4 are arranged on the inner circumferential stepped portion, and the external terminals 9 are arranged on the lower surface.

半導体装置を製造する際のワイヤボンド工程を図１２および図１３に示す。キャピラリ２１から出たワイヤ５の端部に放電によりボールを作り（図示せず）、半導体チップ１の電極パッド３に押し付けながら超音波振動を加えてファーストボンド接合を行い、ループ形成を行い、ループ端部を内部端子８に押し付けながら超音波振動を加えてセカンドボンド接合を行い、最後にワイヤ５を引きちぎる。この動作を対応する各組の電極パッド３と内部端子８とについて行う。多ピン化のために内部端子８を千鳥配置としたものも見られる（特許文献１）。
特開平２−２７８７４２公報 A wire bonding process in manufacturing a semiconductor device is shown in FIGS. A ball is formed by an electric discharge at the end of the wire 5 coming out of the capillary 21 (not shown), and ultrasonic bond is applied while pressing the electrode pad 3 of the semiconductor chip 1 to perform first bond bonding, to form a loop, The ultrasonic vibration is applied while pressing the end portion against the internal terminal 8 to perform the second bond bonding, and finally the wire 5 is torn off. This operation is performed for the corresponding electrode pad 3 and internal terminal 8. In some cases, the internal terminals 8 are arranged in a staggered arrangement to increase the number of pins (Patent Document 1).
JP-A-2-278742

しかし従来の内部端子８は図示したように矩形状であり、そこにワイヤ５を押し付けることで行うセカンドボンドはクレセント状となるため、内部端子８の幅とワイヤ５の方向との関係によっては問題を生じる。   However, the conventional internal terminal 8 has a rectangular shape as shown in the figure, and the second bond performed by pressing the wire 5 on the internal terminal 8 has a crescent shape. Therefore, there is a problem depending on the relationship between the width of the internal terminal 8 and the direction of the wire 5. Produce.

つまり、内部端子８の中心線とワイヤ５の延び方向とが一致するかそれに近いときはセカンドボンドが内部端子８内に収まるものの、角度を持つときはセカンドボンドが内部端子８からはみ出し、接合強度が確保できなくなる。これはパッケージ２の多ピン化のために内部端子８を細くするときに顕在化する問題である。特許文献１のパッケージでも千鳥配置とした内部端子は矩形状であり、上述の問題は存在し、多ピン化に限界がある。   That is, when the center line of the internal terminal 8 and the extending direction of the wire 5 coincide with each other or close to each other, the second bond can be accommodated in the internal terminal 8, but when it has an angle, the second bond protrudes from the internal terminal 8. Cannot be secured. This is a problem that becomes apparent when the internal terminals 8 are thinned to increase the number of pins of the package 2. Even in the package of Patent Document 1, the internal terminals arranged in a staggered manner have a rectangular shape, the above-mentioned problems exist, and there is a limit to increasing the number of pins.

多ピン化のためには、パッケージ２を複数層で構成し（図１０では３層としている）、内部端子８を層を変えて多段に配置するという手法もあるが、パッケージ２が厚くなり、平面サイズも大きくなってしまう。   In order to increase the number of pins, the package 2 is composed of a plurality of layers (three layers in FIG. 10), and there is a method of arranging the internal terminals 8 in multiple stages by changing the layers, but the package 2 becomes thicker, The plane size will also increase.

本発明は、上記問題に鑑み、接合強度を確保することができ、小型であっても多ピン化も実現できる半導体装置を提供することを目的とする。   In view of the above-described problems, an object of the present invention is to provide a semiconductor device that can ensure bonding strength and can realize a large number of pins even if it is small.

上記課題を解決するために、本発明の半導体装置は、半導体チップと、前記半導体チップを搭載した搭載部と前記半導体チップの外周に内部端子が対向した複数の導体とを有した基台と、前記半導体チップの電極パッドと前記導体の内部端子とを接続したワイヤとを具備した半導体装置において、前記内部端子は、前記半導体チップに対向した先端側が広がった形状としたことを特徴とする。これにより、電極パッドから延ばされるワイヤの方向に関わらずセカンドボンドを確実に内部端子上に収めることができ、接合強度を確保できる。   In order to solve the above-described problems, a semiconductor device of the present invention includes a semiconductor chip, a mounting portion on which the semiconductor chip is mounted, and a base having a plurality of conductors with internal terminals facing the outer periphery of the semiconductor chip; In the semiconductor device including a wire connecting the electrode pad of the semiconductor chip and the internal terminal of the conductor, the internal terminal has a shape in which a tip side facing the semiconductor chip is widened. Thereby, regardless of the direction of the wire extending from the electrode pad, the second bond can be reliably stored on the internal terminal, and the bonding strength can be ensured.

複数の導体の内部端子は半導体チップの外周に沿って千鳥配置されていることを特徴とする。これにより内部端子の高密度配置、多ピン化が可能となる。
千鳥配置された内部端子の内、半導体チップにより近い内部端子（内側の内部端子）に比べてより遠い内部端子（外側の内部端子）が厚く形成されていることを特徴とする。外側の内部端子に接続するワイヤの位置が高くなるため、高密度配置であっても、内側の内部端子とのショートを確実に防止できる。 The internal terminals of the plurality of conductors are staggered along the outer periphery of the semiconductor chip. As a result, the internal terminals can be arranged at a high density and the number of pins can be increased.
Among the internal terminals arranged in a staggered manner, the internal terminals (outside internal terminals) farther from the internal terminals closer to the semiconductor chip (inside internal terminals) are formed thicker. Since the position of the wire connected to the outer internal terminal is increased, short-circuiting with the inner internal terminal can be reliably prevented even in a high-density arrangement.

本発明の半導体装置は、内部端子を先端側が広がった形状、いわゆる扇形状としたことで、電極パッドから延ばされるワイヤの方向に関わらずセカンドボンドを確実に内部端子上に収めることができ、接合強度を確保できる。この内部端子の扇形状は、セカンドボンドに必要な無駄のない的確な形状であり、材料も少なくて済み、セカンドボンドのねらい位置を内部端子自身が明示できボンド位置の標準化ができる。   The semiconductor device of the present invention has a shape in which the tip of the internal terminal is widened, that is, a so-called fan shape, so that the second bond can be reliably accommodated on the internal terminal regardless of the direction of the wire extending from the electrode pad. Strength can be secured. The fan shape of the internal terminal is an accurate shape necessary for the second bond, and requires less material. The internal terminal itself can clearly indicate the intended position of the second bond, and the bond position can be standardized.

内部端子を千鳥配置とすることにより、各内部端子を必要サイズに保ちながら極限まで高密度配置することが可能になる。つまり、一般的な千鳥配置は、縦または横のいずれかの方向のみに内部端子の一部がオーバーラップしたものであるが、本発明での千鳥配置は、内部端子が扇形状であるため、縦横の両方についてオーバーラップしたものとすることができる。内部端子を１列に配置するのに比べて奥行きを必要とするものの、それでも矩形の内部端子を１段または多段に配置するのに比べて必要面積は小さい。よって、基台（および半導体装置）を小型のまま多ピン化を図ることができる。   By arranging the internal terminals in a staggered arrangement, it is possible to arrange the internal terminals at a high density to the limit while maintaining the required size. In other words, the general staggered arrangement is a part of the internal terminal that overlaps only in either the vertical or horizontal direction, but the staggered arrangement in the present invention is a fan-shaped internal terminal, It can be overlapped both vertically and horizontally. Although the depth is required as compared with the arrangement of the internal terminals in one row, the required area is still smaller than the arrangement of the rectangular internal terminals in one or more stages. Therefore, the number of pins can be increased while the base (and the semiconductor device) is small.

さらに、千鳥配置する内側の内部端子に比べて外側の内部端子を厚く形成すると、その分、外側の内部端子に接続したワイヤの位置も高くなり、高密度配置としていても、内側の内部端子との間に隙間を確保してショートの発生を確実に防止できる。   Furthermore, if the outer internal terminal is formed thicker than the inner internal terminals arranged in a staggered manner, the position of the wire connected to the outer internal terminal is increased accordingly, and even if it is arranged at a high density, A gap can be secured between the two so as to reliably prevent the occurrence of a short circuit.

以下、本発明の実施の形態を図面に基づいて説明する。
図１は本発明の一実施形態の半導体装置の一部を示す断面図、図２は同半導体装置に使用するパッケージの斜視図、図３は同パッケージの分解斜視図である。半導体装置の全体構成は先の図１０とほぼ同様なので図１０を援用する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 is a cross-sectional view showing a part of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a perspective view of a package used in the semiconductor device, and FIG. 3 is an exploded perspective view of the package. Since the entire configuration of the semiconductor device is almost the same as that of FIG. 10, FIG.

半導体装置は、半導体チップ１と、半導体チップ１を搭載した凹状のパッケージ（基台）２と、半導体チップ１の電極パッド３とパッケージ２に配列された導体４とを接続したワイヤ５と、パッケージ２の上面に封着剤６により接着されパッケージ２内を保護するガラス７とを有している。パッケージ２において、複数の導体４の内部端子８は内周の段差部に並び、外部端子９は下面に並んでいる。１０は半導体チップ１をパッケージ２内に接着したＡｇペーストである。   The semiconductor device includes a semiconductor chip 1, a concave package (base) 2 on which the semiconductor chip 1 is mounted, a wire 5 that connects an electrode pad 3 of the semiconductor chip 1 and a conductor 4 arranged in the package 2, and a package. 2 and a glass 7 that is bonded to the upper surface of the package 2 with a sealant 6 to protect the inside of the package 2. In the package 2, the internal terminals 8 of the plurality of conductors 4 are arranged in a step portion on the inner periphery, and the external terminals 9 are arranged on the lower surface. Reference numeral 10 denotes an Ag paste in which the semiconductor chip 1 is bonded in the package 2.

詳述する。パッケージ２は、第１のセラミック層１１と第２のセラミック層１２と第３のセラミック層１３とを積層して形成されている。第１のセラミック層１１は平板状であり、第２のセラミック層１２および第３のセラミック層１３は中央部が四角形に開口され枠状となっていて、第３のセラミック層１３の開口がより大きいため対向する１対の内周面に上述の段差部がある。   Detailed description. The package 2 is formed by laminating a first ceramic layer 11, a second ceramic layer 12, and a third ceramic layer 13. The first ceramic layer 11 has a flat plate shape, and the second ceramic layer 12 and the third ceramic layer 13 have a frame shape with a central portion opened in a square shape, and the opening of the third ceramic layer 13 is more Since it is large, the above-described stepped portions are present on a pair of opposed inner peripheral surfaces.

第１のセラミック層１１の中央部は半導体チップ１のための搭載部となっている。第１のセラミック層１１と第２のセラミック層１２とにわたって上述の導体４が設けられている。第１のセラミック層１１には、外部端子９とされた下面配線とキャスタレーション１４（側面）と上面配線１５とがある。第２のセラミック層１２には、内部端子８を各々有する上面配線１６と、この上面配線１６と上述の上面配線１５とを接続するビア１７とがある。   The central portion of the first ceramic layer 11 is a mounting portion for the semiconductor chip 1. The above-described conductor 4 is provided across the first ceramic layer 11 and the second ceramic layer 12. The first ceramic layer 11 includes a lower surface wiring, a castellation 14 (side surface), and an upper surface wiring 15 which are external terminals 9. The second ceramic layer 12 includes an upper surface wiring 16 having internal terminals 8 and vias 17 connecting the upper surface wiring 16 and the above-described upper surface wiring 15.

上面配線１６は、段差部の上面においては、その内周側の端辺と交わる方向に延びるように、かつ、互いに一定の間隔を有するように平行に配列されていて、その内周側の端部である内部端子８が半導体チップ１の外周に対向するようになっている。各内部端子８の形状は、半導体チップ１に対向する先端側が広がった形状、いわゆる扇形状である。   On the upper surface of the stepped portion, the upper surface wiring 16 is arranged in parallel so as to extend in a direction intersecting with the inner peripheral side edge and to have a predetermined distance from each other. The internal terminal 8 which is a part faces the outer periphery of the semiconductor chip 1. The shape of each internal terminal 8 is a so-called fan shape in which the tip side facing the semiconductor chip 1 is widened.

上記の半導体装置の製造方法について説明する。
パッケージは次のように作製する。セラミック層の材料となるグリーンシート（以下、単にセラミック層という）を用意する。 A method for manufacturing the semiconductor device will be described.
The package is manufactured as follows. A green sheet (hereinafter simply referred to as a ceramic layer) as a material for the ceramic layer is prepared.

第１のセラミック層１１には、キャスタレーション１４となる部分を打ち抜き、たとえばタングステンからなる金属ペースト（以下同様）を塗布する。また外部端子９および上面配線１５に対応する部分に金属ペーストをスクリーン印刷法により塗布する。   For the first ceramic layer 11, a portion that becomes the castellation 14 is punched, and a metal paste made of, for example, tungsten (hereinafter the same) is applied. Further, a metal paste is applied to the portions corresponding to the external terminals 9 and the upper surface wiring 15 by a screen printing method.

第２のセラミック層１２にはビア１７となる部分と中央部を打ち抜き、ビア１７となる部分に金属ペーストを充填する。また内部端子８、上面配線１６に対応する部分に金属ペーストをスクリーン印刷法により塗布する。第３のセラミック層１３は中央部を打ち抜く。   The second ceramic layer 12 is stamped with a portion that becomes the via 17 and a central portion, and a portion that becomes the via 17 is filled with a metal paste. Further, a metal paste is applied to the portions corresponding to the internal terminals 8 and the upper surface wiring 16 by a screen printing method. The third ceramic layer 13 is punched at the center.

第１のセラミック層１１と第２のセラミック層１２と第３のセラミック層１３とを、平坦化を図る必要のある箇所については金属ペーストの表面を押圧した後、積層し、圧着し、焼成する。表面に露出する外部端子９、キャスタレーション１４、内部端子８を含む上面配線１６に、たとえばニッケル、その上に金といっためっきを施す。   The first ceramic layer 11, the second ceramic layer 12, and the third ceramic layer 13 are laminated, pressure-bonded, and fired after pressing the surface of the metal paste for a portion that needs to be flattened. . The upper surface wiring 16 including the external terminals 9, the castellations 14, and the internal terminals 8 exposed on the surface is plated with nickel, for example, gold.

このように作製されたパッケージ２の搭載部にＡｇペースト１０を塗布し、ウェーハから個片化した半導体チップ１をピックアップして搭載し、半導体チップ１の電極パッド３とパッケージ２の内部端子８とをワイヤ５で接続するワイヤボンドを行う。ワイヤボンド後に、パッケージ２の上面に封着剤６を塗布し、そこにガラス７を搭載し、ＵＶ照射により封着剤６を硬化させる。   An Ag paste 10 is applied to the mounting portion of the package 2 manufactured in this way, and the semiconductor chip 1 separated from the wafer is picked up and mounted. The electrode pads 3 of the semiconductor chip 1 and the internal terminals 8 of the package 2 Are connected by a wire 5. After the wire bonding, the sealing agent 6 is applied to the upper surface of the package 2, and the glass 7 is mounted thereon, and the sealing agent 6 is cured by UV irradiation.

ワイヤボンドの際には、図４、図５に示すように、キャピラリ２１から出たワイヤ５の一端を放電により溶融させ、半導体チップ１の電極パッド３に押し付けながら超音波振動を加えてファーストボンド接合を行い、ループ形成し、内部端子８に押し付けながら超音波振動を加えてセカンドボンド接合を行い、ワイヤ５を引きちぎる、という動作を繰り返す。   At the time of wire bonding, as shown in FIGS. 4 and 5, one end of the wire 5 coming out from the capillary 21 is melted by electric discharge, and ultrasonic vibration is applied to the electrode pad 3 of the semiconductor chip 1 while applying ultrasonic vibration. Bonding, forming a loop, applying ultrasonic vibration while pressing against the internal terminal 8, performing second bond bonding, and tearing the wire 5 are repeated.

このときに、内部端子８が上述のように先端側が広がった扇形状であるため、ワイヤ５の延び方向が内部端子８の中心線の方向と異なっていても、セカンドボンドが内部端子８からはみ出すことはなく、接合強度が確保できる。   At this time, since the internal terminal 8 has a fan shape in which the tip side is widened as described above, even if the extending direction of the wire 5 is different from the direction of the center line of the internal terminal 8, the second bond protrudes from the internal terminal 8. There is no such thing, and the joining strength can be secured.

内部端子８の扇形状の中心角は、当該パッケージ２でどこまでワイヤ角度を許容するかという設計値から決めればよい。図６は内部端子８部分を拡大図示している。この内部端子８は上面配線１６の直線状部分から曲線状に広がる肩部を持った扇形状である。ワイヤ５の延び方向を、内部端子８の中心線と一致する場合を実線で示し、その両側、最大の角度を持つときの限界位置Ａ，Ｂを２点鎖線で示している。この扇形状は、ワイヤ角度の許容範囲をＡ〜Ｂの範囲とするときに、セカンドボンドを内部端子８に収めるのに十分な形状である。   The fan-shaped central angle of the internal terminal 8 may be determined from the design value of how far the wire angle is allowed in the package 2. FIG. 6 is an enlarged view of the internal terminal 8 portion. The internal terminal 8 has a fan shape having a shoulder extending from the straight portion of the upper surface wiring 16 in a curved shape. A case where the extending direction of the wire 5 coincides with the center line of the internal terminal 8 is indicated by a solid line, and the limit positions A and B having the maximum angle on both sides thereof are indicated by two-dot chain lines. This fan shape is a shape sufficient to accommodate the second bond in the internal terminal 8 when the allowable range of the wire angle is in the range of A to B.

内部端子８の扇形状は、先に図示した形状に限らず、ワイヤ５の方向が許容範囲で変化してもセカンドボンドが必ず内部端子８に収まるという前提下で種々に変形可能である。図７（ａ）に示す内部端子８は、上面配線１６の直線状部分からから垂直に広がる肩部を持った扇形状であり、先端の両角は落とされている。図７（ｂ）に示す内部端子８は、上面配線１６の直線状部分が図７（ａ）に示すものより幅広く、その直線状部分から漸次に（肩部を持たず）広がっている。先端の両角は落とされており、先端は円弧状ではなく直線状である。図７（ｃ）に示す内部端子８は、ワイヤ５を２本接続可能とするよう幅方向に広げたものである。   The fan shape of the internal terminal 8 is not limited to the shape illustrated above, and can be variously modified on the premise that the second bond always fits in the internal terminal 8 even if the direction of the wire 5 changes within an allowable range. The internal terminal 8 shown in FIG. 7A has a fan shape with a shoulder portion extending vertically from the straight portion of the upper surface wiring 16, and both corners of the tip are dropped. In the internal terminal 8 shown in FIG. 7B, the linear portion of the upper surface wiring 16 is wider than that shown in FIG. 7A, and gradually extends (without a shoulder) from the linear portion. Both corners of the tip are dropped, and the tip is not an arc but a straight line. The internal terminals 8 shown in FIG. 7C are expanded in the width direction so that two wires 5 can be connected.

これらの内部端子８の扇形状は、セカンドボンドに必要な無駄のない的確な形状であり、材料も少なくて済み、セカンドボンドのねらい位置を内部端子８自身が明示でき、ボンド位置の標準化ができる。   The fan shape of these internal terminals 8 is an accurate shape necessary for the second bond, requires less material, the internal terminal 8 itself can clearly indicate the second bond aim position, and the bond position can be standardized. .

図８に示すように、内部端子８（８ａ，８ｂ）を半導体チップ１の外周に沿って千鳥配置すれば、各内部端子８を必要サイズに保ちながら極限まで高密度配置することが可能になる。内部端子８が扇形状であるため、隣り合う内部端子８どうし、縦横（図中の上下左右）の両方についてオーバーラップしたものとすることができるのである。内部端子８を１列に配置する（たとえば図５）のに比べて、奥行きを必要とするものの、それでも矩形の内部端子を１段または多段に配置する従来型に比べて必要面積は小さい。よって、パッケージ２（および半導体装置）を小型のまま多ピン化を実現できる。   As shown in FIG. 8, if the internal terminals 8 (8a, 8b) are arranged in a staggered manner along the outer periphery of the semiconductor chip 1, it is possible to arrange the internal terminals 8 at a high density to the limit while maintaining the required size. . Since the internal terminals 8 are fan-shaped, the adjacent internal terminals 8 can be overlapped in both the vertical and horizontal directions (up, down, left and right in the figure). Although the depth is required as compared with the case where the internal terminals 8 are arranged in one row (for example, FIG. 5), the required area is still smaller than the conventional type in which the rectangular internal terminals are arranged in one or more stages. Therefore, the number of pins can be increased while the package 2 (and the semiconductor device) is small.

図９（ａ）（ｂ）に示すように、千鳥配置する内部端子８の内、半導体チップ１により近い内側の内部端子８ａに比べてより遠い外側の内部端子８ｂを厚く形成すれば、内部端子８ｂに接続するワイヤ５の位置が高くなるため、高密度配置であっても、ワイヤ５と内部端子８ａの上面との隙間Ｃを確保してショートを確実に防止できる。   As shown in FIGS. 9A and 9B, if the inner terminal 8b farther away from the inner terminal 8a closer to the semiconductor chip 1 among the inner terminals 8 arranged in a staggered manner is formed thicker, Since the position of the wire 5 connected to 8b becomes high, even if it is a high density arrangement | positioning, the clearance gap C between the wire 5 and the upper surface of the internal terminal 8a can be ensured, and a short circuit can be prevented reliably.

このように厚みの異なる内部端子８ａ，内部端子８ｂを形成するには、第２のセラミック層１２の上面の内部端子８、上面配線１６に対応する箇所に金属ペーストをスクリーン印刷法により塗布し、必要箇所を押圧する。次に内部端子８ｂの部分について、別のスクリーンマスクを用いて２回目の金属ペースト塗布を行う。このときには、第２のセラミック層１２の上面は既に１回目の金属ペースト塗布が行なわれているため平坦ではないが、スクリーンマスクの形状と下降位置とを適切に設定することで、部分的な２回目の塗布も問題なく行うことができる。２回目の金属ペースト塗布後、平坦化のために内部端子８ｂの部分を押圧する。   In order to form the internal terminal 8a and the internal terminal 8b having different thicknesses as described above, a metal paste is applied by screen printing to a location corresponding to the internal terminal 8 and the upper surface wiring 16 on the upper surface of the second ceramic layer 12, Press the necessary part. Next, a second metal paste is applied to the internal terminal 8b using another screen mask. At this time, the upper surface of the second ceramic layer 12 is not flat because the first metal paste has already been applied. However, by appropriately setting the shape of the screen mask and the lowered position, a partial 2 The second application can be performed without any problem. After the second metal paste application, the internal terminal 8b is pressed for planarization.

なお内部端子８ｂの厚みの確保は、上記した金属ペーストの部分的な塗布に限られず、たとえばめっき厚を部分的に変更することによってもよい。千鳥配置された外側の内部端子８ｂが、内側の内部端子８ｂよりも高くなればよいのである。   The securing of the thickness of the internal terminal 8b is not limited to the above-described partial application of the metal paste, and for example, the plating thickness may be partially changed. The outer internal terminals 8b arranged in a staggered manner need only be higher than the inner internal terminals 8b.

さらには、内部端子８（８ａ，８ｂ）が上述のように先端側が広がった形状であればよいのであって、パッケージ２自体も上述のセラミックを材料とした凹状のものに限られず、例えば有機基板であっても構わない。   Further, the internal terminal 8 (8a, 8b) may be any shape as long as the tip side is expanded as described above, and the package 2 itself is not limited to the concave shape made of the above-mentioned ceramic, for example, an organic substrate. It does not matter.

本発明の半導体装置は、小型、多ピンを実現できるもので、種々の電子機器に有用である。   The semiconductor device of the present invention can realize a small size and a large number of pins, and is useful for various electronic devices.

本発明の一実施形態の半導体装置の一部を示す断面図Sectional drawing which shows a part of semiconductor device of one Embodiment of this invention 図１の半導体装置に使用するパッケージの斜視図The perspective view of the package used for the semiconductor device of FIG. 図２のパッケージの分解斜視図2 is an exploded perspective view of the package of FIG. 図１の半導体装置を製造するワイヤボンド時の断面図Sectional drawing at the time of wire bonding which manufactures the semiconductor device of FIG. ワイヤボンド部分の平面図Plan view of wire bond part ワイヤボンド部分の一部拡大図Partial enlarged view of wire bond part 内部端子の変形例を示す図The figure which shows the modification of an internal terminal 本発明の他の実施形態の半導体装置のワイヤボンド部分の平面図The top view of the wire bond part of the semiconductor device of other embodiment of this invention 本発明のさらに他の実施形態の半導体装置のワイヤボンド部分の平面図および断面図The top view and sectional drawing of the wire bond part of the semiconductor device of further another embodiment of this invention 従来の半導体装置の断面図Sectional view of a conventional semiconductor device 図１０の半導体装置に使用するパッケージの斜視図The perspective view of the package used for the semiconductor device of FIG. 図１０の半導体装置のワイヤボンド部分の断面図Sectional drawing of the wire bond part of the semiconductor device of FIG. 図１０の半導体装置のワイヤボンド部分の平面図FIG. 10 is a plan view of a wire bond portion of the semiconductor device of FIG.

符号の説明Explanation of symbols

１ 半導体チップ
２ パッケージ
３ 電極パッド
４ 導体
５ ワイヤ
８ 内部端子 1 Semiconductor chip 2 Package 3 Electrode pad 4 Conductor 5 Wire 8 Internal terminal

Claims (3)

半導体チップと、前記半導体チップを搭載した搭載部と前記半導体チップの外周に内部端子が対向した複数の導体とを有した基台と、前記半導体チップの電極パッドと前記導体の内部端子とを接続したワイヤとを具備した半導体装置において、前記内部端子は前記半導体チップに対向した先端側が広がった形状であることを特徴とする半導体装置。   Connecting a base having a semiconductor chip, a mounting portion on which the semiconductor chip is mounted, and a plurality of conductors with internal terminals facing the outer periphery of the semiconductor chip, and an electrode pad of the semiconductor chip and an internal terminal of the conductor In the semiconductor device comprising the above-described wire, the internal terminal has a shape in which a tip side facing the semiconductor chip is widened. 複数の導体の内部端子は半導体チップの外周に沿って千鳥配置されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the internal terminals of the plurality of conductors are staggered along the outer periphery of the semiconductor chip. 千鳥配置された内部端子の内、半導体チップにより近い内部端子に比べてより遠い内部端子が厚く形成されていることを特徴とする請求項２記載の半導体装置。   3. The semiconductor device according to claim 2, wherein among the internal terminals arranged in a staggered manner, the internal terminals farther from the internal terminals closer to the semiconductor chip are formed thicker.
JP2008111924A 2008-04-23 2008-04-23 Semiconductor device Pending JP2009266905A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018021209A1 (en) * 2016-07-28 2018-02-01 京セラ株式会社 Substrate for mounting semiconductor element and semiconductor device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018021209A1 (en) * 2016-07-28 2018-02-01 京セラ株式会社 Substrate for mounting semiconductor element and semiconductor device
CN109478537A (en) * 2016-07-28 2019-03-15 京瓷株式会社 Semiconductor element mounting substrate and semiconductor device
JPWO2018021209A1 (en) * 2016-07-28 2019-05-09 京セラ株式会社 Semiconductor device mounting substrate and semiconductor device
EP3493252A4 (en) * 2016-07-28 2020-04-15 KYOCERA Corporation Substrate for mounting semiconductor element and semiconductor device
US10777493B2 (en) 2016-07-28 2020-09-15 Kyocera Corporation Semiconductor device mounting board and semiconductor package
JP2021101475A (en) * 2016-07-28 2021-07-08 京セラ株式会社 Substrate for mounting semiconductor element and semiconductor device
JP7049500B2 (en) 2016-07-28 2022-04-06 京セラ株式会社 Substrate for mounting semiconductor devices and semiconductor devices
CN109478537B (en) * 2016-07-28 2022-08-19 京瓷株式会社 Substrate for mounting semiconductor element and semiconductor device

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