JP2009266012A - Backplane - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive backplane which can be diverted to a slave computer as well even while making it possible to mount many kinds of full-size CPU boards. <P>SOLUTION: The backplane 1 is incorporated in a computer 3 provided with the CPU board 31 for performing a model program for evaluation and a single or a plurality of I/O boards 32 connected with the CPU board 31 by a system bus for converting input/output data between the CPU board 31 and an evaluation object device 2, and is provided with a plurality of slots for mounting the CPU board 31 and the I/O board 32. A first master slot 11 corresponding to a full-size CPU board 31, a second master slot 12 corresponding to a half-size CPU board, and a plurality of slave slots 13 corresponding to the I/O board 32 are arrayed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a backplane provided with a slot into which a CPU board and a plurality of I / O boards can be mounted.

  Conventionally, various board computers have been used in various industrial fields. In such a board computer, a backplane provided with slots into which various function boards can be mounted is incorporated in a housing, and a CPU board, a memory board, an image processing board, and an A / D conversion board are installed in the corresponding slots. The expected function is exhibited by mounting an I / O board such as the above.

  Patent Document 1 describes an example in which a CPU board and a plurality of I / O boards are bus-connected via a backplane.

  A simulator used for development and evaluation of an electronic control device incorporated in a vehicle or the like is similarly configured.

However, such simulators also tend to become more complicated as the functions of vehicles become more advanced and digitized, requiring a number of I / O boards that cannot be accommodated by a single general-purpose backplane. Yes.
JP-A-11-328101

  A backplane 100 constituting such a board computer includes a pair of CPU board slots 200 in which a full-size CPU board compatible with PICMG can be mounted, and a plurality of PCI board slots 300 as shown in FIG. 1 or a pair of CPU board slots 400 into which a half-size CPU board can be mounted and a plurality of PCI board slots 300 as shown in FIG. Yes.

  When the number of I / O boards does not fit in the PCI board slot, the I / O board is divided into two housings, one of which is a master computer with a CPU board and some I / O boards and the other is the remaining I / O. A slave computer with an O-board is configured, and a bus bridge board for connecting the chassis 500 with a system bus must be installed on both sides.

  However, when the PICMG-compatible backplane 100 shown in FIG. 1A is adopted, a master-side bus bridge board needs to be mounted on a slave-side casing 500 without a CPU board. Since the board is not in general-purpose products, a dedicated board must be manufactured.

  Therefore, it is conceivable to employ the backplane 100 shown in FIG. 1B, but the type of half-size CPU board is limited, and it is difficult to obtain a CPU board having sufficient functions suitable for the purpose. There was a problem.

  In view of the above-described problems, an object of the present invention is to provide an inexpensive backplane that can be used as a slave computer while allowing a variety of types of full-size CPU boards to be mounted.

  In order to achieve the above-mentioned object, the characteristic configuration of the backplane according to the present invention is connected to a CPU board that executes a model program for evaluation, the CPU board and the system bus, and an input between the CPU board and the evaluation target device. A backplane incorporated in a computer having a single or a plurality of I / O boards for converting output data and provided with a plurality of slots for mounting the CPU board and the I / O board. A first master slot corresponding to the CPU board, a second master slot corresponding to the half-size CPU board, and a plurality of slave slots corresponding to the I / O board are arranged. .

  According to the configuration described above, when a computer equipped with the backplane is used as a master computer, a CPU board may be installed in the first master slot. Therefore, it is possible to use a full-size CPU board that has sufficient functions for the purpose and is easily available.

  Further, according to the above-described configuration, when a computer equipped with the backplane is used as a slave computer, a bus bridge board may be installed in the second master slot. Therefore, a half-size bus bridge board in which general-purpose products exist can be used.

  As described above, according to the present invention, it is possible to provide an inexpensive backplane that can be diverted as a slave computer while allowing a wide variety of full-size CPU boards to be mounted. It was.

  Below, the backplane by this invention and the usage method of a backplane are demonstrated.

  In this embodiment, as shown in FIGS. 2 and 3, the backplane 1 according to the present invention is incorporated in a simulator 3 as an example of a computer that evaluates an electronic control device (hereinafter referred to as ECU) 2 of a vehicle. .

  The ECU 2 is, for example, an ECU that controls an engine, an ECU that controls an automatic transmission, an ECU that controls a brake, or the like. When evaluating the ECU that controls the engine, the simulator 3 calculates simulation information (for example, a crank pulse signal) based on a control signal (for example, a three-phase PWM signal) input from the ECU, and sends it to the ECU. Output.

  The simulator 3 is connected to a CPU board 31 for executing an evaluation model program (for example, a program for simulating an engine as a model when controlling an ECU for controlling the engine), and the CPU board 31 through a system bus. A single or a plurality of I / O boards 32 for converting input / output data between the board 31 and the ECU 2 as an evaluation target device, and a plurality of slots 11, 12, 13 for mounting the CPU board 31 and the I / O board 32. Are provided, an I / F unit 34 for converting input / output data between the I / O board 32 and the ECU 2, a power supply device 35 for supplying power to each part of the simulator 3, and the like. The system bus is formed on the backplane 1 as a wiring pattern.

  The CPU board 31 is mounted in a first master slot 11 to be described later among a plurality of slots, and a CPU that executes an application under the management of the operating system, a ROM that stores an operating system and a model program that is an application. And a first memory such as an EEPROM, a second memory such as a RAM in which control information is stored, a LAN interface for connection to the host computer 4, peripheral circuits, and the like.

  Here, the host computer 4 includes the LAN connector CN6 of the CPU board 31 among the connectors of the boards that appear when the board is inserted into the board insertion port 8 provided in the simulator 3 indicated by the dashed-dotted ellipse in FIG. And a LAN connector provided in the host computer 4 are connected by a LAN cable 7.

  Then, the host computer 4 loads the test data used in the simulation to the second memory of the CPU board 31 via the LAN interface and controls the CPU board 31 in an integrated manner to start and stop the simulation, and to set the simulation conditions. In addition to setting, control information input from the ECU 2 is collected, and the control information is displayed on a monitor provided in the host computer 4.

  The I / O board 32 is mounted in a slave slot 13 to be described later among a plurality of slots. The I / O board 32 is provided with a calculation block including a CPU, FPGA, ASIC, and the like and a memory for storing calculation results. The calculated logical simulation information is converted into a physical simulation signal corresponding to the ECU 2, and the physical control signal output from the ECU 2 is converted into logical control information.

  The I / F unit 34 is provided with an interface circuit that electrically connects power lines and signal lines (converts signal levels and signal forms) between the I / O board 32 and the ECU 2 and relay-connects them. .

  The I / F unit 34 and the ECU 2 are a signal transmission harness 6 used in an actual vehicle between a connector CN 2 provided on one surface of the I / F unit 34 and a connector CN 3 provided on the ECU 2. Connected with.

  The I / F unit 34 and the I / O board 32 include a connector CN4 (CN41 and 42 in FIG. 2) provided on the other surface of the I / F unit 34 and a CN5 (FIG. 2) provided on the I / O board. Then, CN 51 and CN 52) are connected by a signal transmission cable 38 such as a PCI bus cable.

  The power supply device 35 is, for example, an ATX standard power supply unit that generates a plurality of types of voltages from a commercial power supply, and supplies power of an appropriate voltage to the CPU board 31, the I / O board 32, the I / F unit 34, and the like. To do.

  The electric power is supplied to the I / F unit 34 via the power cable 36 connecting the power supply device 35 and the I / F unit 34. In addition, power is supplied to the backplane 1 through a power cable 37 that connects the power supply device 35 and the power connector CN1 of the backplane 1, and through a power supply wiring pattern formed on the backplane 1. It is supplied to the CPU board 31, the I / O board 32, and the like.

  The backplane 1 includes a first master slot 11 corresponding to a full-size CPU board 31, a second master slot 12 corresponding to a half-size CPU board, and a plurality of I / O boards 32 corresponding to the I / O board 32. Slave slots 13 (131 to 139) are arranged. Here, the full-size CPU board 31 is a CPU board having a size substantially the same as the width of the AT-spec motherboard, and the half-size CPU board 31 is substantially half the size of the full-size CPU board 31. This is the CPU board.

  Further, on the backplane 1, a signal wiring pattern for interconnecting corresponding pins (for example, pins having the same number) of each of the slots 11, 12, and 13 constituted by a plurality of pins is formed as a system bus. .

  The first master slot 11 is, for example, a slot into which a PICMG compatible CPU board 31 having a PCI interface serving as a system bus can be mounted.

  Since the PICMG compatible CPU board 31 includes both the edge connector of the ISA interface and the edge connector of the PCI interface, the first master slot 11 includes the slot 11A corresponding to the edge connector of the ISA interface and the PCI interface. A slot 11B corresponding to the edge connector (hereinafter referred to as a PCI-compatible slot) is provided.

  The second master slot 12 is, for example, a slot into which a half-size CPU board having a PCI interface can be mounted, and includes a PCI-compatible slot.

  The slave slot 13 is, for example, a PCI board slot. Like the second master slot 12, the slave slot 13 includes a PCI-compatible slot, but unlike the master slots 11 and 12, the CPU board 31 is provided. It is impossible to put on and use the function.

  Note that the slave slot 13 is not limited to the PCI board slot. For example, instead of the PCI board slot or in addition to the PCI board slot, a PCI mezzanine card (hereinafter referred to as PMC) is described. ) May be a slot that can be mounted (hereinafter referred to as a PMC-compatible slot).

  2 and 3, a PMC-compatible slot is provided in addition to the PCI board slot, and the PMC-compatible slot 13A is arranged at a location on the backplane 1 on the power supply device 35 side.

  The PMC is provided with a connector CN10 on the surface of the PMC for mounting in the PMC compatible slot 13A. That is, the PMC is mounted in the PMC corresponding slot 13A in parallel with the backplane 1, as shown in FIG. Therefore, a space not occupied by the PMC is generated above the PMC.

  In the simulator 3 of this embodiment, the internal cables 36, 37, and 38 for connecting the CPU board 31, the I / O board 32, the I / F unit 34, and the power supply device 35 are located in the space. In many cases, the slots 11, 12, and 13 cannot be arranged.

  The reason is as follows. The CPU board 31 and the I / O board 32 are mounted in the slots 11, 12, and 13 by edge connectors. That is, the boards 31 and 32 have a structure in which connectors for mounting in the slots 11, 12 and 13 are provided on the side surfaces of the boards 31 and 32. Therefore, when these boards 31 and 32 are mounted in the slots 11, 12, and 13, the upper portions of the slots 11, 12, and 13 are occupied by the printed circuit board, and the space is not generated.

  However, when the PMC is mounted, a space not occupied by the PMC is generated as described above, so that interference between the PMC and the internal cable can be prevented. The number of slave slots 13 can be increased by providing the PMC-compatible slots 13A where the slave slots 13 cannot be provided. Furthermore, by providing the PMC-compatible slot 13A in addition to the PCI board slot, the slave slot 13 can support both the PCI board and the PMC, and the versatility can be improved.

  The number of devices that can be connected to the CPU board 31, that is, fan-out is limited by the current drive capability of the CPU board 31. The fan-out number of the CPU board 31 of this embodiment is 4. However, since the backplane 1 of this embodiment has nine slave slots 13 (or ten if the PMC-compatible slot 13A is provided), the CPU board 31 alone is installed in all the slave slots 31. Only four of the I / O boards 32 can be driven.

  Therefore, the backplane 1 of the present embodiment includes a bus bridge IC 14 connected to the master slots 11 and 12 via a system bus. In this case, the CPU board 31 drives the I / O board 32 and the bus bridge IC 14 installed in the three slave slots 131 to 133, and the bus bridge IC 14 is installed in the remaining slave slots 134 to 139. Then, the I / O board 32 is driven. When the PMC-compatible slot 13A is provided, the PMC mounted in the PMC-compatible slot 13A is also driven by the bus bridge IC 14.

  According to the above-described configuration, the PICMG compatible CPU board is a full-size CPU board. That is, as a board to be installed in the first master slot 11, it is possible to use a full-size CPU board that has sufficient functions for the purpose and is easily available. Further, according to the above-described configuration, a half-size bus bridge board having a general-purpose product can be installed in a slot in which a half-size board having a PCI interface can be installed.

  When the electronic control device 2 is evaluated using a plurality of simulators 3 (for example, two simulators 3A and 3B), the electronic control device 2 is evaluated by the plurality of simulators 3 by adopting the configuration shown in FIG. A master / slave simulator can be configured.

  In other words, the master simulator 3A is configured by mounting the CPU board 31 in the first master slot 11 and mounting the I / O board 32 and the system bus bridge board 33 in the slave slot 13. The slave simulator 3B is configured by installing the bridge board 33 in the second master slot 12 and the I / O board 32 in the slave slot 13, and the bridge boards 33 are connected by the bus cable 5. A master / slave simulator is configured.

  The bridge board 33 is a board that relays the system bus of the master simulator 3A and the system bus of the slave simulator 3B, and is a PCI-PCI bridge board or a high-speed LAN interface circuit such as a star fabric, for example.

  The internal configurations of the master simulator 3A and the slave simulator 3B are the same as those in FIGS. 2 and 3 except for the presence of the bridge board 33.

  According to the configuration described above, the master simulator 3A and the slave simulator 3B can be easily diverted by attaching and detaching the board as described below. Hereinafter, the diversion will be described in detail.

  As shown in FIG. 7A, in the slave simulator 3B, the bridge board 33 is installed in the second master slot 12, and in the master simulator 3A, the CPU board 31 is installed in the first master slot 11. A bridge board 33 is mounted in the slave slot 13. FIG. 7B shows an example in which the bridge board 33 is mounted in the PMC-compatible slot 13A as the slave slot 13 of the master simulator 3A.

  In such a mounted state, it is possible to switch to the master simulator 3A by detaching the system bus bridge board 33 from the slave simulator 3B and mounting the CPU board 31 in the first master slot 11.

  Conversely, the CPU board 31 is removed from the master simulator 3A, and the system board bridge board 33 can be mounted in the second master slot 12 to switch to the slave simulator 3B.

  As described above, since the backplane 1 includes both a full-size master slot and a half-size master slot, the full-size CPU board 31 and the half-size bridge board 33 are both general-purpose products. Therefore, the master simulator 3A and the slave simulator 3B can be diverted only by a simple operation of mounting and dismounting from the master slot.

  Hereinafter, another embodiment will be described. In the above-described embodiment, the case where a plurality of simulators 3 are connected to one electronic control device 2 has been described. However, as illustrated in FIG. 5, the simulator 3 includes a plurality of electronic control devices 2 (2 in FIG. 5). It may be connected to the electronic control device 21, 22).

  In this case, the plurality of simulators 3 can evaluate the communication between the two electronic control devices 21 and 22.

  For example, control information is input from the electronic control unit 21 to the simulator 3A, and either or both of the simulators 3A and 3B calculate return information to the electronic control unit 22 based on the control information, and the calculation result is output from the simulator 3B. Is output. Conversely, control information is input from the electronic control unit 22 to the simulator 3B, and either or both of the simulators 3A and 3B calculate return information to the electronic control unit 21 based on the control information, and the calculation result from the simulator 3A. Is output. The simulator 3 evaluates whether the content of the communicated control information is correct, the transfer time of the control information between the electronic control devices 21 and 22, and the like.

  In the above-described embodiment, the case where the backplane 1 according to the present invention is incorporated in the simulator 3 that evaluates the ECU 2 of the vehicle has been described, but the configuration is not limited thereto.

  That is, if the computer or device is used as either a master or a slave and needs to be switched between the master and the slave depending on the application, the backplane 1 according to the present invention is incorporated. be able to. For example, the backplane 1 may be incorporated in a simulator that evaluates other than the ECU 2 of the vehicle, or may be incorporated in a computer or device other than the simulator.

  The embodiment described above describes an example for realizing the present invention, and the specific configuration of each part should be appropriately changed and designed according to the system to be constructed as long as the effects of the present invention are achieved. Is possible.

(A) is explanatory drawing of the board computer provided with a pair of full size CPU board slot, (b) is explanatory drawing of the board computer provided with a pair of half size CPU board slot. Perspective view of simulator Block diagram of simulator Block diagram of the simulator when multiple simulators are interconnected Block diagram of the simulator when the simulator is connected to multiple electronic control units Explanatory drawing which shows mounting | wearing to PMC corresponding slot 13A of PMC (A) is an explanatory diagram showing the connection of a master / slave system simulator, (b) is an explanatory diagram showing the connection of a master / slave system simulator in which the bridge board 33 is mounted in a slot corresponding to the PMC of the master simulator.

Explanation of symbols

1: Backplane 3: Simulator (computer)
5: Bus cable 11: First master slot 12: Second master slot 13: Slave slot 31: CPU board 32: I / O board 33: Bridge board

Claims (5)

A CPU board that executes a model program for evaluation, and a single or plural I / O boards that are connected to the CPU board via a system bus and convert input / output data between the CPU board and the evaluation target device A backplane incorporated in a computer and provided with a plurality of slots for mounting the CPU board and I / O board;
A first master slot corresponding to a full-size CPU board, a second master slot corresponding to a half-size CPU board, and a plurality of slave slots corresponding to the I / O board are arranged. Backplane.   The first master slot is a slot into which a PICMG-compatible CPU board having a PCI interface serving as the system bus can be mounted, and the second master slot is a half-size CPU board having a PCI interface. 2. The backplane according to claim 1, wherein the backplane is a slot that can be mounted, and the slave slot is a PCI board slot.   A master simulator is configured by mounting the CPU board in the first master slot and mounting the I / O board and the system bus bridge board in the slave slot, and the system bus bridge board. Is installed in the second master slot, and the I / O board is installed in the slave slot to form a slave simulator, and the bridge boards are connected by a bus cable to form a master / slave system. The method of using a backplane according to claim 1 or 2, wherein said simulator can be configured.   4. The method of using a backplane according to claim 3, wherein a bridge board of the system bus is detached from the slave simulator, and the CPU board is switched to the master simulator by mounting the CPU board in the first master slot.   The method of using the backplane according to claim 3 or 4, wherein the CPU board is detached from the master simulator and the system board is switched to the slave simulator by mounting the bridge board of the system bus in the second master slot.

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