JP2009260298A - Crystallinity evaluation method of single-crystal semiconductor film and manufacturing method of semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate capable of forming a semiconductor element having favorable crystallinity and high performance. <P>SOLUTION: A single-crystal semiconductor substrate having a brittle layer is bonded to a base substrate via an insulating layer; the single-crystal semiconductor substrate is separated with the brittle layer as a boundary by heat treatment; a single-crystal semiconductor layer is fixed on the base substrate; and laser beams are applied to the single-crystal semiconductor layer for turning the single-crystal semiconductor layer into a partially melted state for recrystallization and recovering crystal defects. In concentration distribution in the depth direction of the single-crystal semiconductor layer after the recrystallization, a carbon concentration has the local maximum. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a method for evaluating crystallinity of a single crystal semiconductor film and a method for manufacturing a semiconductor substrate using the same.

In recent years, integrated circuits using an SOI (Silicon on Insulator) substrate in which a thin single crystal semiconductor film is present on an insulating surface instead of a bulk silicon wafer have been developed. By taking advantage of the thin single crystal silicon layer formed on the insulating film, the transistors in the integrated circuit can be formed completely separated from each other, and the transistors can be made fully depleted, High-value-added semiconductor integrated circuits such as high integration, high speed driving, and low power consumption can be realized.

As one of methods for manufacturing an SOI substrate, a hydrogen ion implantation separation method in which hydrogen ion implantation and separation are combined is known. An outline of a method for manufacturing an SOI substrate by a hydrogen ion implantation separation method will be described below. First, an ion-implanted layer is formed at a predetermined depth from the surface by implanting hydrogen ions into a silicon wafer to be a peeling substrate using an ion implantation method. Next, the silicon wafer implanted with hydrogen ions is bonded (bonded) to another silicon wafer through the silicon oxide film. After that, by performing heat treatment, the separation silicon wafer into which hydrogen ions are implanted with the ion implantation layer as a cleavage plane is separated into a thin film, and a single crystal silicon film can be formed on the separation silicon wafer. . In addition, the hydrogen ion implantation separation method may be referred to as a smart cut (registered trademark) method.

In addition, a method of forming a single crystal silicon film on a base substrate made of glass using such a hydrogen ion implantation separation method has been proposed (see, for example, Patent Documents 1 and 2). In Patent Document 1, in order to remove a defect layer formed by ion implantation and a step of several nm to several tens of nm on the peeling surface, the peeling surface is mechanically polished. In Patent Document 2, after the peeling process, laser light is irradiated to improve the crystal quality of the semiconductor thin film layer and to firmly bond the semiconductor thin film layer and the transparent insulating substrate.

JP-A-11-097379 JP 2005-252244 A

In the case of forming a single crystal semiconductor film by a hydrogen ion implantation separation method, defects in the single crystal semiconductor film are increased by ion implantation. In the case where a single crystal semiconductor film has a large number of defects, for example, defect levels are likely to be formed at the interface with the gate insulating film, so that the characteristics of a semiconductor element manufactured using the defects are not good. .

Conventionally, crystal defects in a semiconductor film attached to a silicon wafer have been removed by heating at a high temperature (for example, 800 ° C. or higher). However, when a glass substrate is used as a base substrate, a large-area and inexpensive SOI substrate can be manufactured. However, since a strain point is 700 ° C. or less and heat resistance is low, removal of crystal defects in a single crystal semiconductor film is eliminated. However, such a high temperature process cannot be used.

Patent Document 2 proposes a method for improving the crystallinity of a single crystal semiconductor film by irradiating a laser to the single crystal semiconductor film after peeling. However, when the laser beam irradiation intensity is too low, defect recovery is not sufficient, and when the laser beam irradiation intensity is too high, the single crystal semiconductor film is microcrystallized and crystallinity is lowered. Problem arises. For this reason, it is necessary to optimize the irradiation intensity of the laser light applied to the single crystal semiconductor film, but the optimal irradiation intensity of the laser light varies depending on the thickness of the single crystal semiconductor film, the irradiation atmosphere, etc. It is not easy to uniformly determine the optimal laser beam irradiation intensity.

In view of the above problems, an object of one embodiment of the present invention is to provide a method for evaluating crystallinity of a single crystal semiconductor film which is necessary for setting optimal irradiation conditions of laser light.

Another object of one embodiment of the present invention is to provide a semiconductor substrate that can form a high-performance semiconductor element and a manufacturing method thereof by optimizing irradiation conditions of laser light. .

One of the crystallinity evaluation methods of the present invention is a method in which a laser is separated from an embrittlement layer formed in a region having a predetermined depth from the surface of a single crystal semiconductor substrate and fixed on a base substrate through an insulating layer. When the carbon concentration distribution in the depth direction of the single crystal semiconductor layer is measured for the single crystal semiconductor layer that has been re-single-crystallized by light irradiation, and the carbon concentration has a maximum, the crystallinity of the single crystal semiconductor layer is It is determined to be excellent.

One of the crystallinity evaluation methods of the present invention is that after being separated from an embrittlement layer formed in a region having a predetermined depth from the surface of a single crystal semiconductor substrate and fixed on a base substrate through an insulating layer. The carbon concentration and hydrogen concentration distribution in the depth direction of the single crystal semiconductor layer are measured with respect to the single crystal semiconductor layer that has been re-single-crystallized by laser light irradiation. The carbon concentration has a maximum and the hydrogen concentration is When there is no shoulder peak corresponding to the maximum of the carbon concentration, it is determined that the crystallinity of the single crystal semiconductor layer is excellent.

Note that in one embodiment of the present invention, the bonding layer can be formed not only on the surface of the single crystal semiconductor substrate but also on the surface of the base substrate. Further, the bonding layer may be formed only on the surface of the base substrate.

In this specification, a shoulder peak refers to a shoulder seen in the vicinity of an interface with an insulating layer in a concentration distribution (profile) in the depth direction of a single crystal semiconductor layer.

By using one embodiment of the present invention, the crystallinity of a single crystal semiconductor film can be evaluated by a simple method. Further, by using this evaluation method, it becomes easy to optimize the irradiation condition of the laser beam, and a single crystal semiconductor layer with favorable crystallinity can be efficiently manufactured.

Therefore, a high-performance semiconductor element can be efficiently formed using the semiconductor substrate according to one embodiment of the present invention.

The figure shown about an example of the irradiation process of a laser beam. The figure which shows element concentration distribution of the depth direction of a single crystal semiconductor layer. The figure which shows the diffusion coefficient of the hydrogen atom and carbon atom in a molten state or a crystalline state. 10A and 10B illustrate a manufacturing process of a semiconductor substrate. 10A and 10B illustrate a manufacturing process of a semiconductor device. 10A and 10B illustrate a manufacturing process of a semiconductor device. 2A and 2B are a plan view and a cross-sectional view of a semiconductor device. FIG. 16 illustrates an electronic device using a semiconductor device. FIG. 16 illustrates an electronic device using a semiconductor device. The figure which measured the single crystal semiconductor layer surface after recrystallization by the EBSP method. The graph which shows the lifetime evaluation measurement result of the single crystal semiconductor layer after recrystallization. The probability statistical distribution map which measured the S value of TFT produced using the single crystal semiconductor layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and various changes can be made in form and details without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals may be used in common in different drawings.

(Embodiment 1)
In this embodiment mode, a crystallinity evaluation method of the present invention will be described with reference to FIGS.

FIG. 1 shows a step of irradiating a plurality of regions of the single crystal semiconductor layer 112 provided on the monitor substrate with laser light 113. In FIG. 1, a single crystal semiconductor layer 112 separated from a single crystal semiconductor substrate is provided over a base substrate 110 with an insulating layer 111 interposed therebetween. In FIG. 1, it is assumed that laser light 113 is irradiated on three regions A to C of the single crystal semiconductor layer 112 under different energy density conditions. Note that as described above, the single crystal semiconductor layer 112 after being separated from the single crystal semiconductor substrate has impaired flatness and crystallinity and increased crystal defects. Note that as the single crystal semiconductor substrate, for example, a single crystal silicon substrate, a germanium substrate, or a compound semiconductor substrate such as gallium arsenide or indium phosphide can be used. In this embodiment mode, a silicon wafer is used as the single crystal semiconductor substrate.

When the laser beam 113 is irradiated, the single crystal semiconductor layer 112 absorbs the laser beam 113 and the temperature of the portion irradiated with the laser beam 113 is increased. When the temperature of this portion is equal to or higher than the melting point of the single crystal semiconductor layer 112, the single crystal semiconductor layer 112 is melted and defects can be repaired. When the laser beam 113 is no longer irradiated, the temperature of the melted portion of the single crystal semiconductor layer 112 is lowered, and the melted portion is eventually solidified and recrystallized (re-single-crystallized). Thus, the crystallinity of the single crystal semiconductor layer can be recovered. At the same time, the flatness of the surface of the single crystal semiconductor layer can be recovered. Note that laser light for melting the single crystal semiconductor layer 112 is emitted from above the single crystal semiconductor layer 112.

As the base substrate 110, for example, a glass substrate can be used. In this embodiment, a glass substrate having a thickness of 0.7 mm is used. As the insulating layer 111, for example, a single layer such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film, or a film in which these layers are stacked can be used. These films can be formed using a thermal oxidation method, a CVD method, a sputtering method, or the like. In the case where the insulating layer 111 is formed by a CVD method, a chemical vapor phase is used as the insulating layer 111 using an organic silane such as tetraethoxysilane (abbreviation: TEOS: chemical formula Si (OC ₂ H ₅ ) ₄ ). A silicon oxide film manufactured by a growth method can be used. In addition, an insulating film containing Si as a main component, such as a silicon carbide (SiC) film, may be used. Note that the insulating layer 111 preferably includes a barrier layer capable of preventing diffusion of sodium from the base substrate 110 side. As the barrier layer, a silicon nitride oxide film or a silicon nitride film can be used. In this embodiment, the insulating layer 111 has a structure in which a silicon oxide film, a silicon nitride oxide film, and a silicon oxynitride film are stacked in this order from the base substrate 110 side.

Note that the silicon oxynitride film has a higher oxygen content than nitrogen and has a Rutherford backscattering method (RBS) and a hydrogen forward scattering method (HFS). As a concentration range, oxygen is included in the range of 50 to 70 atomic%, nitrogen is 0.5 to 15 atomic%, Si is 25 to 35 atomic%, and hydrogen is 0.1 to 10 atomic%. Means what In addition, the silicon nitride oxide film has a composition containing more nitrogen than oxygen. When measured using RBS and HFS, the concentration range of oxygen is 5 to 30 atomic%, nitrogen. Is contained in the range of 20-50 atomic%, Si is 25-35 atomic%, and hydrogen is 15-30 atomic%. However, when the total number of atoms constituting silicon oxynitride or silicon nitride oxide is 100 atomic%, the content ratio of nitrogen, oxygen, Si, and hydrogen is included in the above range.

The laser oscillator that oscillates the laser beam 113 may be any of a continuous wave laser, a pseudo continuous wave laser, and a pulsed laser, but a pulsed laser is preferably used. This is because high-energy pulsed laser light can be instantaneously oscillated, and it becomes easy to create a molten state. The oscillation frequency is preferably about 1 Hz to 10 MHz.

Examples of the laser oscillator include an excimer laser such as a KrF laser, and a gas laser such as an Ar laser and a Kr laser. Other solid-state lasers include YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, KGW laser, KYW laser, alexandrite laser, Ti: sapphire laser, Y ₂ O ₃ laser, and the like. An excimer laser is a pulsed laser, but some solid-state lasers such as a YAG laser can be a continuous wave laser, a pseudo continuous wave laser, or a pulsed laser.

In this embodiment, a XeCl excimer laser is used as the laser oscillator, and the wavelength of the laser beam 113 is 308 nm. In addition, the regions A to C of the single crystal semiconductor layer 112 are irradiated with laser light 113 at different energy densities. Specifically, the region A is irradiated with the laser light 113 with the energy density of the condition A, the region B with the energy density of the condition B, and the region C with the energy density of the condition C. Conditions A to C are as follows.
Condition A. 568 mJ / cm ²
Condition B. 584 mJ / cm ²
Condition C.I. 600 mJ / cm ²

Depending on the energy density of the irradiated laser beam 113, the element concentration distribution of the single crystal semiconductor layer 112 in each region after the laser beam irradiation is characteristic. FIG. 2 shows an example of the concentration distribution in the depth direction of each region of the single crystal semiconductor layer 112 irradiated with the laser light 113 under the irradiation conditions of the above conditions A to C. In FIG. 2A, the horizontal axis indicates the depth (nm) from the surface of the single crystal semiconductor layer 112, and the vertical axis indicates the carbon concentration (arbitrary unit). In FIG. 2B, the horizontal axis indicates the depth (nm) from the surface of the single crystal semiconductor layer 112, and the vertical axis indicates the hydrogen concentration (arbitrary unit). 2A and 2B, a graph indicated by a dotted line indicates a distribution of carbon concentration or hydrogen concentration before the laser beam 113 is irradiated. Note that secondary ion mass spectrometry (SIMS) can be preferably used as a method for analyzing the concentration distribution in the depth direction of the element.

As shown in FIG. 2A, the single crystal semiconductor layer irradiated with the laser light has a higher carbon concentration than the non-irradiated single crystal semiconductor layer because carbon in the atmosphere is taken into the film at the time of irradiation. In addition, when laser light is irradiated under the conditions A and B, the carbon concentration distribution in the single crystal semiconductor layer 112 has a maximum. That is, the single crystal semiconductor layer irradiated under the conditions A and B has a concentration change in the film, and the carbon concentration on the surface side is higher than the carbon concentration on the interface side with the insulating layer. Further, the local maximum exists in a region near 20 nm from the interface with the insulating layer in the condition A, and exists in a region near 10 nm from the interface with the insulating layer in the condition B. That is, the maximum appears in the region closer to the interface with the insulating layer 111 under the condition B where the energy density is larger than the condition A. On the other hand, when laser light is irradiated under the condition C, the maximum in the distribution of carbon concentration in the single crystal semiconductor layer 112 is not observed.

From FIG. 2B, the single crystal semiconductor layer 112 irradiated with laser light is not irradiated because hydrogen contained in the single crystal semiconductor layer is released into the atmosphere or an insulating layer at the time of irradiation. As compared with the above, the hydrogen concentration on the surface side of the single crystal semiconductor layer 112 is reduced. In addition, when laser light is irradiated under the condition A, the hydrogen concentration in the single crystal semiconductor layer 112 has a shoulder peak. That is, in the single crystal semiconductor layer irradiated under the condition A, a gradual change in hydrogen concentration is observed in the film. Further, the shoulder peak is seen at a position substantially corresponding to the position of the maximum carbon concentration. On the other hand, when laser light is irradiated under conditions B and C, no shoulder peak can be confirmed.

The above is summarized as follows.
In the region A of the single crystal semiconductor layer irradiated with the laser light under the condition A, the carbon concentration has a maximum in the element concentration distribution of the single crystal semiconductor layer. Moreover, it has a shoulder peak of hydrogen concentration corresponding to the maximum of the carbon concentration.
In the region B of the single crystal semiconductor layer irradiated with the laser light under the condition B, the carbon concentration has a maximum in the element concentration distribution of the single crystal semiconductor layer. Moreover, there is no shoulder peak of hydrogen concentration corresponding to the maximum of the carbon concentration.
In the region C of the single crystal semiconductor layer irradiated with the laser light under the condition C, the maximum concentration of carbon and the shoulder peak of hydrogen concentration cannot be confirmed in the element concentration distribution of the single crystal semiconductor layer.

The present inventors determined that the difference in concentration of carbon atoms and hydrogen atoms in the single crystal semiconductor layer after recrystallization caused by the difference in energy density of laser light depends on the melting state of the single crystal semiconductor layer during laser light irradiation. Then I considered it. In other words, hydrogen atoms or carbon atoms in the single crystal semiconductor layer (a silicon layer in this embodiment) depend on whether the single crystal semiconductor layer is in a molten state or a crystalline state when irradiated with laser light. Because the behavior changes, a concentration difference occurs near the solid-liquid interface.

FIG. 3 shows diffusion coefficients of carbon atoms and hydrogen atoms in silicon in a crystalline state and a molten state calculated by using the classical molecular dynamics method. In FIG. 3, the horizontal axis indicates temperature (° C.), and the vertical axis indicates the diffusion coefficient (cm ² / s) of carbon atoms or hydrogen atoms. A black circle indicates the diffusion coefficient of hydrogen atoms, and a white circle indicates the diffusion coefficient of carbon atoms. Since the melting point of silicon is 1410 ° C., the region below 1410 ° C. in FIG. 3 represents the atomic diffusion coefficient in the crystalline state, and the region above 1410 ° C. represents the atomic diffusion coefficient in the molten state. .

From FIG. 3, the diffusion coefficient of carbon atoms in crystalline silicon is remarkably small as 1 × 10 ⁻⁹ cm ² / s or less, and carbon atoms hardly diffuse in crystalline silicon. On the other hand, the diffusion coefficient of carbon atoms in the state in which the silicon is melted is increased as compared to crystalline silicon 10 ⁴ times or more. When the single crystal semiconductor layer irradiated with the laser beam is melted from the surface to the interface with the base insulating layer and is in a liquid state (hereinafter, completely melted), the entire thickness direction of the single crystal semiconductor layer The carbon concentration is uniform because it has a substantially uniform diffusion coefficient. On the other hand, in the single crystal semiconductor layer irradiated with laser light, the upper layer melts to become a liquid phase and the lower layer does not melt but remains a solid single crystal semiconductor (hereinafter referred to as a partially molten state). It has a difference of ¹⁰⁴ times or more of the diffusion coefficient, density difference between carbon concentration appears in the region near the solid-liquid interface due to the difference in the diffusion coefficient.

Further, from FIG. 3, the diffusion coefficient of hydrogen atoms in crystalline silicon is about 1 × 10 ⁻⁵ cm ² / s at the maximum, so that some of the atoms in the vicinity of the surface of the hydrogen atoms in crystalline silicon are in the atmosphere. It can be said that the change in the concentration of hydrogen atoms in the entire film is small. On the other hand, the diffusion coefficient of hydrogen atoms in the molten state of silicon is 10 times or more compared to the crystalline state, and is easily released into the atmosphere. When the single crystal semiconductor layer irradiated with laser light is in a completely molten state, hydrogen atoms near the surface are easily released into the atmosphere, and hydrogen atoms near the underlying insulating layer are not released directly into the atmosphere, but near the surface. And the gradient of the layer near the insulating layer is made smaller and moved so as to be uniform. Therefore, the hydrogen atom concentration in the entire single crystal semiconductor layer is greatly reduced as compared to before irradiation with laser light. On the other hand, when the single crystal semiconductor film irradiated with laser light is in a partially melted state, hydrogen atoms near the surface have a large diffusion coefficient, so the concentration is reduced by being released into the atmosphere. Therefore, the concentration change is small compared to the liquid phase. Therefore, the concentration of hydrogen atoms in the entire single crystal semiconductor layer is not uniform, and a concentration difference appears.

Therefore, the melting state of the single crystal semiconductor layer when irradiated with laser light can be determined from the concentration distribution of hydrogen atoms and carbon atoms in the single crystal semiconductor layer after recrystallization. In the SIMS measurement results shown in FIG. 2, the condition A and the condition B have a concentration difference (maximum) in carbon concentration, and the condition C has no maximum. Therefore, the conditions A and B are in a partially molten state, and the condition C is It can be seen that it is in a completely molten state. Further, since carbon atoms hardly diffuse in the crystalline state, the vicinity of the region where the concentration difference of the carbon concentration appears, that is, the vicinity of the maximum can be approximated to the solid-liquid interface.

Also, hydrogen atoms have a larger diffusion coefficient than carbon atoms, and in a partially molten state, the hydrogen atoms are in a melted region and a region heated to a temperature higher than the temperature at which hydrogen gas is released by heat conduction from the region. Concentration decreases. Therefore, the change in concentration becomes a gradual shoulder peak as compared with carbon atoms, and the position shifts downward (in the direction of the interface with the insulating layer) from the solid-liquid interface. Note that when the solid-liquid interface approaches the interface with the insulating film as in Condition B, the entire single crystal semiconductor layer is heated above the temperature at which hydrogen gas is released, and the hydrogen atoms are substantially uniform throughout the single crystal semiconductor layer. The difference in density disappears due to diffusion. When the carbon concentration has a maximum in the concentration distribution of the single crystal semiconductor layer, and there is no shoulder peak of the hydrogen concentration corresponding to the maximum of the carbon concentration, the single crystal semiconductor layer when irradiated with laser light has a lower insulation. It can be said that it is in a partially molten state melted to the vicinity of the interface with the layer.

Hereinafter, in the present specification, the single crystal semiconductor layer after recrystallization has a partially melted state having a hydrogen concentration shoulder peak corresponding to the maximum carbon concentration as a partially melted state in a narrow sense, and after recrystallization. A partially molten state in which the single crystal semiconductor layer has a maximum of carbon concentration and does not have a shoulder peak of hydrogen concentration corresponding to the maximum is expressed as a quasi-completely molten state. The quasi-completely melted single crystal semiconductor layer is melted to the vicinity of the interface with the lower insulating layer. For example, in this embodiment, the single crystal semiconductor layer when the laser light is irradiated under the condition A is a partially melted state in a narrow sense, and the single crystal semiconductor when the laser light is irradiated under the condition B The molten state of the layer is a quasi-completely molten state.

In the case where defects in the single crystal semiconductor layer are reduced by laser light irradiation, it is preferable to use a partially melted state in a narrow sense or a quasi-completely melted state. This is because, in a completely molten state, a part of the single crystal semiconductor layer is microcrystallized due to disordered nucleation after becoming a liquid phase, and crystallinity is lowered.

On the other hand, when a partially melted state in a narrow sense is used, crystal growth proceeds from an unmelted solid region, so that defects can be reduced while maintaining crystallinity. Further, in the case of a quasi-completely melted state, a little unmelted solid remains in the vicinity of the interface with the lower insulating layer, and crystal growth proceeds using this as a seed crystal. For this reason, defects can be reduced without lowering crystallinity due to solidification from the vicinity of the interface with the lower insulating layer. By setting the single crystal semiconductor layer to a quasi-completely melted state, even when a crystal defect exists up to the interface between the single crystal semiconductor layer and the lower insulating layer, the defect is repaired and the crystal of the single crystal semiconductor layer is recovered. It becomes possible to restore sex.

For the purpose of reducing defects and improving crystallinity of the single crystal semiconductor layer in the semiconductor substrate, the crystallinity of the single crystal semiconductor layer is good when the single crystal semiconductor layer irradiated with laser light is in a partially molten state. It is particularly good when in a quasi-completely melted state. That is, in the distribution of concentration in the depth direction of the single crystal semiconductor layer after laser irradiation, when the carbon concentration has a maximum, the crystallinity of the single crystal semiconductor layer is excellent, and the carbon concentration has a maximum. In addition, when the hydrogen concentration does not have a shoulder peak corresponding to the maximum, it can be said that the crystallinity of the single crystal semiconductor layer is particularly excellent. In addition, since the position of the maximum of the carbon concentration can be approximated to the solid-liquid interface in the partially molten state, when the maximum exists in the region within 20 nm, preferably within 10 nm from the interface with the lower insulating layer, the single crystal semiconductor It can be said that the crystallinity of the layer is good.

As shown above, the element concentration distribution in the depth direction of the single crystal semiconductor layer after recrystallization is measured, and the melting state of the single crystal semiconductor layer is determined, so that after recrystallization by an extremely simple method The crystallinity of the single crystal semiconductor layer can be evaluated.

Further, by using the evaluation method according to the present invention, it is easy to optimize the irradiation condition of the laser light, and thus a single crystal semiconductor layer with favorable crystallinity can be efficiently manufactured.

For example, in the case of manufacturing n (n ≧ 2) semiconductor substrates by laser processing of n (n ≧ 2) single crystal semiconductor layers, one of the n single crystal semiconductor layers is used as a monitor substrate. After the plurality of regions are irradiated with laser light under different energy density conditions, the crystallinity of the single crystal semiconductor layer after recrystallization is evaluated using the crystallinity evaluation method described in this embodiment. Then, (n−1) sheets are irradiated with laser light using the optimum irradiation condition of laser light detected using the evaluation method. Accordingly, (n−1) semiconductor substrates having a single crystal semiconductor layer with favorable crystallinity can be efficiently manufactured.

In addition, by selecting an optimal laser light irradiation intensity, generation of a defective substrate in which a single crystal semiconductor layer is microcrystallized in a semiconductor substrate manufacturing process can be suppressed. Therefore, a semiconductor substrate having a favorable single crystal semiconductor layer can be manufactured at low cost.

Note that this embodiment can be freely combined with any of the other embodiments.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor substrate using the evaluation method of Embodiment 1 will be described with reference to FIGS.

First, n (n ≧ 2) base substrates 110 are prepared (see FIG. 4A). As the base substrate 110, a light-transmitting glass substrate used in a liquid crystal display device or the like can be preferably used. A glass substrate having a strain point of 580 ° C. or higher and 680 ° C. or lower (preferably 600 ° C. or higher and 680 ° C. or lower) may be used. The glass substrate is preferably an alkali-free glass substrate. For the alkali-free glass substrate, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used, for example.

As the base substrate 110, a glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate, a substrate made of a semiconductor such as silicon, a substrate made of a conductor such as metal or stainless steel, or the like is used. You can also

Although not shown in this embodiment mode, an insulating layer may be formed on the surface of the base substrate 110. By providing the insulating layer, when an impurity (such as an alkali metal or an alkaline earth metal) is contained in the base substrate 110, the impurity can be prevented from diffusing into the semiconductor layer. The insulating layer may have a single layer structure or a laminated structure. Examples of the material forming the insulating layer include silicon oxide, silicon nitride, silicon oxynitride, and silicon nitride oxide.

Next, n (n ≧ 2) single crystal semiconductor substrates 100 are prepared. As the single crystal semiconductor substrate 100, for example, a single crystal semiconductor substrate made of a Group 4 element such as silicon, germanium, silicon germanium, or silicon carbide can be used. Of course, a substrate made of a compound semiconductor such as gallium arsenide or indium phosphide may be used. In this embodiment, a single crystal silicon substrate is used as the single crystal semiconductor substrate 100. Although there is no restriction | limiting in the shape and size of the single crystal semiconductor substrate 100, For example, circular semiconductor substrates, such as 8 inches (200 mm), 12 inches (300 mm), and 18 inches (450 mm), can be processed into a rectangle and used. . Note that in this specification, a single crystal means that the crystal structure is formed with a certain regularity and the crystal axes are in the same direction in any part. That is, it does not matter about the number of defects.

After the single crystal semiconductor substrate 100 is cleaned, an insulating layer is formed on the surface of the single crystal semiconductor substrate 100. Although an insulating layer may be omitted, it is preferable to provide an insulating layer in order to prevent contamination and surface damage of the single crystal semiconductor substrate 100 during subsequent ion implantation.

Next, the single crystal semiconductor substrate 100 is irradiated with an ion beam made of ions accelerated by an electric field through the insulating layer, and the embrittlement layer 102 is formed in a region at a predetermined depth from the surface of the single crystal semiconductor substrate 100. Form. The depth of the region where the embrittlement layer 102 is formed can be controlled by the acceleration energy of the ion beam and the incident angle of the ion beam. Here, the embrittlement layer 102 is formed in a region having a depth similar to the average penetration depth of ions.

The thickness of the semiconductor layer separated from the single crystal semiconductor substrate 100 is determined by the depth at which the embrittlement layer 102 is formed. The depth at which the embrittlement layer 102 is formed is 50 nm or more and 500 nm or less, preferably 50 nm or more and 200 nm or less from the surface of the single crystal semiconductor substrate 100.

When ions are implanted into the single crystal semiconductor substrate 100, an ion implantation apparatus or an ion doping apparatus can be used. In the ion implantation apparatus, a source gas is excited to generate ion species, the generated ion species are mass-separated, and an ion species having a predetermined mass is injected into a workpiece. The ion doping apparatus excites a process gas to generate ion species, and implants the generated ion species into a workpiece without mass separation. Note that an ion doping apparatus provided with a mass separator can also perform ion implantation with mass separation, as in the case of an ion implanter. In this specification, only one of the ion implantation apparatus and the ion doping apparatus is specified particularly when it is necessary to use the ion implantation apparatus, and if not particularly specified, any apparatus may be used for ion implantation. I will do it.

The ion implantation process in the case of using an ion doping apparatus can be performed, for example, under the following conditions.
・ Acceleration voltage: 10 kV to 100 kV (preferably 30 kV to 80 kV)
・ Dose amount 1 × 10 ¹⁶ ions / cm ² or more and 4 × 10 ¹⁶ ions / cm ² or less ・ Beam current density ² μA / cm ² or more (preferably 5 μA / cm ² or more, more preferably 10 μA / cm ² or more)

In the case of using an ion doping apparatus, a gas containing hydrogen can be used as a source gas in an ion implantation process. By using the gas, H ⁺ , H ₂ ⁺ , and H ₃ ⁺ can be generated as ionic species. When the gas is used as a source gas, it is preferable to implant a large amount of H ₃ ⁺ . Specifically, it is preferable that 70% or more of H ₃ ⁺ ions are included in the ion beam with respect to the total amount of H ⁺ , H ₂ ⁺ , and H ₃ ⁺ . Moreover, it is more preferable that the ratio of H ₃ ⁺ ions is 80% or more. By increasing the ratio of H ₃ ^{+ in} this manner, the embrittlement layer 102 can contain hydrogen at a concentration of 1 × 10 ²⁰ atoms / cm ³ or more. Thereby, peeling from the embrittlement layer 102 becomes easy. Further, by implanting a large amount of H ₃ ⁺ ions, the ion implantation efficiency is improved as compared with implanting H ⁺ and H ₂ ⁺ . That is, the time required for driving can be shortened.

When using an ion implantation apparatus, it is preferable to implant H ₃ ⁺ ions by mass separation. Of course, H ₂ ⁺ may be implanted. However, when an ion implantation apparatus is used, since ion species are selected and implanted, the efficiency of ion implantation may be reduced as compared with the case where an ion doping apparatus is used.

After the embrittlement layer 102 is formed, the insulating layer is removed and an insulating layer 111 is newly formed (see FIG. 4B). Here, the reason why the insulating layer is removed is that there is a high possibility that the insulating layer is damaged during the ion implantation. Note that it is not necessary to remove the insulating layer if damage to the insulating layer is not a problem.

Since the insulating layer 111 is a layer for forming bonding in bonding, the surface thereof preferably has high flatness. As such an insulating layer 111, for example, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas can be used. Note that although the insulating layer 111 has a single-layer structure in this embodiment, a stacked structure including two or more layers may be used.

Alternatively, the insulating layer 111 may be formed by performing heat treatment on the single crystal semiconductor substrate 100 in an oxidizing atmosphere. The thermal oxidation treatment is preferably performed by adding halogen in an oxidizing atmosphere. The insulating layer formed by adding halogen and performing thermal oxidation contains halogen, and halogen is contained at a concentration of 1 × 10 ¹⁶ atoms / cm ³ or more and 2 × 10 ²¹ atoms / cm ³ or less. Thus, a function as a protective film for capturing impurities such as metal and preventing contamination of the single crystal semiconductor substrate 100 can be exhibited.

After that, the n base substrates 110 and the n single crystal semiconductor substrates 100 are attached to each other (see FIG. 4C). Specifically, after the surfaces of the base substrate 110 and the insulating layer 111 are cleaned by a method such as ultrasonic cleaning, the surface of the base substrate 110 and the surface of the insulating layer 111 are placed in contact with each other. Pressure treatment is performed so that bonding is formed between the surface and the surface of the insulating layer 111. The formation of bonding is thought to involve Van der Waals forces and hydrogen bonding. Note that two or more single crystal semiconductor substrates may be attached to one base substrate.

Before the bonding is formed, the surface of the base substrate 110 or the insulating layer 111 may be subjected to oxygen plasma treatment or ozone treatment to make the surface hydrophilic. By this treatment, a hydroxyl group is added to the surface of the base substrate 110 or the insulating layer 111, so that hydrogen bonds can be formed efficiently.

Next, heat treatment is performed on the bonded base substrate 110 and single crystal semiconductor substrate 100 so that the bonding becomes strong. The heating temperature at this time needs to be a temperature at which separation in the embrittlement layer 102 does not proceed. For example, it can be less than 400 ° C., preferably 300 ° C. or less. The heat treatment time is not particularly limited, and optimal conditions may be set as appropriate based on the relationship between the processing speed and the bonding strength. In this embodiment mode, heat treatment is performed at 200 ° C. for 2 hours. Here, it is also possible to irradiate the microwave only to the region related to bonding and locally heat it. Note that the heat treatment may be omitted when there is no problem in the bonding strength.

Next, the single crystal semiconductor substrate 100 is separated into the single crystal semiconductor layer 112 and the single crystal semiconductor substrate 118 by the embrittlement layer 102 (see FIG. 4D). The single crystal semiconductor substrate 100 is separated by heat treatment. The heat treatment temperature can be based on the heat resistant temperature of the base substrate 110. For example, when a glass substrate is used as the base substrate 110, the heating temperature is preferably 400 ° C. or higher and 650 ° C. or lower. Note that heat treatment may be performed at 400 ° C to 700 ° C for a short time. Note that in this embodiment, heat treatment is performed at 600 ° C. for 2 hours.

By performing the heat treatment as described above, a volume change of minute holes formed in the embrittlement layer 102 occurs, and the embrittlement layer 102 is cracked. As a result, the single crystal semiconductor substrate 100 is cleaved along the embrittlement layer 102. Since the insulating layer 111 is attached to the base substrate 110, the single crystal semiconductor layer 112 separated from the single crystal semiconductor substrate 100 is fixed over the base substrate 110. Further, in this heat treatment, an interface related to the bonding between the base substrate 110 and the insulating layer 111 is heated, so that a covalent bond is formed at the interface related to the bonding, and the bonding force between the base substrate 110 and the insulating layer 111 is further increased. improves.

After that, the single crystal semiconductor layer 112 is irradiated with laser light 113 for the purpose of reducing defects in the single crystal semiconductor layer 112 (see FIG. 4E). Here, by using the crystallinity evaluation method described in Embodiment Mode 1, the irradiation condition of the laser beam 113 can be easily optimized. That is, the first base substrate provided with the first single crystal semiconductor layer is used as a monitor substrate, the monitor substrate is irradiated with laser light under a plurality of energy density conditions, and the single crystal after the laser light is irradiated The concentration distribution in the depth direction of the carbon concentration and hydrogen concentration of the semiconductor layer is measured. Next, the (n-1) single crystal semiconductor layers are irradiated with laser light at the optimum energy density detected using the monitor substrate.

For the irradiation with the laser beam 113, a pulsed laser is preferably used. This is because a high-energy pulsed laser beam can be oscillated instantaneously and it becomes easy to create a partially molten state. The oscillation frequency is preferably about 1 Hz to 10 MHz. More preferably, it is 10 Hz or more and 1 MHz or less. As the above-mentioned pulsed laser, Ar laser, Kr laser, excimer (ArF, KrF, XeCl) laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser A laser, a ruby laser, an alexandrite laser, a Ti: sapphire laser, a copper vapor laser, a gold vapor laser, or the like can be used. Note that a pulsed laser is preferably used for irradiation with the laser light 113, but the present invention is not limited to this. That is, use of a continuous wave laser is not excluded. As the continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser, Ti: There are sapphire lasers, helium cadmium lasers, and the like.

The wavelength of the laser beam 113 needs to be absorbed by the single crystal semiconductor layer 112. The wavelength may be determined in consideration of the penetration length of the laser beam. For example, in the case where the single crystal semiconductor layer 112 is a single crystal silicon layer, the thickness can be in the range of 200 nm to 700 nm. Further, the energy density of the laser light 113 can be determined in consideration of the wavelength of the laser light 113, the material of the single crystal semiconductor layer 112, the thickness of the single crystal semiconductor layer 112, and the like. The energy density of the laser beam 113 can be, for example, in the range of 300 mJ / cm ^{2 to} 800 mJ / cm ² . These conditions can also be optimized using the evaluation method of the first embodiment.

Irradiation with the laser light 113 can be performed in an atmosphere containing oxygen such as an air atmosphere or an inert atmosphere such as a nitrogen atmosphere. In order to irradiate the laser beam 113 in an inert atmosphere, the laser beam 113 may be irradiated in an airtight chamber and the atmosphere in the chamber may be controlled. In the case where a chamber is not used, a nitrogen atmosphere can be formed by spraying an inert gas such as nitrogen gas on the surface to be irradiated with the laser light 113. In addition, the irradiation with the laser beam 113 may be performed in a vacuum.

After irradiation with the laser light 113 as described above, a thinning process for reducing the thickness of the single crystal semiconductor layer 112 may be performed. In order to reduce the thickness of the single crystal semiconductor layer 112, an etching process (etch back process) in which one of dry etching or wet etching or a combination of both is applied may be applied. For example, if the single crystal semiconductor layer 112 is a layer made of a silicon material, a dry etching process using SF ₆ and 0 ₂ in the process gas, it is possible to thin the single crystal semiconductor layer 112.

Note that although an example in which etching is performed after planarization or the like by laser light irradiation is given in this embodiment mode, the present invention is not construed as being limited thereto. For example, etching treatment may be performed before laser light irradiation. In this case, the unevenness and defects on the surface of the semiconductor layer can be reduced to some extent by the etching treatment. Further, the above processing may be applied both before and after laser light irradiation. Further, the laser light irradiation and the above process may be repeated alternately. As described above, by using a combination of laser light irradiation and etching treatment, unevenness, defects, and the like on the surface of the semiconductor layer can be significantly reduced. Of course, it is not always necessary to use the above-described etching treatment or heat treatment.

Through the above steps, a semiconductor substrate including the single crystal semiconductor layer 120 (single crystal silicon semiconductor layer) with improved surface flatness and reduced defects can be manufactured (see FIG. 4F).

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment mode, a method for manufacturing a semiconductor device using the above-described semiconductor substrate will be described with reference to FIGS. Here, a method for manufacturing a semiconductor device including a plurality of transistors is described as an example of the semiconductor device. Note that various semiconductor devices can be formed by using a combination of the transistors described below.

FIG. 5A is a cross-sectional view of the semiconductor substrate manufactured according to Embodiment Mode 2. Note that in this embodiment, the case where the insulating layer 111 in Embodiment 2 has a two-layer structure is described.

In order to control the threshold voltage of the TFT, a p-type impurity such as boron, aluminum, or gallium, or an n-type impurity such as phosphorus or arsenic may be added to the single crystal semiconductor layer 120. The region to which the impurity is added and the kind of the impurity to be added can be changed as appropriate. For example, a p-type impurity can be added to the formation region of the n-channel TFT, and an n-type impurity can be added to the formation region of the p-channel TFT. When the above-described impurities are added, the dose may be set to about 1 × 10 ¹⁵ ions / cm ² or more and about 1 × 10 ¹⁷ ions / cm ² or less. After that, the single crystal semiconductor layer 120 is separated into islands, so that a semiconductor layer 702 and a semiconductor layer 704 are formed (see FIG. 5B).

Next, a gate insulating layer 706 is formed so as to cover the semiconductor layers 702 and 704 (see FIG. 5C). Here, a silicon oxide film is formed as a single layer by a plasma CVD method. In addition, a gate insulating layer 706 may be formed by forming a film containing silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like with a single-layer structure or a stacked structure.

As a manufacturing method other than the plasma CVD method, a sputtering method or a method using oxidation or nitridation by high-density plasma treatment can be given. The high-density plasma treatment is performed using a mixed gas of a rare gas such as helium, argon, krypton, or xenon and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In this case, high-density plasma can be generated at a low electron temperature by exciting the plasma by introducing a microwave. By oxidizing or nitriding the surface of the semiconductor layer with oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by such high-density plasma, 1 nm or more An insulating layer of 20 nm or less, preferably 2 nm or more and 10 nm or less is formed so as to be in contact with the semiconductor layer.

Since the oxidation or nitridation of the semiconductor layer by the high-density plasma treatment described above is a solid-phase reaction, the interface state density between the gate insulating layer 706, the semiconductor layer 702, and the semiconductor layer 704 can be extremely low. Further, by directly oxidizing or nitriding the semiconductor layer by high-density plasma treatment, variation in the thickness of the formed insulating layer can be suppressed. In addition, since the semiconductor layer has crystallinity, even when the surface of the semiconductor layer is oxidized by solid-phase reaction using high-density plasma treatment, non-uniform oxidation at the crystal grain boundary is suppressed and the uniformity is good. A gate insulating layer having a low interface state density can be formed. In this manner, by using the insulating layer formed by high-density plasma treatment for part or all of the gate insulating layer of the transistor, variation in characteristics can be suppressed.

A more specific example of a method for manufacturing an insulating layer by plasma treatment will be described. Nitrous oxide (N ₂ O) is diluted 1 to 3 times (flow rate ratio) with argon (Ar), and a microwave (2.45 GHz) of 3 kW to 5 kW under a pressure of 10 Pa to 30 Pa. ) Electric power is applied to oxidize or nitride the surfaces of the semiconductor layer 702 and the semiconductor layer 704. By this treatment, a lower layer of the gate insulating layer 706 having a thickness of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed. Further, nitrous oxide (N ₂ O) and silane (SiH ₄ ) are introduced, and a microwave (2.45 GHz) power of 3 kW to 5 kW is applied under a pressure of 10 Pa to 30 Pa and vapor phase growth is performed. A silicon oxynitride film is formed as an upper layer of the gate insulating layer 706. In this manner, by forming the gate insulating layer 706 by combining the solid phase reaction and the vapor deposition method, the gate insulating layer 706 having a low interface state density and an excellent withstand voltage can be formed. Note that in this case, the gate insulating layer 706 has a two-layer structure.

Alternatively, the gate insulating layer 706 may be formed by thermally oxidizing the semiconductor layer 702 and the semiconductor layer 704. When such thermal oxidation is used, it is preferable to use a base substrate having relatively high heat resistance.

Note that a gate insulating layer 706 containing hydrogen is formed, and then heat treatment is performed at a temperature of 350 ° C to 450 ° C, so that hydrogen contained in the gate insulating layer 706 is added into the semiconductor layer 702 and the semiconductor layer 704. You may make it diffuse. In this case, as the gate insulating layer 706, silicon nitride or silicon nitride oxide using a plasma CVD method can be used. The process temperature is preferably 350 ° C. or lower. In this manner, by supplying hydrogen to the semiconductor layer 702 and the semiconductor layer 704, the interface between the gate insulating layer 706 and the semiconductor layer 702 in the semiconductor layer 702, the interface between the gate insulating layer 706 and the semiconductor layer 704, and Defects at the interface can be effectively reduced.

Next, after a conductive layer is formed over the gate insulating layer 706, the conductive layer is processed (patterned) into a predetermined shape, so that an electrode 708 is formed over the semiconductor layer 702 and the semiconductor layer 704 (FIG. 5). (See (D)). A CVD method, a sputtering method, or the like can be used for forming the conductive layer. The conductive layer is formed using a material such as tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or niobium (Nb). can do. Alternatively, an alloy material containing the above metal as a main component or a compound containing the above metal may be used. Alternatively, a semiconductor material such as polycrystalline silicon doped with an impurity element imparting conductivity to a semiconductor may be used.

In this embodiment mode, the electrode 708 is formed using a single conductive layer; however, the semiconductor device of the present invention is not limited to this structure. The electrode 708 may be formed of a plurality of stacked conductive layers. In the case of a two-layer structure, for example, a molybdenum film, a titanium film, a titanium nitride film, or the like may be used as a lower layer, and an aluminum film or the like may be used as an upper layer. In the case of a three-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film, a stacked structure of a titanium film, an aluminum film, and a titanium film, or the like may be employed.

Note that a mask used for forming the electrode 708 may be formed using a material such as silicon oxide or silicon nitride oxide. In this case, a step of forming a mask by patterning a silicon oxide film, a silicon nitride oxide film, or the like is added. However, since the film thickness of the mask during etching is less than that of a resist material, a more accurate electrode 708 is formed. Can be formed. Alternatively, the electrode 708 may be selectively formed by a droplet discharge method without using a mask. Here, the droplet discharge method means a method of forming a predetermined pattern by discharging or ejecting a droplet containing a predetermined composition, and includes an ink jet method or the like in its category.

Further, using an ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to the coil-type electrode layer, a power amount applied to the electrode layer on the substrate side, and an electrode temperature on the substrate side) Etc.) is adjusted as appropriate, and the conductive layer is etched so as to have a desired tapered shape, whereby the electrode 708 can be formed. The taper shape can also be controlled by the shape of the mask. As an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen may be used as appropriate. it can.

Next, using the electrode 708 as a mask, an impurity element imparting one conductivity type is added to the semiconductor layers 702 and 704 (see FIG. 6A). In this embodiment, an impurity element imparting n-type conductivity (eg, phosphorus or arsenic) is added to the semiconductor layer 702, and an impurity element imparting p-type conductivity (eg, boron) is added to the semiconductor layer 704. Note that when the impurity element imparting n-type conductivity is added to the semiconductor layer 702, the semiconductor layer 704 to which the p-type impurity is added is covered with a mask or the like, and the addition of the impurity element imparting n-type is selectively performed. To be done. In addition, when an impurity element imparting p-type conductivity is added to the semiconductor layer 704, the semiconductor layer 702 to which an n-type impurity is added is covered with a mask or the like, and the impurity element imparting p-type conductivity is selectively added. To be done. Alternatively, after adding one of an impurity element imparting p-type conductivity or an impurity element imparting n-type to the semiconductor layer 702 and the semiconductor layer 704, an impurity imparting p-type at a higher concentration only to one semiconductor layer The other of the element or the impurity element imparting n-type conductivity may be added. By the addition of the impurities, an impurity region 710 is formed in the semiconductor layer 702 and an impurity region 712 is formed in the semiconductor layer 704.

Next, a sidewall 714 is formed on a side surface of the electrode 708 (see FIG. 6B). The sidewall 714 is formed by, for example, forming a new insulating layer so as to cover the gate insulating layer 706 and the electrode 708 and partially etching the insulating layer by anisotropic etching mainly in the vertical direction. can do. Note that the gate insulating layer 706 may be partially etched by the anisotropic etching described above. As the insulating layer for forming the sidewall 714, a film containing silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, an organic material, or the like is formed by a plasma CVD method, a sputtering method, or the like. A stacked structure may be used. In this embodiment, a silicon oxide film with a thickness of 100 nm is formed by a plasma CVD method. As the etching gas, a mixed gas of CHF ₃ and helium can be used. Note that the step of forming the sidewall 714 is not limited to these steps.

Next, an impurity element imparting one conductivity type is added to the semiconductor layers 702 and 704 using the gate insulating layer 706, the electrodes 708, and the sidewalls 714 as masks (see FIG. 6C). Note that an impurity element having the same conductivity type as the impurity element added in the previous step is added to the semiconductor layer 702 and the semiconductor layer 704 at a higher concentration. Note that when the impurity element imparting n-type conductivity is added to the semiconductor layer 702, the semiconductor layer 704 to which the p-type impurity is added is covered with a mask or the like, and the addition of the impurity element imparting n-type is selectively performed. To be done. In addition, when an impurity element imparting p-type conductivity is added to the semiconductor layer 704, the semiconductor layer 702 to which an n-type impurity is added is covered with a mask or the like, and the impurity element imparting p-type conductivity is selectively added. To be done.

By the addition of the impurity element, a pair of high-concentration impurity regions 716, a pair of low-concentration impurity regions 718, and a channel formation region 720 are formed in the semiconductor layer 702. In addition, by adding the impurity element, a pair of high-concentration impurity regions 722, a pair of low-concentration impurity regions 724, and a channel formation region 726 are formed in the semiconductor layer 704. The high concentration impurity region 716 and the high concentration impurity region 722 function as a source or a drain, and the low concentration impurity region 718 and the low concentration impurity region 724 function as an LDD (Lightly Doped Drain) region.

Note that the side wall 714 formed over the semiconductor layer 702 and the side wall 714 formed over the semiconductor layer 704 have the same length in the direction in which carriers move (a direction parallel to a so-called channel length). However, they may be formed differently. The length of the sidewall 714 over the semiconductor layer 704 serving as a p-channel transistor is preferably larger than the length of the sidewall 714 over the semiconductor layer 702 serving as an n-channel transistor. This is because boron implanted to form a source and a drain in a p-channel transistor easily diffuses and easily induces a short channel effect. In the p-channel transistor, by increasing the length of the sidewall 714, high-concentration boron can be added to the source and the drain, and the resistance of the source and the drain can be reduced.

In order to further reduce the resistance of the source and the drain, a silicide layer in which part of the semiconductor layer 702 and the semiconductor layer 704 is silicided may be formed. Silicidation is performed by bringing a metal into contact with the semiconductor layer and reacting silicon in the semiconductor layer with the metal by heat treatment (eg, GRTA method, LRTA method, etc.). As the silicide layer, cobalt silicide or nickel silicide may be used. When the semiconductor layer 702 or the semiconductor layer 704 is thin, the silicide reaction may be advanced to the bottom of the semiconductor layer 702 or the semiconductor layer 704. Metal materials that can be used for silicidation include titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Hf (hafnium), and tantalum (Ta). ), Vanadium (V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), and the like. The silicide layer can also be formed by laser light irradiation or the like.

Through the above steps, an n-channel transistor 728 and a p-channel transistor 730 are formed. Note that although a conductive layer functioning as a source electrode or a drain electrode is not formed in the stage illustrated in FIG. 6C, the conductive layer functioning as the source electrode or the drain electrode is sometimes referred to as a transistor. .

Next, an insulating layer 732 is formed so as to cover the n-channel transistor 728 and the p-channel transistor 730 (see FIG. 6D). Although the insulating layer 732 is not necessarily provided, the formation of the insulating layer 732 can prevent impurities such as an alkali metal and an alkaline earth metal from entering the n-channel transistor 728 and the p-channel transistor 730. Specifically, the insulating layer 732 is preferably formed using a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, or aluminum oxide. In this embodiment, a silicon nitride oxide film with a thickness of about 600 nm is used as the insulating layer 732. In this case, the above-described hydrogenation step may be performed after the silicon nitride oxide film is formed. Note that although the insulating layer 732 has a single-layer structure in this embodiment, it is needless to say that a stacked structure may be used. For example, in the case of a two-layer structure, a stacked structure of a silicon oxynitride film and a silicon nitride oxide film can be employed.

Next, an insulating layer 734 is formed over the insulating layer 732 so as to cover the n-channel transistor 728 and the p-channel transistor 730. The insulating layer 734 is preferably formed using a heat-resistant organic material such as polyimide, acrylic, polyimide, benzocyclobutene, polyamide, or epoxy. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass) Alumina or the like can also be used. Here, the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may have one selected from fluorine, an alkyl group, and an aromatic hydrocarbon in addition to hydrogen as a substituent. Note that the insulating layer 734 may be formed by stacking a plurality of insulating layers formed using these materials.

For the formation of the insulating layer 734, a CVD method, a sputtering method, an SOG method, spin coating, dipping, spray coating, a droplet discharge method (ink jet method, screen printing, offset printing, etc.), a doctor knife, A roll coater, curtain coater, knife coater, or the like can be used.

Next, contact holes are formed in the insulating layer 732 and the insulating layer 734 so that the semiconductor layer 702 and part of the semiconductor layer 704 are exposed. Then, a conductive layer 736 and a conductive layer 738 which are in contact with the semiconductor layer 702 and the semiconductor layer 704 through the contact holes are formed (see FIG. 7A). The conductive layer 736 and the conductive layer 738 function as a source electrode or a drain electrode of the transistor. In the present embodiment, a mixed gas of CHF ₃ and He is used as a gas used for etching when the contact hole is opened. However, the present invention is not limited to this.

The conductive layers 736 and 738 can be formed by a CVD method, a sputtering method, or the like. Specifically, as the conductive layer 736 and the conductive layer 738, aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or the like can be used. Alternatively, an alloy containing the above material as its main component or a compound containing the above material may be used. The conductive layer 736 and the conductive layer 738 may have a single-layer structure or a stacked structure.

As an example of an alloy containing aluminum as a main component, an alloy containing aluminum as a main component and containing nickel can be given. Further, examples include aluminum as a main component and one or both of nickel and carbon or silicon. Aluminum and aluminum silicon (Al—Si) have low resistance and are inexpensive, and thus are suitable as materials for forming the conductive layers 736 and 738. In particular, aluminum silicon is preferable because generation of hillocks due to resist baking during patterning can be suppressed. Further, instead of silicon, a material in which about 0.5% Cu is mixed in aluminum may be used.

When the conductive layer 736 and the conductive layer 738 have a stacked structure, for example, a stacked structure of a barrier film, an aluminum silicon film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon film, a titanium nitride film, and a barrier film is employed. Good. Note that a barrier film is a film formed using titanium, titanium nitride, molybdenum, molybdenum nitride, or the like. When the conductive layer is formed so that the aluminum silicon film is sandwiched between the barrier films, generation of hillocks of aluminum or aluminum silicon can be further prevented. In addition, when a barrier film is formed using titanium which is a highly reducing element, even if a thin oxide film is formed over the semiconductor layer 702 and the semiconductor layer 704, titanium contained in the barrier film forms the oxide film. By reduction, the contact between the conductive layer 736 and the semiconductor layer 702 and between the conductive layer 738 and the semiconductor layer 704 can be favorable. Alternatively, a plurality of barrier films may be stacked. In that case, for example, the conductive layer 736 and the conductive layer 738 can have a five-layer structure or a stacked structure of more layers such as titanium, titanium nitride, aluminum silicon, titanium, and titanium nitride from the lower layer.

Alternatively, tungsten silicide formed by a chemical vapor deposition method using WF ₆ gas and SiH ₄ gas may be used for the conductive layers 736 and 738. Alternatively, tungsten formed by hydrogen reduction of WF ₆ may be used for the conductive layer 736 and the conductive layer 738.

Note that the conductive layer 736 is connected to the high-concentration impurity region 716 of the n-channel transistor 728. The conductive layer 738 is connected to the high concentration impurity region 722 of the p-channel transistor 730.

FIG. 7B is a plan view of the n-channel transistor 728 and the p-channel transistor 730 illustrated in FIG. Here, a cross section taken along line AB in FIG. 7B corresponds to FIG. Note that in FIG. 7B, for simplicity, the conductive layer 736, the conductive layer 738, the insulating layer 732, the insulating layer 734, and the like are omitted.

Note that in this embodiment, the case where each of the n-channel transistor 728 and the p-channel transistor 730 includes one electrode 708 functioning as a gate electrode is described. It is not limited to. The transistor manufactured in this embodiment may have a multi-gate structure in which a plurality of electrodes functioning as gate electrodes are provided and the plurality of electrodes are electrically connected.

In this embodiment, instead of performing mechanical polishing treatment or the like, laser light is irradiated to reduce defects and surface unevenness of the single crystal semiconductor layer. Furthermore, by using the evaluation method of Embodiment 1, the laser light irradiation conditions are optimized by a very simple method. As a result, a semiconductor substrate with high flatness in which defects are sufficiently reduced can be provided, and the cost for providing the semiconductor substrate can be suppressed. Further, by using the semiconductor substrate, a transistor that can operate at high speed, has a low subthreshold value, has high field-effect mobility, and can be driven at a low voltage can be manufactured at low cost.

This embodiment can be combined with any of the other embodiments as appropriate.

(Embodiment 4)
A semiconductor device such as a transistor can be manufactured using the semiconductor substrate described in any of the above embodiments, and various electronic devices can be completed using the semiconductor device. Since the single crystal semiconductor layer provided in the semiconductor substrate described in Embodiment 2 has reduced crystal defects, it is possible to reduce the density of localized states at the interface with the gate insulating layer. By using this single crystal semiconductor layer as an active layer, a semiconductor element with reduced leakage current and improved electrical characteristics can be manufactured. In other words, by using the semiconductor substrate described in Embodiment 2, a semiconductor element with high current driving capability and high reliability can be manufactured. As a result, an electronic device as a final product can be manufactured with high throughput. It becomes possible to produce with good quality. In this embodiment, specific application examples to electronic devices are described with reference to drawings.

Electronic devices manufactured using semiconductor devices (particularly display devices) include video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (such as car audio components), computers, and game devices. , A portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image reproducing device (specifically, a digital versatile disc (DVD)) provided with a recording medium, and the image And the like).

FIG. 8A illustrates a television receiver or a personal computer monitor. A housing 1001, a support base 1002, a display portion 1003, a speaker portion 1004, a video input terminal 1005, and the like are included. The semiconductor device described in any of the above embodiments is used for the display portion 1003, and a highly reliable and high-performance television receiver or personal computer monitor can be provided at a low price.

FIG. 8B illustrates a digital camera. An image receiving unit 1013 is provided on the front portion of the main body 1011, and a shutter button 1016 is provided on the upper surface portion of the main body 1011. Further, a display portion 1012, operation keys 1014, and an external connection port 1015 are provided on the back surface portion of the main body 1011. The display portion 1012 uses the semiconductor device described in any of the above embodiments, so that a highly reliable digital camera with high performance can be provided at a low price.

FIG. 8C illustrates a laptop personal computer. A main body 1021 is provided with a keyboard 1024, an external connection port 1025, and a pointing device 1026. Further, a housing 1022 having a display portion 1023 is attached to the main body 1021. The semiconductor device described in any of the above embodiments is used for the display portion 1023, so that a highly reliable and high-performance notebook personal computer can be provided at a low price.

FIG. 8D illustrates a mobile computer, which includes a main body 1031, a display portion 1032, a switch 1033, operation keys 1034, an infrared port 1035, and the like. The display portion 1032 is provided with an active matrix display device. The semiconductor device described in any of the above embodiments is used for the display portion 1032, and a highly reliable and high-performance mobile computer can be provided at a low price.

FIG. 8E shows an image reproducing device. The main body 1041 is provided with a display portion B 1044, a recording medium reading portion 1045, and operation keys 1046. In addition, a housing 1042 including a speaker portion 1047 and a display portion A 1043 is attached to the main body 1041. Each of the display portion A 1043 and the display portion B 1044 uses the semiconductor device described in any of the above embodiments, so that a highly reliable and high-performance image reproducing device can be provided at a low price.

FIG. 8F illustrates an electronic book. The main body 1051 is provided with operation keys 1053. In addition, a plurality of display portions 1052 are attached to the main body 1051. The semiconductor device described in any of the above embodiments is used for the display portion 1052, so that a highly reliable electronic book with high performance can be provided at a low price.

FIG. 8G illustrates a video camera. A main body 1061 is provided with an external connection port 1064, a remote control receiving portion 1065, an image receiving portion 1066, a battery 1067, an audio input portion 1068, and operation keys 1069. A housing 1063 having a display portion 1062 is attached to the housing. The semiconductor device described in any of the above embodiments is used for the display portion 1062, so that a highly reliable video camera with high performance can be provided at a low price.

FIG. 8H illustrates a mobile phone, which includes a main body 1071, a housing 1072, a display portion 1073, an audio input portion 1074, an audio output portion 1075, operation keys 1076, an external connection port 1077, an antenna 1078, and the like. The semiconductor device described in any of the above embodiments is used for the display portion 1073, so that a highly reliable mobile phone with high performance can be provided at a low price.

FIG. 9 illustrates an example of a configuration of a portable electronic device 1100 that has both a telephone function and an information terminal function. Here, FIG. 9A is a front view, FIG. 9B is a rear view, and FIG. 9C is a development view. The portable electronic device 1100 is an electronic device called a smartphone that has both functions of a telephone and an information terminal and can perform various data processing in addition to voice calls.

A portable electronic device 1100 includes a housing 1101 and a housing 1102. A housing 1101 includes a display portion 1111, a speaker 1112, a microphone 1113, operation keys 1114, a pointing device 1115, a camera lens 1116, an external connection terminal 1117, and the like. The housing 1102 includes a keyboard 1121, an external memory slot 1122, a camera Lens 1123, light 1124, earphone terminal 1125, and the like. An antenna is incorporated in the housing 1101. In addition to the above structure, a non-contact IC chip, a small recording device, or the like may be incorporated.

The semiconductor device described in any of the above embodiments is incorporated in the display portion 1111. Note that the video (and the display direction) displayed on the display unit 1111 varies depending on the usage form of the mobile electronic device 1100. In addition, since the camera lens 1116 is provided on the same surface as the display portion 1111, a voice call with video (so-called videophone) is possible. Note that the speaker 1112 and the microphone 1113 can be used for recording, reproduction, and the like without being limited to voice calls. When a still image and a moving image are taken using the camera lens 1123 (and the light 1124), the display unit 1111 is used as a viewfinder. The operation keys 1114 are used for making and receiving calls, inputting simple information such as e-mail, scrolling the screen, moving the cursor, and the like.

The housing 1101 and the housing 1102 (FIG. 9A) which are overlapped with each other slide and can be developed as illustrated in FIG. 9C, so that they can be used as information terminals. In this case, smooth operation using the keyboard 1121 and the pointing device 1115 is possible. The external connection terminal 1117 can be connected to various cables such as an AC adapter and a USB cable, and enables charging and data communication with a computer or the like. In addition, a recording medium can be inserted into the external memory slot 1122 to support storage and movement of a larger amount of data. In addition to the above functions, a wireless communication function using an electromagnetic wave such as infrared rays, a television reception function, or the like may be provided. By mounting the semiconductor device described in any of the above embodiments, a highly reliable portable electronic device with high performance can be provided at a low price.

As described above, the application range of this embodiment is extremely wide and can be used for electronic devices in various fields. Note that this embodiment can be combined with any of the other embodiments as appropriate.

In this example, the crystallinity of a single crystal semiconductor layer irradiated with laser light under conditions A to C having the concentration distribution shown in FIG. 2 was evaluated using an EBSP (Electron Backscatter Diffraction Pattern) method. Show.

In this example, the single crystal semiconductor layer was oxidized on a non-alkali glass substrate (trade name: AN100) having a thickness of 0.7 mm, similarly to the single crystal semiconductor layer 112 described with reference to FIG. In this structure, a silicon film, a silicon nitride oxide film, and a silicon oxynitride film are provided through insulating films each having a thickness of 50 nm. The thickness of the single crystal semiconductor layer is 100 nm.

As a single crystal semiconductor substrate for manufacturing the single crystal semiconductor layer, a single crystal silicon wafer is used. The single crystal silicon wafer is a 5-inch square substrate. Its conductivity type is P type, and its resistivity is about 10 Ω · cm. The crystal orientation is (100) on the main surface and <110> on the side surface.

The silicon oxynitride film, the silicon nitride oxide film, and the silicon oxide film were formed using a PECVD method. The process gas of the silicon oxynitride film is SiH ₄ and N ₂ O, and the flow rate ratio is SiH ₄ \ N ₂ O = ₄ \ 800. The substrate temperature in the film forming process is 400 ° C. The process gas of the silicon nitride oxide film is SiH ₄ , NH ₃ , N ₂ O, and H ₂ , and the flow rate ratio is SiH ₄ \ NH ₃ \ N ₂ O \ H ₂ = 10 \ 100 \ ₂₀ \ 400. . The temperature of the film forming process is 350 ° C. As a process gas for forming the silicon oxide film, TEOS and O ₂ are used, and the flow ratio thereof is TEOS \ O ₂ = 15 \ 750. The temperature of the film forming process is 300 ° C.

In order to form an embrittlement layer in a single crystal silicon wafer, hydrogen ions are added to the single crystal silicon wafer using an ion doping apparatus. 100% hydrogen gas is used as a source gas, and ions in plasma generated by exciting the hydrogen gas are accelerated by an electric field and irradiated to a single crystal silicon wafer substrate without mass separation. Formed. In the ion doping apparatus, by exciting the hydrogen gas, three types of ion species H ⁺ , H ₂ ⁺ , and H ₃ ⁺ are generated, and all the ion species are accelerated and irradiated to the single crystal silicon wafer. Of the hydrogen ion species generated from hydrogen gas, about 80% is H ₃ ⁺ .

In this example, the hydrogen ion doping conditions were a power output of 100 W, an acceleration voltage of 40 kV, and a dose of 2.2 × 10 ¹⁶ ions / cm ³ .

The glass substrate and the single crystal silicon wafer on which the insulating layer was formed were ultrasonically cleaned in pure water, and then cleaned with pure water containing ozone. Next, the silicon oxide film formed on the surface of the glass substrate and the surface of the single crystal silicon wafer was adhered and bonded. Next, in order to cause cleavage in the embrittlement layer, heat treatment is performed at 200 ° C. for 2 hours in a heating furnace to improve the bonding strength between the glass substrate and the silicon oxide film, and subsequently, 600 ° C. in the heating furnace, By heating for 4 hours, the single crystal silicon wafer is cleaved, and the single crystal silicon layer is separated from the single crystal silicon wafer.

Next, the single crystal silicon layer was treated with a hydrofluoric acid solution diluted to 1/100 to remove the natural oxide film formed on the surface. Next, the single crystal silicon layer was irradiated with laser light, melted, and recrystallized. A XeCl excimer laser that oscillates a beam with a wavelength of 308 nm was used as the laser oscillator. The pulse width of the laser beam is 25 nsec, and the repetition frequency is 30 Hz. As described above, the laser light irradiation treatment was performed on the three regions of the single crystal semiconductor layer 112 under three conditions (conditions A to C) in which the energy density of the laser light was different from each other. Conditions A to C are as follows.
Condition A. 568 mJ / cm ²
Condition B. 584 mJ / cm ²
Condition C.I. 600 mJ / cm ²

FIG. 10 shows the results of measuring the crystallinity of the single crystal semiconductor layer 112 after irradiation with the laser light 113 by the EBSP method. In this measurement, the measurement range is 40 μm × 40 μm. 10A shows the distribution of crystal orientation of the single crystal semiconductor layer 112 in the region irradiated with the laser beam 113 under the condition A. FIG. 10B shows the distribution under the condition B and FIG. (C) shows the crystal orientation distribution of the single crystal semiconductor layer 112 in the region irradiated with the laser beam 113 under the condition C. FIG. 10A to 10C illustrate distributions in the direction perpendicular to the single crystal semiconductor layer 112. FIG. FIG. 10D shows the plane orientation in FIGS. 10A to 10C.

From FIG. 10, it is considered that the crystal orientation of the single crystal semiconductor layer 112 in the region irradiated with the laser light 113 under the conditions A and B is substantially a single direction and is a single crystal. As described above, the conditions A and B are the conditions in which the concentration of elements in the depth direction of the single crystal semiconductor layer after recrystallization has a maximum carbon concentration, that is, the single crystal semiconductor layer is in a partially molten state. It is a condition. On the other hand, it can be seen that the single crystal semiconductor layer 112 in the region irradiated with the laser light 113 under the condition C has a large number of crystal defects and a part of the crystallized region exists. This can be judged to be because, when irradiated under the condition C, disordered nucleation occurred after the single crystal semiconductor layer was completely melted and became a liquid phase.

From the concentration distribution of the element shown in FIG. 2 and the concentration distribution of the element in the depth direction of the single crystal semiconductor layer after recrystallization from FIG. 10, when the carbon concentration has a maximum, the crystallinity of the single crystal semiconductor layer Was shown to be good.

In this embodiment, lifetime measurement is used for crystallinity of a single crystal semiconductor layer subjected to laser light irradiation treatment under four conditions (conditions A ′, A, B, and C ′) in which the energy density of laser light is different. Results of evaluation and characteristics of a TFT manufactured using the single crystal semiconductor layer are shown.

In this embodiment, the laser light irradiation conditions are as follows.
Condition A ′. 547 mJ / cm ²
Condition A. 568 mJ / cm ²
Condition B. 584 mJ / cm ²
Condition C ′. 608 mJ / cm ²

Note that in this example, the structure and manufacturing method of the single crystal semiconductor layer other than the laser light irradiation conditions are the same as those described in Example 1, and thus the description thereof is omitted. In this example, the concentration distribution in the depth direction of the single crystal semiconductor layer after recrystallization under conditions A and B is the same as the result shown in FIG. Although the concentration distributions for conditions A ′ and C ′ are not shown, it is estimated from the results shown in FIG. 2 that condition A ′ is a narrowly-defined partially molten state in which the solid-liquid interface is located on the surface side than condition A. can do. Further, the condition C ′ can be approximated to the condition C in FIG. 2, and it can be assumed that it is in a completely molten state.

FIG. 11 is a graph of lifetime evaluation results of the single crystal semiconductor layer after irradiation with laser light. In this example, a lifetime evaluation apparatus using a microwave photoconductive decay method manufactured by Kobelco Research Institute, Ltd. was used as the measurement apparatus.

Microwave photoconductive decay method (hereinafter referred to as μ-PCD method) is a method of irradiating a semiconductor surface with laser light, generating carriers in the semiconductor, and irradiating the position where the laser light is irradiated with microwaves. In this method, the lifetime is evaluated by detecting the attenuation state of the intensity of the microwave reflected by the semiconductor. In the μ-PCD method, when carriers are generated in the semiconductor, the resistance value of the semiconductor decreases, and therefore, the microwave reflectance in the region where the carriers are generated increases. By detecting this, the lifetime is evaluated.

When single crystal silicon is irradiated with light, electrons generated in the valence band and holes generated in the conduction band recombine and disappear. If the single crystal silicon layer has many contaminations and defects, the density of the charge trap centers increases, and the probability of carrier recombination in the single crystal silicon increases, so the lifetime is shortened. For this reason, the lifetime is used as a parameter for evaluating whether or not the crystal structure of a semiconductor such as single crystal silicon is complete.

The vertical axis of the graph of FIG. 11 represents the peak value of the detection signal of the reflected microwave, and the longer the peak value, the longer the lifetime. It can be seen that the condition C ′ in which the single crystal semiconductor layer is in a completely molten state during laser irradiation has a significantly shorter lifetime than conditions A ′, A and B in which the single crystal semiconductor layer is in a partially molten state. In addition, when comparing Condition A ′, Condition A, and Condition B, the lifetime may be longer as the single crystal semiconductor layer is partially melted during laser light irradiation and the solid-liquid interface approaches the lower insulating layer. I understand.

12A and 12B show an n-channel TFT manufactured using a single crystal semiconductor layer recrystallized by irradiating with laser light under conditions A ′, A, B, and C ′. 8 is a probability statistical distribution diagram of the S value (FIG. 12A), and a probability statistical distribution diagram of the S value of the p-channel TFT (FIG. 12B). Alternatively, the ratio between the channel length (L) and the channel width (W) of the p-channel TFT is L / W = 10/8 μm.

In the probability statistical distribution diagram, the horizontal axis indicates the S value (V / dec.), And the vertical axis indicates the cumulative frequency. Also, in the probability statistical distribution diagram, the smaller the S value variation between TFTs, the larger the slope of the graph.

12 (A) and 12 (B), the x mark indicates the measurement result when irradiated under the condition A ′, the black triangle mark indicates the measurement result when irradiated under the condition A, and the white circle mark indicates the condition. The measurement results when irradiated with B and the white squares indicate the measurement results when irradiated under condition C ′. In both the n-channel TFT shown in FIG. 12A and the p-channel TFT shown in FIG. 12B, the single crystal semiconductor layers in condition A ′, condition A, and condition B are more completely melted. Compared to the graph of the estimated condition C ′, it can be seen that the variation is small and the S value characteristic is also good.

Under conditions A ′, A, and B where the single crystal semiconductor layer is in a partially molten state when irradiated with laser light, the energy density of the laser light increases, in other words, the single crystal after recrystallization. In the concentration distribution in the depth direction of the semiconductor layer, the S value decreases as the position of the maximum carbon concentration approaches the interface with several insulating layers, and the characteristics of the TFT are improved. This can be determined because the closer the solid-liquid interface is to the interface with the lower insulating layer in the partially molten state, the more the defects can be repaired in the entire film thickness direction and the crystallinity of the single crystal semiconductor layer can be recovered.

When the carbon concentration has a maximum in the concentration distribution of the element shown in FIG. 2 and the concentration distribution of the element in the depth direction of the single crystal semiconductor layer after recrystallization from FIGS. 11 and 12, the single crystal semiconductor layer It was shown that the crystallinity of the TFT and the characteristics of a TFT manufactured using the single crystal semiconductor layer are good. It was also shown that the closer the position of the maximum is to the interface with the lower insulating layer, the better the crystallinity of the single crystal semiconductor layer and the characteristics of the TFT manufactured using the single crystal semiconductor layer.

100 single crystal semiconductor substrate 102 embrittlement layer 110 base substrate 111 insulating layer 112 single crystal semiconductor layer 113 laser beam 118 single crystal semiconductor substrate 120 single crystal semiconductor layer

Claims (4)

The single crystal semiconductor substrate is separated from the embrittlement layer formed in a region of a predetermined depth from the surface of the single crystal semiconductor substrate, fixed on the base substrate through the insulating layer, and then re-single-crystallized by laser irradiation. For the crystalline semiconductor layer,
Measure the carbon concentration distribution in the depth direction of the single crystal semiconductor layer,
A method for evaluating crystallinity of a single crystal semiconductor layer, wherein the crystallinity of the single crystal semiconductor layer is determined to be excellent when the carbon concentration has a maximum. The single crystal semiconductor substrate is separated from the embrittlement layer formed in a region of a predetermined depth from the surface of the single crystal semiconductor substrate, fixed on the base substrate through the insulating layer, and then re-single-crystallized by laser irradiation. For the crystalline semiconductor layer,
Measure the carbon concentration and hydrogen concentration distribution in the depth direction of the single crystal semiconductor layer,
When the carbon concentration has a maximum and the hydrogen concentration does not have a shoulder peak corresponding to the maximum of the carbon concentration, it is determined that the single crystal semiconductor layer has excellent crystallinity. A method for evaluating crystallinity of a crystalline semiconductor layer. The single crystal semiconductor substrate is separated from the embrittlement layer formed in a region of a predetermined depth from the surface of the single crystal semiconductor substrate, fixed on the base substrate through the insulating layer, and then re-single-crystallized by laser irradiation. For the crystalline semiconductor layer,
Measure the carbon concentration distribution in the depth direction of the single crystal semiconductor layer,
When the carbon concentration has a maximum in a region within 20 nm from the interface with the insulating layer in the single crystal semiconductor layer, it is determined that the crystallinity of the single crystal semiconductor layer is excellent. A method for evaluating crystallinity of a single crystal semiconductor layer.   The laser light irradiation condition is determined using the single crystal semiconductor layer crystallinity evaluation method according to any one of claims 1 to 3, and the laser light is irradiated using the determined irradiation condition. A method for manufacturing a semiconductor substrate.