JP2009260028A - Semiconductor integrated circuit, node potential measurement system, and node potential measurement method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, a node potential voltage measurement system, and node potential voltage measurement method, capable of reducing measurement error, and detecting node potential voltage with high reliability and with no increase of cost. <P>SOLUTION: One transistor 221 for measurement is mounted inside a semiconductor integrated circuit 2. Selection is made using a selector 222 so that an external power source (supply terminal TVref of reference voltage Vref) is directly connected to a gate input of the measurement transistor 221, with a voltage/current characteristics stored in a storage device. Then, selection is so made that an internal node is connected to a gate of the measurement transistor 221, for measuring a current flowing the measurement transistor 221. An internal node potential voltage is derived from the current and the voltage/current characteristics. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit capable of measuring a node potential in a circuit, a node potential measurement system, and a node potential measurement method.

  In general, an analytical technique (probe contact method) in which a probe (needle) is applied is used to detect a potential of an important internal node for evaluation of a semiconductor integrated circuit (eg, LSI). .

  Patent Document 1 discloses a semiconductor integrated circuit device that detects an arbitrary node potential inside a semiconductor integrated circuit without using a probe contact method.

The semiconductor integrated circuit device includes a first current section for passing a current having a magnitude corresponding to the voltage of an arbitrary node inside the semiconductor integrated circuit, and a second current having the same voltage / current characteristics as the first current section. Current section.
The semiconductor integrated circuit device assumes that the input voltage of the second current part when the same current as the current flowing through the first current part flows to the second current part corresponds to the voltage of the arbitrary node. Detect node voltage.
The first current part and the second current part are configured by separate transistors, that is, a measurement transistor and a characteristic acquisition transistor.
Japanese Patent Laid-Open No. 7-263507

By the way, in the probe contact method described above, the cost is high, and the measurement environment (limited to temperature and assembly chip) and the number of measurement samples (convenience of measurement time) are limited. It is only suitable for analysis and not suitable for acquisition of mass data.
In addition, it is conceivable that the circuit characteristics are changed by applying the probe, and there is a possibility that a correct value in the original operation state cannot be measured.
Furthermore, although it is conceivable that the internal node to be measured is directly output as a pin to the outside of the LSI, it is not preferable from the viewpoint of extra capacity added to the node and reliability.

In addition, in the semiconductor integrated circuit device of Patent Document 1, since the measurement transistor and the characteristic acquisition transistor are separate, the voltage-current characteristics of both transistors do not exactly match due to manufacturing variations or the like. Remain.
Furthermore, if a depletion type is used to expand the voltage measurement range, the number of manufacturing steps increases, resulting in an increase in cost.

  The present invention provides a semiconductor integrated circuit, a node potential measurement system, and a node potential measurement method capable of reducing a measurement error without causing an increase in cost and capable of performing highly reliable node potential detection. There is to do.

  A semiconductor integrated circuit according to a first aspect of the present invention includes at least one internal node for potential measurement, a power supply voltage terminal connectable to the outside, a reference potential terminal connectable to the outside, and a reference voltage supplied from the outside. A reference voltage supply terminal, one measurement transistor for measuring the potential of the internal node, and a selector connected to the control terminal of the measurement transistor, the selector according to a select signal The control transistor has a control terminal selectively connected to the reference voltage supply terminal or the internal node. The measurement transistor has a first terminal connected to the power supply voltage terminal and a second terminal connected to the reference potential terminal. Current flowing when the reference voltage is supplied to the control terminal and when the internal node potential is applied And it can be measured through the reference potential terminal.

  Preferably, the measurement transistor is configured such that when the control terminal is connected to the reference voltage supply terminal by the selector, an external reference voltage that changes within a predetermined range is applied to the control terminal. Voltage-current characteristics are acquired, and when the control terminal is connected to the internal node by the selector, a current is measured when the internal node potential is applied to the control terminal, and the acquired voltage-current characteristics and The internal node potential is derived from the measurement current.

  Preferably, the measurement transistor is formed of a p-channel insulated gate field effect transistor having a threshold voltage higher than that of the thin film transistor.

  Preferably, the measurement transistor is a p-channel insulated gate field effect transistor.

  Preferably, the measurement transistor is an n-channel insulated gate field effect transistor.

  A node potential measurement system according to a second aspect of the present invention includes a semiconductor integrated circuit and a measurement device capable of measuring the node potential of the semiconductor integrated circuit, and the semiconductor integrated circuit includes at least one potential measurement target. One internal node, a power supply voltage terminal connectable to the outside, a reference potential terminal connectable to the outside, a reference voltage supply terminal to which a reference voltage is supplied from the outside, and 1 for measuring the potential of the internal node Two measuring transistors and a selector connected to the control terminal of the measuring transistor, wherein the selector selectively selects the control terminal of the measuring transistor as the reference voltage supply terminal or the internal node according to a select signal. The measurement transistor has a first terminal connected to the power supply voltage terminal, a second terminal connected to the reference potential terminal, and the control transistor. A current flowing when a reference voltage is supplied to the child and when the internal node potential is applied can be measured through the power supply voltage terminal and the reference potential terminal, and the measuring apparatus includes the semiconductor integrated circuit In this case, at least when the control terminal of the measurement transistor is connected to the reference voltage supply terminal by the selector, the reference voltage is supplied to the reference voltage supply terminal while being changed within a predetermined range. When the current flowing through the power supply voltage terminal and the reference potential terminal are measured to obtain voltage-current characteristics, and the control terminal of the measurement transistor is connected to the internal node by the selector in the semiconductor integrated circuit. The current flowing through the measuring transistor is It was measured through fine the reference potential terminal, to derive the internal node potential and a voltage-current characteristic and the measured current in the acquired.

  Preferably, the storage device stores the acquired voltage-current characteristic information, and the measuring device holds the acquired voltage-current characteristic information in the holding unit and is held in the holding unit. The internal node potential is derived from the voltage-current characteristics and the measured current.

  A node potential measurement method according to a third aspect of the present invention includes a semiconductor integrated circuit including at least one internal node that is a potential measurement target, a power supply voltage terminal that can be connected to the outside, a reference potential terminal that can be connected to the outside, A reference voltage supply terminal to which a reference voltage is supplied from the outside, one measurement transistor for measuring the potential of the internal node, and the control terminal of the measurement transistor according to a select signal as the reference voltage supply terminal or the above-mentioned In the semiconductor integrated circuit, the control terminal of the measurement transistor is connected to the reference voltage supply terminal, and the reference voltage is applied to the reference voltage supply terminal with a predetermined range. The current flowing through the measurement transistor is measured through the power supply voltage terminal and the reference potential terminal to Obtaining current characteristics, connecting the control terminal of the measurement transistor to the internal node in the semiconductor integrated circuit, measuring a current flowing through the measurement transistor through the power supply voltage terminal and the reference potential terminal, and obtaining the current characteristic. The internal node potential is derived from the voltage-current characteristics and the measured current.

According to the present invention, with the control transistor connected to the reference voltage supply terminal by the selector, an external reference voltage that changes within a predetermined range is applied to the control terminal, and the voltage-current characteristics at this time Is acquired.
Next, the current is measured when the internal node potential is applied to the control terminal while the control terminal of the measurement transistor is connected to the internal node by the selector.
The internal node potential is derived from the acquired voltage-current characteristics and the measured current.

  According to the present invention, a measurement error can be reduced without causing an increase in cost, and a highly reliable node potential can be detected.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing a configuration example of a node potential measurement system for a semiconductor integrated circuit according to an embodiment of the present invention.

The node potential measurement system 1 includes a semiconductor integrated circuit 2, a tester 3, and a personal computer (PC) 4.
The tester 3 and the PC 4 constitute a measuring device.

  The semiconductor integrated circuit 2 includes a potential measurement target internal node 21, a measurement circuit 22, a power supply voltage terminal TVDD, a reference potential (for example, ground potential GND) terminal TVSS, and a reference voltage supply terminal TVref.

  The measurement circuit 22 of the semiconductor integrated circuit 2 is connected to one insulated gate field effect transistor (hereinafter referred to as measurement transistor) 221 for measuring the potential Vnode of the internal node 21 and the gate (control terminal) of this measurement transistor. Selector 222.

  The measurement transistor 221 has a source (for example, a first terminal) and a drain (for example, a second terminal) connected to the power supply voltage terminals TVDD and TVSS, respectively.

  The selector 222 selectively connects the gate of the measuring transistor 221 to the external reference voltage Vref supply terminal TVref or the internal node 21 in accordance with the select signal SEL and its inverted signal / SEL (/ indicates inversion).

In the present embodiment, basically, first, the voltage-current characteristics of the measurement transistor 221 are acquired in a state where the gate of the measurement transistor 221 is connected to the supply terminal TVref of the reference voltage Vref from the outside by the selector 222.
Since the acquired voltage-current characteristic may be stored in the internal memory, the tester 3, or the external PC 4, it is stored as a database in the storage device.
Next, the selector 222 obtains the measurement current and the voltage to be measured from the database in a state where the gate of the measurement transistor 221 is connected to the node 21 to be measured.
As described above, in the present embodiment, it is not necessary to compare the reference potential with the reference potential every time when measuring the potential. Therefore, the temporal change of the potential can be calculated in real time by one measurement.

  In the node voltage measurement system 1 of FIG. 1, the voltage / current characteristic of the measurement transistor 221 is measured by the tester 3 through the measurement circuit 22 mounted on the semiconductor integrated circuit 2. An example is shown in which the obtained voltage-current characteristics of the measurement transistor 221 are stored in the storage device 41 as a holding unit in the PC 4 connected to the tester 3.

The tester 3 supplies, for example, the power supply voltage VDD to the power supply voltage terminal TVDD of the semiconductor integrated circuit 2 under the control of the PC 4, applies the reference potential VSS to the reference potential terminal TVSS, and the semiconductor integrated circuit 2 from 0 V to the reference voltage terminal TVref. It has a function of supplying the reference voltage Vref by changing to the power supply voltage of.
The tester 3 includes a current measurement unit (A) 31 connected to the supply line of the power supply voltage VDD, and measures a current value flowing through the measurement transistor 221 in the measurement circuit 22 of the semiconductor integrated circuit 2.

  FIG. 2 is a circuit diagram showing a configuration example of the measurement circuit 22 according to the present embodiment.

The measurement transistor 221 in FIG. 2 is formed of a thick p-channel MOS (PMOS) transistor PT21.
Here, the thick-film PMOS transistor PT21 means a high threshold transistor, in other words, a high breakdown voltage transistor, and has a high operating voltage of 3.3 V with respect to a thin film transistor having an operating voltage of about 1.0 V. It is formed by the transistor applied to.
In this way, by using a thick PMOS transistor PT21 (for example, 3.3V operation) as the measurement transistor 221, it is possible to use a potential near VDD or a potential near GND for a circuit including a thin film transistor (for example, 1.0V operation). It can be measured with two measuring transistors.

The gate of the PMOS transistor PT21 is connected to the selector 222 as described above.
The source of the PMOS transistor PT21 is connected to the power supply voltage terminal TVDD and supplied with the power supply voltage VDD.
The drain of the PMOS transistor PT21 is connected to the reference potential terminal TVSS and is connected to the reference potential VSS.

  The selector 222 in FIG. 2 is formed by transmission gates TMG21 and TMG22.

The transmission gate TMG21 has two input / output terminals formed by connecting the sources and drains of the PMOS transistor PT22 and the n-channel MOS (NMOS) transistor NT21.
In the transmission gate TMG21, one input / output terminal is connected to the reference voltage supply terminal TVref, and the other input / output terminal is connected to the gate of the PMOS transistor PT21 which is the measurement transistor 221.

The transmission gate TMG22 has two input / output terminals formed by connecting the sources and drains of the PMOS transistor PT23 and the NMOS transistor NT22.
In the transmission gate TMG 22, one input / output terminal is connected to the internal node 21, and the other input / output terminal is connected to the gate of the PMOS transistor PT 21 that is the measurement transistor 221.

The gate of the PMOS transistor PT22 of the transmission gate TMG21 and the gate of the NMOS transistor NT22 of the transmission gate TMG22 are connected to the supply line of the select signal SEL.
The gate of the NMOS transistor NT21 of the transmission gate TMG21 and the gate of the PMOS transistor PT23 of the transmission gate TMG22 are connected to a supply line of an inverted signal / SEL (/ indicates logic inversion) obtained by logically inverting the select signal SEL.

  The select signal SEL and its inverted signal / SEL may be generated within the semiconductor integrated circuit 2 or may be directly supplied from the tester 3 side.

  Next, the operation when the measurement circuit of FIG. 2 is used will be described.

First, the select signal SEL and its inverted signal / SEL signal are set so that the supply terminal TVref of the reference voltage Vref is connected to the gate of the measurement transistor 221.
In the case of the selector 222 in FIG. 2, the select signal SEL is set to a low level (LO), and the inverted signal / SEL is set to a high level (HI). Thereby, PMOS transistor PT22 and NMOS transistor NT21 of transmission gate TMG21 are turned on, and PMOS transistor PT23 and NMOS transistor NT22 of transmission gate TMG22 are turned off.
That is, the transmission gate TMG21 is turned on, and the reference voltage Vref supplied by the tester 3 is applied to the gate of the PMOS transistor PT21 forming the measurement transistor 221.

Next, the tester 3 measures the current value I flowing through the PMOS transistor PT21 as the measurement transistor 221 while changing the reference voltage Vref from 0 V to the power supply voltage of the semiconductor integrated circuit.
The reference voltage Vref and the current value I at this time are stored in the storage device 41 of the PC 4 as voltage-current value characteristics, for example.
Usually, the threshold voltage of a thick film (high threshold voltage) PMOS transistor (for example, 3.3 V operation) is higher than the power supply voltage VDD of a circuit formed of a thin film transistor (for example, 1.0 V operation). Even if Vref is changed in the full range, the measuring transistor 221 is not turned off, and the voltage-current characteristic thereof is almost linear as shown in FIG.
Due to this linear characteristic, it is possible to obtain a desired potential with a certain degree of accuracy without depending on the voltage Vnode of the internal node 21.

Next, the select signal SEL and its inverted signal / SEL signal are set so that the internal node 21 is connected to the gate of the measurement transistor 221.
In the case of the selector 222 in FIG. 2, the select signal SEL is set to the high level (HI), and the inverted signal / SEL is set to the low level (LO). Thereby, PMOS transistor PT22 and NMOS transistor NT21 of transmission gate TMG21 are turned off, and PMOS transistor PT23 and NMOS transistor NT22 of transmission gate TMG22 are turned on.
That is, the transmission gate TMG22 is turned on, and the potential Vnode of the internal node 21 is applied to the gate of the PMOS transistor PT21 that forms the measurement transistor 221.

Here, in the tester 3, the current value I flowing through the PMOS transistor PT21 is measured in a state where the potential Vnode of the internal node 21 is applied to the gate of the PMOS transistor PT21 forming the measurement transistor 221.
Then, the potential Vnode of the internal node 21 is derived from the measured value and the voltage-current characteristic acquired in advance using the PC 4 or the like.

In the above description, the storage device 41 of the PC 4 is used to store the voltage / current characteristics. However, the storage device of the voltage / current characteristics is not limited to the PC 4 and may be in the tester or the semiconductor integrated circuit 2. An internal memory or the like may be used.
As long as it can be stored in a storage device as a database, the location of the storage device is not limited.

In addition, the measurement circuit including the measurement transistor and the selector is not limited to the circuit shown in FIG. 2, and various modes are possible.
FIG. 4 is a circuit diagram showing a second configuration example of the measurement circuit according to the present embodiment.
FIG. 5 is a circuit diagram showing a third configuration example of the measurement circuit according to the present embodiment.
FIG. 6 is a circuit diagram showing a fourth configuration example of the measurement circuit according to the present embodiment.

  When the expected measurement potential is a potential close to the reference potential VSS, for example, a measurement circuit as shown in FIG. 4 can be applied.

The measurement transistor 221A shown in FIG. 4 is formed of a thin film PMOS transistor PT24 applicable when the operating voltage is 1.0V.
The selector 222A is formed by an NMOS transistor NT23 and an NMOS transistor NT24.
The inverted signal / SEL of the select signal SEL is supplied to the gate of the NMOS transistor NT23, and the select signal SEL is supplied to the gate of the NMOS transistor NT24.

Also in this case, first, the select signal SEL and its inverted signal / SEL signal are set such that the supply terminal TVref of the reference voltage Vref is connected to the gate of the measurement transistor 221A.
In the case of the selector 222A in FIG. 4, the select signal SEL is set to a low level (LO), and the inverted signal / SEL is set to a high level (HI). As a result, the NMOS transistor NT23 is turned on and the NMOS transistor NT24 is turned off.
That is, the NMOS transistor NT23 is turned on, and the reference voltage Vref supplied by the tester 3 is applied to the gate of the PMOS transistor PT24 that forms the measurement transistor 221A.

Next, the tester 3 measures the current value I flowing through the PMOS transistor PT24, which is the measurement transistor 221A, while changing the reference voltage Vref from 0 V to the power supply voltage of the semiconductor integrated circuit.
The reference voltage Vref and the current value I at this time are stored in the storage device 41 of the PC 4 as voltage-current value characteristics, for example.

Next, the select signal SEL and its inverted signal / SEL signal are set so that the internal node 21 is connected to the gate of the measurement transistor 221A.
In the case of the selector 222A in FIG. 4, the select signal SEL is set to a high level (HI) and the inverted signal / SEL is set to a low level (LO). As a result, the NMOS transistor NT23 is turned off and the NMOS transistor NT24 is turned on.
That is, the NMOS transistor NT24 is turned on, and the potential Vnode of the internal node 21 is applied to the gate of the PMOS transistor PT24 that forms the measurement transistor 221A.

Here, in the tester 3, the current value I flowing through the PMOS transistor PT24 is measured in a state where the potential Vnode of the internal node 21 is applied to the gate of the PMOS transistor PT24 forming the measurement transistor 221A.
Then, the potential Vnode of the internal node 21 is derived from the measured value and the voltage-current characteristic acquired in advance using the PC 4 or the like.

  According to the measurement circuit of FIG. 4, the selector can be made small. However, since it is difficult to measure a potential close to VDD, the measurement circuit in FIG. 4 is applied when the expected measurement potential is close to the reference potential VSS.

  Since the selector 222A is formed of an NMOS transistor, the transfer voltage may drop by the threshold voltage. In that case, the level when the select signal SEL and the inverted signal / SEL are at the high level can be set to a level obtained by adding a higher voltage α to the power supply voltage value having the highest supply voltage, for example.

  Further, when the expected measurement potential is a potential close to the power supply voltage VDD, a measurement circuit as shown in FIG. 5 can be applied.

The measurement transistor 221B of FIG. 5 is formed by a thin film NMOS transistor NT25.
The selector 222B is formed by a PMOS transistor PT25 and a PMOS transistor PT26.
The select signal SEL is supplied to the gate of the PMOS transistor PT25, and the inverted signal / SEL of the select signal SEL is supplied to the gate of the PMOS transistor PT26.

Also in this case, first, the select signal SEL and its inverted signal / SEL signal are set so that the supply terminal TVref of the reference voltage Vref is connected to the gate of the measurement transistor 221B.
In the case of the selector 222B in FIG. 5, the select signal SEL is set to a low level (LO), and the inverted signal / SEL is set to a high level (HI). As a result, the PMOS transistor PT25 is turned on and the PMOS transistor PT26 is turned off.
That is, the PMOS transistor PT25 is turned on, and the reference voltage Vref supplied by the tester 3 is applied to the gate of the NMOS transistor NT25 forming the measurement transistor 221B.

Next, the tester 3 measures the current value I flowing through the NMOS transistor NT25 as the measurement transistor 221B while changing the reference voltage Vref from 0 V to the power supply voltage of the semiconductor integrated circuit.
The reference voltage Vref and the current value I at this time are stored in the storage device 41 of the PC 4 as voltage-current value characteristics, for example.

Next, the select signal SEL and its inverted signal / SEL signal are set so that the internal node 21 is connected to the gate of the measurement transistor 221B.
In the case of the selector 222B in FIG. 5, the select signal SEL is set to the high level (HI), and the inverted signal / SEL is set to the low level (LO). As a result, the PMOS transistor PT25 is turned off and the PMOS transistor PT26 is turned on.
That is, the PMOS transistor PT26 is turned on, and the potential Vnode of the internal node 21 is applied to the gate of the NMOS transistor NT25 that forms the measurement transistor 221B.

Here, in the tester 3, the current value I flowing through the NMOS transistor NT25 is measured in a state where the potential Vnode of the internal node 21 is applied to the gate of the NMOS transistor NT25 forming the measurement transistor 221B.
Then, the potential Vnode of the internal node 21 is derived from the measured value and the voltage-current characteristic acquired in advance using the PC 4 or the like.

  According to the measurement circuit of FIG. 5, the selector can be made small. However, since it is difficult to measure a potential close to VSS, the measurement circuit in FIG. 5 is applied when the expected measurement potential is a potential close to the power supply voltage VDD.

For example, as shown in the measurement circuit of FIG. 6, it is possible to increase the number of signals to be selected and increase the number of nodes that can be selected so that the potentials of many nodes can be measured.
FIG. 6 shows a measurement circuit that measures the potentials of the three types of first to third internal nodes 21-1, 21-2, and 21-3 in the vicinity of VSS.

The measurement transistor 221C is formed of a thin-film PMOS transistor PT24 as in FIG.
An NMOS transistor NT23 is connected between the reference voltage supply terminal TVref and the gate of the PMOS transistor PT24 as the measurement transistor 221C.
An NMOS transistor NT24 is connected between the first internal node 21-1 and the gate of the PMOS transistor PT24 as the measurement transistor 221C.
An NMOS transistor NT26 is connected between the second internal node 21-2 and the gate of the PMOS transistor PT24 as the measurement transistor 221C.
An NMOS transistor NT27 is connected between the third internal node 21-3 and the gate of the PMOS transistor PT24 as the measurement transistor 221C.

  The select signal SEL0 is supplied to the gate of the NMOS transistor NT23, the select signal SEL1 is supplied to the gate of the NMOS transistor NT24, the select signal SEL2 is supplied to the gate of the NMOS transistor NT26, and the select signal SEL3 is supplied to the gate of the NMOS transistor NT27. Is supplied.

  Note that the levels of the select signals SEL0 to SEL3 are individually controlled. The select signals SEL0 to SEL3 may be generated in the semiconductor integrated circuit 2 or may be configured to be supplied directly from the tester 3 side.

Also in this case, first, the select signals SEL0 to SEL3 are set so that the supply terminal TVref of the reference voltage Vref is connected to the gate of the measurement transistor 221C.
In the case of the selector 222C in FIG. 6, the select signal SEL0 is set to the high level (HI), and the select signals SEL1 to SEL3 are set to the low level (L0). Thereby, the NMOS transistor NT23 is turned on, and the NMOS transistors NT24, NT26, NT27 are turned off.
That is, the NMOS transistor NT23 is turned on, and the reference voltage Vref supplied by the tester 3 is applied to the gate of the PMOS transistor PT24 that forms the measurement transistor 221C.

Next, in the tester 3, the current value I flowing through the PMOS transistor PT24, which is the measurement transistor 221C, is measured while changing the reference voltage Vref from 0 V to the power supply voltage VDD of the semiconductor integrated circuit 2.
The reference voltage Vref and the current value I at this time are stored in the storage device 41 of the PC 4 as voltage-current value characteristics, for example.

Next, select signals SEL0 to SEL3 are set so that, for example, first internal node 21-1 is connected to the gate of measurement transistor 221C.
In the case of the selector of FIG. 6, the select signal SEL1 is set to the high level (HI), and the select signals SEL0, SEL2, and SEL3 are set to the low level (LO). As a result, the NMOS transistors NT23, NT26, NT27 are turned off and the NMOS transistor NT24 is turned on.
That is, the NMOS transistor NT24 is turned on, and the potential Vnode1 of the first internal node 21-1 is applied to the gate of the PMOS transistor PT24 that forms the measurement transistor 221C.

Here, in the tester 3, the current value I flowing through the PMOS transistor PT24 is measured in a state where the potential Vnode1 of the first internal node 21-1 is applied to the gate of the PMOS transistor PT24 forming the measurement transistor 221C.
Then, the potential Vnode1 of the first internal node 21-1 is derived from the measured value and the voltage-current characteristic acquired in advance using the PC 4 or the like.

Further, select signals SEL0 to SEL3 are set so that, for example, the second internal node 21-2 is connected to the gate of the measurement transistor 221C.
In the case of the selector 222C in FIG. 6, the select signal SEL2 is set to the high level (HI), and the select signals SEL0, SEL2, and SEL3 are set to the low level (LO). As a result, the NMOS transistors NT23, NT24, NT27 are turned off and the NMOS transistor NT26 is turned on.
That is, the NMOS transistor NT26 is turned on, and the potential Vnode2 of the second internal node 21-2 is applied to the gate of the PMOS transistor PT24 that forms the measurement transistor 221C.

Here, in the tester 3, the current value I flowing through the PMOS transistor PT24 is measured in a state where the potential Vnode2 of the second internal node 21-2 is applied to the gate of the PMOS transistor PT24 forming the measurement transistor 221C.
Then, the potential Vnode2 of the second internal node 21-2 is derived from the measured value and the voltage-current characteristic acquired in advance using the PC 4 or the like.

Further, select signals SEL0 to SEL3 are set so that, for example, the third internal node 21-3 is connected to the gate of the measurement transistor 221C.
In the case of the selector 222C in FIG. 6, the select signal SEL3 is set to the high level (HI), and the select signals SEL0, SEL1, and SEL2 are set to the low level (LO). As a result, the NMOS transistors NT23, NT24, NT26 are turned off and the NMOS transistor NT27 is turned on.
That is, the NMOS transistor NT27 is turned on, and the potential Vnode3 of the third internal node 21-3 is applied to the gate of the PMOS transistor PT24 that forms the measurement transistor 221C.

Here, in the tester 3, the current value I flowing through the PMOS transistor PT24 is measured in a state where the potential Vnode3 of the third internal node 21-3 is applied to the gate of the PMOS transistor PT24 forming the measurement transistor 221C.
Then, the potential Vnode3 of the third internal node 21-3 is derived from the measured value and the voltage-current characteristic acquired in advance using the PC 4 or the like.

  Note that the configuration corresponding to a plurality of nodes as shown in FIG. 6 can also be applied to the measurement circuits shown in FIGS.

As described above, according to the present embodiment, a voltage measurement system that indirectly measures the node potential in the semiconductor integrated circuit 2 without applying a probe or directly outputting it to an external terminal is configured. Yes.
Specifically, one measuring transistor 221 is mounted inside the semiconductor integrated circuit 2, and first, the selector 222 is connected so that an external power supply (supply terminal TVref of the reference voltage Vref) is directly connected to the gate input of the measuring transistor 221. To select the voltage-current characteristic in the storage device. Next, the measurement transistor 221 is selected so that the internal node is connected to the gate of the measurement transistor 221, and the current flowing through the measurement transistor 221 is measured. The internal node potential is derived from the current and voltage-current characteristics.
Since it has the above structure, according to this embodiment, the following effects can be acquired.

Since the thick film transistor is a device that is always used in an I / O cell or the like, even if this measurement circuit is mounted, the manufacturing process does not change.
Since it is not necessary to pull out the internal node directly to the outside of the chip or touch the probe needle, it is highly reliable and the additional capacitance component can be suppressed, so that a more realistic value can be measured.
Since it is not necessary to perform measurement by needle contact, the measurement environment (limited to temperature and assembly chip) and the number of measurement samples (convenience of measurement time) are released.
When measuring the potential, it is not a method of comparing with the reference voltage every time. By measuring the change in the current value I flowing in the measurement transistor in real time, it is relatively easy to change the temporal potential in one measurement. It can be measured.
Since there is only one measuring transistor that acquires voltage-current characteristics, it is resistant to manufacturing variations.
Although the manufacturing variation of the selector can be considered, since it is used as a device that propagates only the voltage, it is strong against the manufacturing variation as a measurement circuit.

It is a figure which shows the structural example of the node electric potential measurement system of the semiconductor integrated circuit device which concerns on embodiment of this invention. It is a circuit diagram which shows one structural example of the measurement circuit which concerns on this embodiment. It is a figure which shows that the voltage-current characteristic of the measurement transistor in this embodiment has linearity. It is a circuit diagram which shows the 2nd structural example of the measurement circuit which concerns on this embodiment. It is a circuit diagram which shows the 3rd structural example of the measurement circuit which concerns on this embodiment. It is a circuit diagram which shows the 4th structural example of the measurement circuit which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Node voltage measuring system, 2 ... Semiconductor integrated circuit, 21 ... Internal node, 221, 221A, 221B, 221C ... Measuring transistor, PT21, PT24 ... PMOS transistor as measuring transistor, NT25 ... NMOS transistor as a measurement transistor, 222 ... select circuit, 3 ... tester, 31 ... current measurement unit (A), 4 ... personal computer (PC), 41. ··Storage device.

Claims (8)

At least one internal node of the potential measurement object;
A power supply voltage terminal that can be connected to the outside;
A reference potential terminal that can be connected to the outside;
A reference voltage supply terminal to which a reference voltage is supplied from the outside;
One measuring transistor for measuring the potential of the internal node;
A selector connected to the control terminal of the measurement transistor,
The above selector
In accordance with a select signal, the control terminal of the measurement transistor is selectively connected to the reference voltage supply terminal or the internal node,
The measurement transistor is
The first terminal is connected to the power supply voltage terminal, the second terminal is connected to the reference potential terminal, and flows when the reference voltage is supplied to the control terminal and when the internal node potential is applied. A semiconductor integrated circuit in which current can be measured through the power supply voltage terminal and the reference potential terminal. The measurement transistor is
With the control terminal connected to the reference voltage supply terminal by the selector, a voltage-current characteristic is obtained when an external reference voltage that is changed with a predetermined range is applied to the control terminal,
With the control terminal connected to the internal node by the selector, a current is measured when the internal node potential is applied to the control terminal,
The semiconductor integrated circuit according to claim 1, wherein the internal node potential is derived from the acquired voltage-current characteristic and the measured current. The measurement transistor is
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed of a p-channel insulated gate field effect transistor having a threshold voltage higher than that of the thin film transistor. The measurement transistor is
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed of a p-channel insulated gate field effect transistor. The measurement transistor is
The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is formed of an n-channel insulated gate field effect transistor. A semiconductor integrated circuit;
A measuring device capable of measuring the node potential of the semiconductor integrated circuit,
The semiconductor integrated circuit is
At least one internal node of the potential measurement object;
A power supply voltage terminal that can be connected to the outside;
A reference potential terminal that can be connected to the outside;
A reference voltage supply terminal to which a reference voltage is supplied from the outside;
One measuring transistor for measuring the potential of the internal node;
A selector connected to the control terminal of the measurement transistor,
The above selector
In accordance with a select signal, the control terminal of the measurement transistor is selectively connected to the reference voltage supply terminal or the internal node,
The measurement transistor is
The first terminal is connected to the power supply voltage terminal, the second terminal is connected to the reference potential terminal, and flows when the reference voltage is supplied to the control terminal and when the internal node potential is applied. The current can be measured through the power supply voltage terminal and the reference potential terminal,
The measuring device is
In the semiconductor integrated circuit, when the control terminal of the measurement transistor is connected to the reference voltage supply terminal by at least the selector, the reference voltage is supplied to the reference voltage supply terminal while being changed within a predetermined range. The current flowing through the measurement transistor is measured through the power supply voltage terminal and the reference potential terminal to obtain a voltage-current characteristic.
In the semiconductor integrated circuit, when the control terminal of the measurement transistor is connected to the internal node by the selector, a current flowing through the measurement transistor is measured through the power supply voltage terminal and the reference potential terminal.
A node potential measurement system that derives the internal node potential from the acquired voltage-current characteristics and the measured current. A holding unit for storing the acquired voltage-current characteristic information;
The measuring device is
Holding the acquired voltage-current characteristic information in the holding unit,
The node potential measurement system according to claim 6, wherein the internal node potential is derived from the voltage-current characteristic held in the holding unit and the measurement current. Semiconductor integrated circuit
At least one internal node of the potential measurement object;
A power supply voltage terminal that can be connected to the outside;
A reference potential terminal that can be connected to the outside;
A reference voltage supply terminal to which a reference voltage is supplied from the outside;
One measuring transistor for measuring the potential of the internal node,
In response to a select signal, the control terminal of the measurement transistor is selectively connected to the reference voltage supply terminal or the internal node,
In the semiconductor integrated circuit, the control terminal of the measurement transistor is connected to the reference voltage supply terminal,
Supply the reference voltage to the reference voltage supply terminal while changing it in a predetermined range, measure the current flowing through the measurement transistor through the power supply voltage terminal and the reference potential terminal, and obtain voltage-current characteristics.
In the semiconductor integrated circuit, the control terminal of the measurement transistor is connected to the internal node,
Measure the current flowing through the measurement transistor through the power supply voltage terminal and the reference potential terminal,
A node potential measuring method for deriving the internal node potential from the acquired voltage-current characteristic and the measured current.

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