JP2009259990A - Semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor module with high reliability, the module being obtained by equalizing currents flowing to respective semiconductor switch elements constituting the semiconductor module. <P>SOLUTION: The semiconductor module includes IGBT chips 2a and 2b which are connected in parallel, an emitter relay conductor 11a for connecting emitter terminals 9a to an emitter electrode of IGBT chips 2a and 2b, a gate relay conductor 18 for connecting gate terminals 20 to a gate electrode, and a control emitter relay conductor 19 for connecting a control emitter terminal 21 to a control emitter electrode. The gate relay conductor 18 is constituted so that a potential difference equal to a potential difference generated between the control emitter electrodes of the IGBT chips 2a and 2b may be generated between the gate electrodes of the IGBT chips 2a and 2b with induced electromotive force generated in the emitter relay conductor 11a or control emitter relay conductor 19. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor module composed of a voltage-driven semiconductor switching element such as an insulated gate bipolar transistor (IGBT), and more particularly to a wiring structure of the semiconductor module.

  In a semiconductor module in which a plurality of semiconductor switch elements are connected in parallel, when an induced electromotive force is generated between the gate and emitter of each semiconductor switch element due to the main current, there is a difference in the gate-emitter voltage between the semiconductor switch elements. As a result, there is a problem that the current flowing through each semiconductor switching element becomes non-uniform and the reliability of the semiconductor module is lowered.

  As a conventional technique for solving such a problem, a voltage source that generates a voltage corresponding to a voltage drop of a reactor component generated in an inter-emitter connection conductor of semiconductor switch elements connected in parallel, and a voltage source There is a driving means for driving the semiconductor switch element, and a gate-emitter voltage of each semiconductor switch element is made uniform by applying a drop of the emitter potential due to the reactor component to the gate potential by a voltage source ( Patent Document 1).

Japanese Patent Laid-Open No. 7-177727 (FIG. 1)

  In the structure in which the voltage corresponding to the voltage drop of the reactor component generated in the connection conductor between the emitters of each semiconductor switch element in Patent Document 1 is applied to the gate potential, the emitter-side common terminal through which the main current flows is connected to the gate-emitter voltage. The reference potential is used, and the voltage difference between the gate and the emitter generated due to the difference in self-inductance in the emitter wiring of each semiconductor switch element is made uniform.

  Such a structure equalizes the voltage difference between the gate and the emitter caused by the difference in self-inductance of the emitter wiring of each semiconductor switch element. The voltage difference between the gate and the emitter generated due to the mutual inductance difference cannot be made uniform.

  In addition, in order to avoid variations in self-inductance in the emitter wiring, a control emitter wiring through which a minute current flows from the emitter electrode of each semiconductor chip is provided separately from the emitter wiring through which the main current, which is a large current, flows. In a structure that is not affected by the self-inductance as the reference potential of the emitter-to-emitter voltage, it is generated due to the difference in self-inductance of the emitter wiring of each semiconductor switch element as shown in Patent Document 1 above. In the structure in which the voltage drop is applied to the gate potential, it is impossible to equalize the voltage between the gate and the emitter and make the current flowing through each semiconductor switch element the same.

  If the current flowing through each semiconductor switch element is different and the current concentrates on a specific semiconductor switch element, the temperature of the semiconductor switch element rises, and the life of the semiconductor module is shortened or short-circuited by repeating high and low temperatures. In this case, there is a problem that durability of the case is lowered.

  The present invention has been made to solve the above-described problems, and has an object to provide a semiconductor module having a long life and high reliability by making the current flowing through each semiconductor switching element uniform. It is.

  In the semiconductor module according to the present invention, a plurality of semiconductor switch elements are connected in parallel, a collector-side wiring connecting the collector electrode and the collector terminal of the semiconductor switch element, and an emitter electrode and an emitter terminal of the semiconductor switch element Equipped with emitter-side wiring to be connected, gate-side wiring for connecting the gate electrode and gate terminal of the semiconductor switch element, and control emitter-side wiring for connecting the control emitter electrode and control emitter terminal of the semiconductor switch element A potential difference equivalent to the potential difference between the control emitter electrodes of the plurality of semiconductor switch elements generated by the induced electromotive force generated in the emitter side wiring and / or the control emitter side wiring is generated between the gate electrodes of the plurality of semiconductor switch elements. Thus, the gate side wiring is formed.

  According to the semiconductor module of the present invention, the plurality of semiconductor switch elements are connected in parallel, the collector-side wiring connecting the collector electrode and the collector terminal of the semiconductor switch element, and the emitter electrode and the emitter terminal of the semiconductor switch element An emitter-side wiring for connecting the gate electrode and the gate terminal of the semiconductor switch element, and a control emitter-side wiring for connecting the control emitter electrode and the control emitter terminal of the semiconductor switch element. A potential difference equivalent to the potential difference between the control emitter electrodes of the plurality of semiconductor switch elements generated by the induced electromotive force generated in the emitter side wiring and / or the control emitter side wiring is between the gate electrodes of the plurality of semiconductor switch elements. As the gate side wiring is formed, The gate voltage applied to the body switch element can be reduced, the flowing current can be made the same, and a highly reliable semiconductor module can be obtained.

Embodiment 1 FIG.
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1 is a perspective view showing an internal wiring structure of a semiconductor module 1 according to Embodiment 1 of the present invention, FIG. 2 is a perspective view showing only a collector side wiring in FIG. 1, and FIG. 3 is an emitter side wiring and a control emitter. 4 is a plan view, FIG. 5 is a perspective view showing only the gate side wiring, FIG. 6 is a plan view, and FIG. 7 is a plan view showing a current path in the collector side wiring. 8 is a plan view for showing a current path in the emitter-side wiring, and FIG. 9 is a simplified circuit diagram of the semiconductor module 1.

  In the figure, a plurality (two in FIG. 1) of IGBT chips 2a, 2b constituting the semiconductor switch element are placed on the collector patterns 3a, 3b, and the collector electrodes and collector patterns 3a of the IGBT chips 2a, 2b. , 3b are connected by solder or the like. The collector patterns 3a and 3b and the emitter patterns 4a and 4b are disposed on the insulating plates 5a and 5b, and a certain insulating distance is provided between the collector patterns 3a and 3b and the emitter patterns 4a and 4b. The insulating plates 5a and 5b are disposed on the base plate 6. The base plate 6 is a substrate constituting the semiconductor module 1, and the IGBT chips 2 a and 2 b are installed on the substrate of the semiconductor module 1.

  The emitter patterns 4a and 4b and the emitter electrodes of the IGBT chips 2a and 2b are connected by bonding wires 7a and 7b. The collector terminal 8a and the collector patterns 3a and 3b are connected via a collector relay conductor 10a, thereby forming a collector side wiring. The emitter terminal 9a and the emitter patterns 4a and 4b are connected via an emitter relay conductor 11a, thereby forming an emitter-side wiring.

  The gate relay conductor 18 and the control emitter relay conductor 19, which are control wires for the IGBT chips 2 a and 2 b, are arranged so as to be parallel to the base plate 6 and arranged at a certain distance. The gate relay conductor 18 is provided with a gate terminal 20 which is a positive terminal for connecting a gate power source, and the control emitter relay conductor 19 is provided with a control emitter terminal 21 which is a negative terminal for connecting a gate power source. .

  As shown in FIG. 5, the gate relay conductor 18 and the gate electrodes of the IGBT chips 2a and 2b are connected to each other through gate wires 12a and 12b, gate patterns 14a and 14b, and gate pins 16a and 16b. It is configured. As shown in FIG. 3, the control emitter relay conductor 19 and the control emitter electrodes of the IGBT chips 2a and 2b are connected via control emitter wires 13a and 13b, control emitter patterns 15a and 15b, and control emitter pins 17a and 17b. These constitute the control emitter side wiring.

  The gate patterns 14a and 14b and the control emitter patterns 15a and 15b are arranged on the insulating plates 5c and 5d with a certain insulating distance therebetween. A main current flows between the collector electrode and the emitter electrode, and a voltage signal for energizing and interrupting the main current is applied between the gate electrode and the control emitter electrode.

  IGBT chips 2a and 2b, collector patterns 3a and 3b, emitter patterns 4a and 4b, insulating plates 5a, 5b, 5c and 5d, gate patterns 14a and 14b, and control emitter patterns 15a and 15b are placed on the base plate 6. . As shown in FIG. 6, the gate relay conductor 18 is formed in a substantially U shape, and as shown in FIG. 4, the control emitter relay conductor 19 is formed in a substantially U shape. The control emitter relay conductors 19 are formed to have substantially the same dimensions by a printed circuit board or the like, and are arranged in parallel to each other and stacked so as to be seen from the base plate 6 side serving as a substrate.

  A portion of the gate relay conductor 18 that does not overlap the control emitter relay conductor 19 is disposed close to the emitter relay conductor 11a. In FIG. 2, only the collector patterns 3a and 3b, the collector terminal 8a, and the collector relay conductor 10a, which are collector-side wirings, are shown.

  In FIG. 3, emitter patterns 4a and 4b which are wiring on the emitter side, bonding wires 7a and 7b, emitter terminal 9a, emitter relay conductor 11a, control emitter wires 13a and 13b which are wiring on the control emitter side, and control emitter pattern. Only 15a, 15b, control emitter pins 17a, 17b, and control emitter relay conductor 19 are shown.

  As shown in FIG. 4, the emitter-side wiring and the control emitter-side wiring include the emitter electrodes of the IGBT chips 2a and 2b, bonding wires 7a and 7b, emitter patterns 4a and 4b, emitter relay conductor 11a, control emitter wires 13a and 13b, The control emitter patterns 15a and 15b, the control emitter pins 17a and 17b, and the control emitter relay conductor 19 form a closed loop.

  In FIG. 5, only the gate wires 12a and 12b, the gate pins 16a and 16b, and the gate relay conductor 18 which are the wirings on the gate side are shown. Further, as shown in FIG. 6, the gate-side wiring forms a closed loop.

  In FIG. 7, the main current enters the semiconductor module from the collector terminal 8a, is divided in two directions by the collector relay conductor 10a, and flows into the collector electrodes of the IGBT chips 2a and 2b through the collector patterns 3a and 3b. In FIG. 8, the current flowing out from the emitter electrodes of the IGBT chips 2a and 2b passes through the bonding wires 7a and 7b and the emitter patterns 4a and 4b. Flows out of the semiconductor module 1.

  The current path flowing through the collector relay conductor 10a indicated by the arrow A and the current path flowing through the emitter relay conductor 11a indicated by the arrow B are asymmetric with respect to the symmetry line 29 of the semiconductor module. On the other hand, in FIG. 7, the current path except for the arrow A has a symmetric relationship with respect to the symmetric line 29, and in FIG. It has become. The symmetry line 29 is defined by a vertical bisector that connects the IGBT chips 2a and 2b.

  Since a large frequency current flows through the semiconductor module 1, the magnetic flux formed by the current changes with time, and an induced electromotive force may be generated in another wiring. When the induced electromotive force is generated in the gate wiring or emitter wiring, the gate-emitter voltage of the IGBT chips 2a and 2b connected in parallel may be made uneven. In this case, the IGBT chips 2a and 2b connected in parallel The flowing current becomes uneven.

  The current paths excluding the arrows A and B are symmetrical with respect to the symmetry line 29. In FIGS. 4 and 6, the bonding wires 7a and 7b, the emitter patterns 4a and 4b, the emitter relay conductor 11a, the control emitter Emitter-side wiring composed of wires 13a and 13b, control emitter patterns 15a and 15b, control emitter pins 17a and 17b, control emitter relay conductor 19, and gate side composed of gate wires 12a and 12b, gate pins 16a and 16b, and gate relay conductor 18 Since the wiring is also formed so as to be substantially symmetric with respect to the symmetric line 29, in the induced electromotive force generated in the emitter side wiring and the gate side wiring by the current excluding the arrows A and B, the symmetric line 29 is made symmetric. It is generated almost equally on the left and right, so the gate-emitter voltage of IGBTs 2a and 2b For pot equivalent effect, not a problem.

  On the other hand, the currents indicated by the arrows A and B have an asymmetric relationship with respect to the symmetric line 29. The symmetric lines 29 are symmetric, and induced electromotive forces having different magnitudes are generated on the left and right emitter side wirings and gate side wirings. generate. In particular, the induced electromotive force generated in the emitter-side wiring and the gate-side wiring located in a parallel relationship with the currents of the arrows A and B is large. This is because it is most susceptible to magnetic flux generated by the currents indicated by arrows A and B.

  Therefore, in consideration of the above points, in the present invention, the gate relay conductor 18 is laminated and arranged so as to be parallel to the emitter relay conductor 11a and the control emitter relay conductor 19. With this configuration, as shown in FIG. 4, when the magnetic flux is interlinked by the time change of the main current flowing in the collector side wiring and the emitter side wiring indicated by arrows A and B, the emitter side wiring and the control emitter Inductive electromotive forces C and D are generated in the side wiring. In FIG. 6, when the magnetic flux is linked by the time change of the main current flowing through the collector side wiring and the emitter side wiring indicated by the arrows A and B, induced electromotive forces E and F are also generated in the gate side wiring.

  Since the gate side wiring, the emitter side wiring, and the control emitter side wiring are arranged so as to be stacked close to each other as described above, the induced electromotive forces C and E, D, and F generated by the magnetic flux are substantially equal. The induced electromotive forces C and E are larger than D and F because they are close to the currents indicated by the arrows A and B. Since the control emitter electrodes of the IGBT chips 2a and 2b are located between the emitter relay conductor 11a where the induced electromotive force C is generated and the control emitter relay conductor 19 where the induced electromotive force D is generated, the IGBT chips 2a and 2b have a control emitter electrode. If the voltage difference (potential difference) between the control emitter electrodes is V1, D <V1 <C. The gate electrodes of the IGBT chips 2a and 2b are located between the gate relay conductor 18 where the induced electromotive force E is generated and the gate relay conductor 18 where the induced electromotive force F is generated. When the voltage difference (potential difference) between the gate electrodes is V2, F <V2 <E. Since the values of C and E, D and F are substantially equal, and the gate electrodes and control emitter electrodes of the IGBT chips 2a and 2b exist at substantially the same position, the gate electrodes of the IGBT chips 2a and 2b are between the gate electrodes. The generated voltage difference V2 and the voltage difference V1 generated between the control emitter electrodes of the IGBT chips 2a and 2b are substantially equal (V1≈V2).

  Therefore, the gate-emitter voltage in the IGBT chip 2a and the gate-emitter voltage in the IGBT chip 2b are also equal, and the currents flowing in the IGBT chip 2a and the IGBT chip 2b can be equalized.

Embodiment 2. FIG.
10 is a perspective view showing an internal wiring structure of a semiconductor module according to Embodiment 2 of the present invention. The semiconductor module according to this embodiment includes a base plate 6, a first semiconductor module 27 on the base plate 6, a second semiconductor module 28, a gate relay conductor 182, and a control emitter relay conductor 192. The parts in the first semiconductor module 27 and the parts in the second semiconductor module 28 are made of the same material and dimensions, and have the same arrangement.

  In the first semiconductor module 27, IGBT chips 2a, 2b made of a plurality of semiconductor switch elements are placed on the collector patterns 3a, 3b, and in the second module 28, the IGBT chips 2c, 2d are collector patterns. It is mounted on 3c, 3d. The collector electrodes of the IGBT chips 2a, 2b, 2c, 2d and the collector patterns 3a, 3b, 3c, 3d are connected by solder or the like.

  Collector patterns 3a, 3b, 3c, 3d and emitter patterns 4a, 4b, 4c, 4d are arranged on insulating plates 5a, 5b, 5e, 5f, and collector patterns 3a, 3b, 3c, 3d and emitter patterns 4a, 4d A constant insulation distance is provided between 4b, 4c and 4d.

  The emitter patterns 4a, 4b, 4c, 4d and the emitter electrodes of the IGBT chips 2a, 2b, 2c, 2d are connected by bonding wires 7a, 7b, 7c, 7d. The collector terminals 8a and 8b and the collector patterns 3a, 3b, 3c, and 3d are connected via the collector relay conductors 10a and 10b, thereby forming a collector-side wiring. The emitter terminals 9a, 9b and the emitter patterns 4a, 4b, 4c, 4d are connected via the emitter relay conductors 11a, 11b, thereby forming an emitter side wiring.

  The collector terminal 8a and the collector terminal 8b of the semiconductor module are connected in parallel by an external wiring (not shown), and the emitter terminal 9a and the emitter terminal 9b are also connected in parallel by an external wiring (not shown). Therefore, the IGBT chips 2a, 2b, 2c, 2d in the semiconductor module are connected in parallel to each other.

  The gate relay conductor 182 and the control emitter relay conductor 192, which are control wires for the IGBT chips 2a, 2b, 2c, and 2d, are parallel to the base plate 6 and overlapped when viewed from the base plate 6 side. In addition to being arranged, they are arranged at a certain distance. The gate relay conductor 182 is provided with a gate terminal 20 which is a positive terminal for connecting a gate power source, and the control emitter relay conductor 192 is provided with a control emitter terminal 21 which is a negative terminal for connecting a gate power source.

  The gate relay conductor 182 and the gate electrodes of the IGBT chips 2a, 2b, 2c, and 2d are connected to the gate wires 12a, 12b, 12c, and 12d, the gate patterns 14a, 14b, 14c, and 14d, and the gate pins 16a, 16b, 16c, and 16d. The gate side wiring is configured by the connection. The control emitter relay conductor 192 and the control emitter electrodes of the IGBT chips 2a, 2b, 2c, 2d are control emitter wires 13a, 13b, 13c, 13d, control emitter patterns 15a, 15b, 15c, 15d, and control emitter pins 17a, 17b. , 17c, 17d to form a control emitter side wiring.

  The gate patterns 14a, 14b, 14c, and 14d and the control emitter patterns 15a, 15b, 15c, and 15d are arranged on the insulating plates 5c, 5d, 5g, and 5h with a predetermined insulation distance. FIG. 11 is a plan view showing only the emitter-side wiring and the control emitter-side wiring.

  FIG. 12 is a plan view showing only the gate-side wiring. The gate relay conductor 182 and the control emitter relay conductor 192 are formed of a printed circuit board or the like, and are arranged in parallel with each other and stacked. Further, a part of the gate relay conductor 182 that does not overlap the control emitter relay conductor 192 is arranged so as to be parallel to and stacked on the emitter relay conductors 11a and 11b.

  Asymmetrical current paths with respect to the symmetric line 29 are arrows A and B and arrows G and H. The symmetric line 29 is symmetric to generate induced electromotive forces having different sizes in the left and right emitter side wirings and gate side wirings. . In particular, the induced electromotive force generated in the emitter-side wiring and the gate-side wiring located in a parallel relationship with the currents of arrows A and B and arrows G and H is large.

  In the present embodiment, because of the complicated structure in which many asymmetric current paths are formed with respect to the symmetric line 29, the emitter-side wiring and the gate-side wiring parallel to these lines are induced by many current components. Power is generated and it becomes more difficult to equalize the voltage between the gate electrode and the control emitter electrode.

  Therefore, in consideration of the above points, in the present embodiment, the gate relay conductor 182 is configured in a substantially Japanese character shape, and is disposed close to the emitter relay conductors 11a and 11b and the control emitter relay conductor 192. .

  With this configuration, induced electromotive forces C, D, and I are generated in the emitter-side wiring, and induced electromotive forces E, F, and J are generated in the gate-side wiring. Since the gate-side wiring and the emitter-side wiring are arranged close to each other as described above, the induced electromotive forces C and E, D and F, and I and J generated by the magnetic flux are almost equal.

  Therefore, even if the structure has many asymmetric current paths with respect to the symmetric line 29, the voltage generated between the gate electrodes of the IGBT chips 2a, 2b, 2c, 2d and the IGBT chips 2a, 2b, 2c, 2d. Since the voltages generated between the control emitter electrodes of the IGBT chips 2a, 2b, 2c and 2d can be made substantially equal, the voltages between the gate electrodes and the control emitter electrodes of the IGBT chips 2a, 2b, 2c and 2d can be made equal. The current flowing through 2d can be made uniform. In the first and second embodiments, the case where two or four IGBT chips are provided in parallel has been shown. However, the number of IGBT chips can be increased to 6, 8,. Can be formed.

Embodiment 3 FIG.
13 is a perspective view showing an internal wiring structure of a semiconductor module according to Embodiment 3 of the present invention, FIG. 14 is a plan view showing only the emitter-side wiring and the control emitter-side wiring, and FIG. 15 is a plan view showing only the gate-side wiring. It is.

  The current paths excluding the arrows A and B are symmetrical with respect to the symmetry line 29, and the emitter side wiring and the gate side wiring are formed so as to be substantially symmetrical with respect to the symmetry line 29. On the other hand, the current paths indicated by the arrows A and B have an asymmetric relationship with respect to the symmetry line 29 of the semiconductor module. Different induced electromotive forces are generated. In particular, the induced electromotive force generated in the emitter-side wiring and the gate-side wiring, which is located in a parallel relationship with the currents of the arrows A and B and has the same path length as the arrows A and B, is large.

  Therefore, in consideration of the above points, in the present invention, as shown in FIGS. 14 and 15, the gate relay conductor 183, the emitter relay conductor 11 a, and the control emitter relay conductor 19 are parallel to the currents of the arrows A and B. The portions located in the relationship and having the same path length as the arrow A and the arrow B are arranged so as to be stacked close to each other. That is, in the present embodiment, as shown in FIGS. 5 and 6, the entire gate relay conductor is not formed in a substantially square shape, but in a portion having the same path length as that of the arrows A and B. Is formed in a substantially square shape so as to correspond only to.

  With the above configuration, induced electromotive forces C and D are generated in the emitter side wiring, and induced electromotive forces E and F are generated in the gate side wiring. Since the gate-side wiring and the emitter-side wiring are arranged close as described above, the induced electromotive forces C and E, D, and F generated by the magnetic flux are almost equal.

  Accordingly, since the voltage generated between the gate electrodes of the IGBT chips 2a and 2b and the voltage generated between the control emitter electrodes of the IGBT chips 2a and 2b can be made substantially equal, the gate electrodes of the IGBT chips 2a and 2b and the control are controlled. Since the voltage between the emitter electrodes can be made uniform, the current flowing through the IGBT chips 2a and 2b can be made uniform, and the size of the gate relay conductor 183 can be reduced as compared with the case of the first embodiment. Even if the gate relay conductor 18 having the structure as shown in FIG. 1 cannot be installed due to the installation space, the installation space can be obtained by configuring the gate relay conductor 183 as shown in FIG. The gate relay conductor 183 can be installed even in a case where there are restrictions.

It is a perspective view which shows the internal wiring structure of the semiconductor module 1 by Embodiment 1 of this invention. It is the perspective view which took out and showed only the collector side wiring. It is a perspective view which shows only an emitter side wiring and a control emitter side wiring. It is a top view which shows only an emitter side wiring and a control emitter side wiring. It is a perspective view which shows only gate side wiring. It is a top view which shows only gate side wiring. It is a top view for showing the course of the current in a collector side wiring. It is a top view for showing the path | route of the electric current in emitter side wiring. It is a simplified circuit diagram of a semiconductor module. It is a perspective view which shows the internal wiring structure of the semiconductor module by Embodiment 2 of this invention. It is a top view which shows only an emitter side wiring and a control emitter side wiring. It is a top view which shows only gate side wiring. It is a perspective view which shows the internal wiring structure of the semiconductor module by Embodiment 3 of this invention. It is a top view which shows only an emitter side wiring and a control emitter side wiring. It is a top view which shows only gate side wiring.

Explanation of symbols

1 Semiconductor module, 2a, 2b, 2c, 2d IGBT chip,
8a, 8b collector terminal, 9a, 9b emitter terminal, 20 gate terminal,
21 Control emitter terminal, 29 symmetry line.

Claims (3)

A plurality of semiconductor switch elements connected in parallel; a collector-side wiring connecting the collector electrode and the collector terminal of the semiconductor switch element; and an emitter-side wiring connecting the emitter electrode and the emitter terminal of the semiconductor switch element; A semiconductor module comprising: a gate-side wiring that connects a gate electrode and a gate terminal of the semiconductor switch element; and a control emitter-side wiring that connects a control emitter electrode and a control emitter terminal of the semiconductor switch element. A potential difference equivalent to a potential difference between the control emitter electrodes of the plurality of semiconductor switch elements generated by the induced electromotive force generated in the side wiring and / or the control emitter side wiring is generated between the gate electrodes of the plurality of semiconductor switch elements. So that the gate-side wiring was formed A semiconductor module characterized by that. Part or all of the emitter-side wiring or the control emitter-side wiring and part or all of the gate-side wiring are parallel to each other and overlap each other when viewed from the substrate side on which the semiconductor switch element is installed. The semiconductor module according to claim 1, wherein the semiconductor module is arranged as described above. The gate-side wiring is formed at a position corresponding to a current path that flows through the collector-side wiring and the emitter-side wiring and is not symmetrical with respect to the symmetry line of the semiconductor module. The semiconductor module according to claim 1 or 2.

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