JP2009259403A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can supply a bank with a stable internal voltage irrespective to the number of operating banks. <P>SOLUTION: Internal power supply circuits (1701 and 1703) are provided in a prescribed number of sets of banks (B1-B4) and (B5-B8), respectively. Internal power supply lines (2001B1-2001B8), which transmit internal power supply voltages generated by the internal power supply circuits to sense amplifiers (SA1-SAn, 2007), are independently provided for each set of banks, and sense ground wires (2003B1-2003B8), which transmit ground voltages to the sense amplifiers of the respective banks, are independently arranged in the banks, and are connected to each other in an area outside the banks, for each of the sets of banks. The sense ground wires are separated between the sets of banks. Noise in banks is prevented from being transmitted to other banks, and consequently an internal voltage is stably transmitted to the sense amplifier of each bank. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an internal voltage supply circuit for supplying an internal voltage to be supplied to an activated bank.

  FIG. 26 is a diagram showing a configuration of an internal voltage generation circuit 2600 in the conventional semiconductor memory device disclosed in Japanese Patent Laid-Open No. 1-276486.

  In FIG. 26, when the row address strobe signal / RAS (/ represents a bar) signal becomes H (logic high) level and is not selected, the voltage VA at the node NA is the first substrate bias voltage generating circuit 10. The ring oscillator 11 in FIG. 1 oscillates and a first substrate bias voltage is applied to the semiconductor substrate. When the row address strobe signal / RAS signal becomes L (logic low) level, the ring oscillator 21 in the second substrate bias voltage generation circuit 20 performs the oscillation operation until the substrate voltage reaches a predetermined level, and reaches the predetermined level. After reaching this point, the oscillation is stopped when the non-selected state is reached. That is, the semiconductor memory device operates only when it is in an active state, and power consumption when the semiconductor memory device is in a (standby state) non-selected state can be reduced.

  However, in the case of a semiconductor memory device having a plurality of banks, the range of the operating memory array varies depending on the number of operating banks. Since the current consumption increases as the number of operating banks increases, it is necessary to increase the internal voltage supply capability of an internal voltage supply circuit such as a substrate voltage (Vbb) supply circuit. On the other hand, if the number of operating banks is small, the internal voltage supply capability of the internal voltage supply circuit does not need to be increased more than necessary.

  Therefore, in such a conventional semiconductor memory device, the internal voltage supply circuit does not change the supply capability of the internal voltage depending on the number of operating banks, so the supply capability may be insufficient depending on the number of operating banks. There has been a problem that the potential level tends to fluctuate during operation.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor memory device capable of supplying a stable internal voltage regardless of the number of operating banks. .

  The semiconductor memory device according to the present invention includes first to second N banks each provided with a circuit including a memory cell array having a plurality of memory cells and a plurality of sense amplifiers for sensing data in these memory cells. A first PMOS transistor having one electrode to which an external power supply voltage supplied from the outside is input and the other electrode that outputs a first internal power supply voltage obtained by stepping down the external power supply voltage; and a first internal power supply voltage And a voltage at the internal step-down level are input, and a first current mirror type amplifier circuit that outputs a voltage to the gate electrode of the first PMOS transistor according to the comparison result of the first internal power supply voltage and the voltage at the internal step-down level And is activated in response to any of the first to Nth external bank address signals indicating the selection of the first to Nth banks given from the outside Accordingly, the first internal step-down circuit for outputting the first internal power supply voltage, one electrode for inputting the external power supply voltage, and the other electrode for outputting the second internal power supply voltage obtained by stepping down the external power supply voltage are provided. The second PMOS transistor, the second internal power supply voltage and the internal step-down voltage are input, and the second PMOS transistor is selected according to the comparison result between the second internal power supply voltage and the internal step-down voltage. And N + 1 to 2N external bank address signals indicating selection of the N + 1 to 2N banks given from the outside The signal activated in response to any of the above, the second internal step-down circuit for outputting the second internal power supply voltage, and extending from outside the memory cell array region into the memory cell array region, The internal power supply voltage is wired to the plurality of sense amplifiers of the corresponding memory array, and at least one of the first to Nth external bank address signals is activated. Even in this case, in response to this activation, a plurality of first wirings to which the internal power supply voltage is supplied and the region extending from the memory cell array region to the memory cell array region, The internal power supply voltage is wired in a region of the memory cell array corresponding to the 2Nth bank, and supplies an internal power supply voltage to a plurality of sense amplifiers of the corresponding memory array, and at least one of the N + 1th to 2Nth external bank address signals is supplied. Even when activated, a plurality of second wirings to which an internal power supply voltage is supplied and a plurality of first wirings are connected to the memory cell array region in response to the activation. In comprising a third wiring connecting, the fourth wiring connecting a plurality of the second wiring outside the memory cell array region. The third wiring and the fourth wiring are not connected.

  The semiconductor memory device of the present invention can provide a semiconductor device capable of supplying a stable internal voltage regardless of the number of operating banks.

  In addition, it is possible to prevent the generated noise on the internal power supply line from being transmitted to other activated banks and causing malfunctions.

  Furthermore, it is possible to prevent the generated noise on the ground line from being transmitted to another activated bank and causing a malfunction.

1 is a block diagram showing a configuration of a semiconductor memory device 100 according to a first embodiment of the present invention. It is a circuit diagram which shows an example of the Vbb pump 109 (, 111) of FIG. It is a block diagram which shows the structure of the semiconductor memory device 300 of Embodiment 2 of this invention. It is a block diagram which shows the structure of the semiconductor memory device 400 of Embodiment 3 of this invention. FIG. 5 is a circuit diagram illustrating an example of a Vpp pump 409 (, 411) in FIG. 4. It is a block diagram which shows the structure of the semiconductor memory device 900 of Embodiment 4 of this invention. It is a block diagram which shows the structure of the semiconductor memory device 600 of Embodiment 5 of this invention. FIG. 8 is a circuit diagram illustrating an example of a VDC circuit 609 (, 611) in FIG. 7. It is a block diagram which shows the structure of the semiconductor memory device 800 of Embodiment 6 of this invention. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 7 of this invention. 11 is a timing chart showing bank activation signals generated by an activation signal generation circuit in the semiconductor memory device of FIG. 10; 11 is a timing chart showing bank activation signals generated by an activation signal generation circuit in the semiconductor memory device of FIG. 10; FIG. 11 is a circuit diagram showing a VDC circuit which is an example of the VDC circuit of FIG. 10. It is a circuit diagram which shows the VDC circuit contained in the semiconductor memory device of Embodiment 8 of this invention. FIG. 15 is a circuit diagram showing a VDC circuit which is an improved example of the VDC circuit of FIG. 14. It is a block diagram which shows the principal part of the semiconductor memory device of Embodiment 9 of this invention. It is a block diagram which shows the structure of the principal part of the semiconductor memory device of Embodiment 10 of this invention. It is a block diagram which shows the structure of the semiconductor memory device of Embodiment 11 of this invention. FIG. 19 is a circuit diagram illustrating a VDC circuit which is an example of the VDC circuit in FIG. 18. It is a circuit diagram which shows the structure of the semiconductor memory device of Embodiment 12 of this invention. It is a circuit diagram which shows the semiconductor memory device of Embodiment 13 of this invention. It is a circuit diagram which shows the semiconductor memory device of Embodiment 14 of this invention. It is a circuit diagram which shows the semiconductor memory device of Embodiment 15 of this invention. It is a circuit diagram which shows the Vpp pump in the semiconductor memory device of Embodiment 16 of this invention. It is a circuit diagram which shows the Vbb pump in the semiconductor memory device of Embodiment 17 of this invention. It is a figure which shows the structure of the internal voltage supply circuit 2600 in the conventional semiconductor memory device.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same reference numerals denote the same or corresponding parts.

(1) Embodiment 1
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device 100 according to the first embodiment of the present invention. FIG. 1 shows a case where the number of banks in the memory cell array is two for simplification.

  Here, since the bank address signals indicating the banks need only be different from each other corresponding to the banks, for further simplification, one of the two banks B1 and B2 is the external bank address signal. ext. It is activated when BA (hereinafter abbreviated as ext.BA) is at H (logic high) level, and the other bank B2 is ext. External bank address signal ext. It is activated when / BA (hereinafter abbreviated as ext./BA) is at the H level.

  Referring to FIG. 1, semiconductor memory device 100 has a memory cell array 113 divided into two banks B1 and B2, and an external row address strobe signal (hereinafter abbreviated as ext./RAS) as an internal row address strobe. Signal (hereinafter abbreviated as int./RAS) int. RAS buffer circuit 103 for converting to / RAS, int. / RAS generating clock signal CLK1 synchronized with RAS, ext. Int. BA, int. Address buffer 107 for outputting / BA and Vbb pumps 109 and 111 for supplying substrate voltage Vbb are included.

  The output node of the RAS buffer circuit 103 is connected to the input node of the clock generation circuit 105, and the output node of the clock generation circuit 105 is connected to the Vbb pumps 109 and 111. Of the two output nodes of the address buffer 107, int. The output node from which BA is output is sent to the bank B1 and the Vbb pump 109 in the memory cell array 113, int. The output node from which / BA is output is connected to the bank B2 and the Vbb pump 111 in the memory cell array 113. A Vbb output node N1 for outputting Vbb of each of the Vbb pumps 109 and 111 is connected to the banks B1 and B2.

  When there are a plurality of banks, each of the output nodes of the address buffer 107 is connected to a bank corresponding to the internal bank address that it outputs.

  In FIG. 1, the RAS buffer circuit 103 includes ext. / RAS int. The data is converted into / RAS and output to the clock generation circuit 105. The clock generation circuit 105 receives the int. / RAS based on int. Clock signal CLK1 synchronized with / RAS is generated and input to Vbb pumps 109 and 111.

  On the other hand, ext. When BA is input, the address buffer 107 stores int. BA is supplied to the Vbb pump 109, int. / BA is output to the Vbb pump 111. These int. BA, int. In response to / BA, Vbb pump 109 or 111 operates.

  FIG. 2 is a circuit diagram showing an example of the Vbb pump 109 (, 111) of FIG. Referring to FIG. 2, Vbb pump 109 (111) includes a NAND gate 201, a capacitor Cp, and P channel MOS transistors (hereinafter abbreviated as PMOS transistors) 205 207.

  The output node of the NAND gate 201 is connected to one electrode of the capacitor Cp. The source electrode and gate electrode of the PMOS transistor 207 are connected to a ground potential (hereinafter referred to as GND). The source electrode and gate electrode of the PMOS transistor 205 are connected to the drain electrode of the PMOS transistor 207 and the other electrode of the capacitor Cp. The drain electrode of the PMOS transistor 205 is connected to the Vbb output node N1 for outputting the substrate voltage Vbb.

  The NAND gate 201 receives the clock signal CLK1 generated by the clock generation circuit 105 and the internal bank address signal (int.BA in the Vbb pump 109 and int.BA in the Vbb pump 111) from the address buffer 107. Is done.

  H level internal bank address signal (int.BA or int./BA) is input to NAND gate 201, and int. When the clock signal CLK1 changes from L (logic low) level to H level in synchronization with / RAS, the output of the NAND gate 201 changes from H level to L level, and the voltage of the other electrode of the capacitor Cp changes from -Vthp to -Vcc-. The substrate voltage Vbb is generated by extracting to a negative voltage of Vthp (= Vbb). Here, Vthp is a threshold voltage of the PMOS transistors 205 and 207.

  That is, when bank B1 is activated, ext. BA becomes H level and is input to the address buffer 107. The int. BA sends Vbb pump 109 with L level int. / BA is output to the Vbb pump 111. And this int. BA and int. The Vbb pump 109 is operated by the clock signal CLK1 synchronized with / RAS, and the substrate voltage Vbb is supplied to the bank B1.

  When bank B2 is activated, ext. BA becomes L level and is input to the address buffer 107. The int. BA sends Vbb pump 109 to H level int. / BA is output to the Vbb pump 111. And this int. The Vbb pump 111 is operated by the clock signal CLK1 synchronized with / RAS, and the substrate voltage Vbb is supplied to the bank B2.

  As described above, since each bank has a Vbb pump, even when switching from a bank to another bank is shorter than the response time of the Vbb pump, a stable voltage of Vbb level regardless of the number of operating banks. Can be supplied to the bank based on the input of the row address signal.

(2) Embodiment 2
FIG. 3 is a block diagram showing a configuration of the semiconductor memory device 300 according to the second embodiment of the present invention. In the first embodiment, ext. Although the operation of the Vbb pump is synchronized with RAS (int./RAS), in the second embodiment, the external column address strobe signal ext. The Vbb pump operates in synchronization with / CAS (internal column address strobe signal int./CAS).

  Referring to FIG. 3, semiconductor memory device 300 includes a memory cell array 113 divided into two banks B1 and B2, an external column address strobe signal ext. / CAS (hereinafter abbreviated as ext.CAS) to the internal column address strobe signal int. / CAS (hereinafter abbreviated as int.CAS) CAS buffer circuit 303, and int. Clock generating circuit 305 for generating a clock signal CLK2 synchronized with / CAS, ext. Int. BA, int. Address buffer 107 that outputs / BA and Vbb pumps 109 and 111 that generate substrate voltage Vbb are included.

  The output node of the CAS buffer circuit 303 is connected to the input node of the clock generation circuit 305, and the output node of the clock generation circuit 305 is connected to the Vbb pumps 109 and 111. Of the two output nodes of the address buffer 107, int. The output node from which BA is output is sent to the bank B1 and the Vbb pump 109 in the memory cell array 113, int. The output node from which / BA is output is connected to the bank B2 and the Vbb pump 111 in the memory cell array 113. A Vbb output node N1 for outputting Vbb of each of the Vbb pumps 109 and 111 is connected to the banks B1 and B2.

  When there are a plurality of banks, each of the output nodes of the address buffer 107 is connected to a bank corresponding to the internal bank address signal output from the output node.

  In FIG. 3, CAS buffer circuit 303 is inputted from the outside. ext / CAS is int. / CAS, int. / CAS is output to the clock generation circuit 305. In the clock generation circuit 305, the int. / CAS based on int. A clock signal CLK2 synchronized with / CAS is generated and input to the Vbb pumps 109 and 111.

  On the other hand, ext. When BA is input, the int. BA is supplied to the Vbb pump 109, int. / BA is sent to the Vbb pump 111. These int. BA, int. In response to / BA, Vbb pump 109 or 111 operates.

  The Vbb pump 109 (, 111) is the same as that shown in FIG.

  int. BA, int. / BA is input to the NAND gate 201, int. When the clock signal CLK2 changes from L level to H level in synchronization with / CAS, the output of the NAND gate 201 changes from H level to L level, and the voltage of the other electrode of the capacitor Cp changes from -Vthp to -Vcc-Vthp (= Vbb). ), The substrate voltage Vbb is generated.

  That is, when bank B1 is activated, ext. BA becomes H level and is input to the address buffer 107. The int. BA sends Vbb pump 109 with L level int. / BA is output to the Vbb pump 111. And this H level int. BA and int. The Vbb pump 109 is operated by the clock signal CLK2 synchronized with / CAS, and the substrate voltage Vbb is supplied to the bank B1.

  When bank B2 is activated, ext. BA becomes L level and is input to the address buffer 107. The int. BA sends Vbb pump 109 to H level int. / BA is output to the Vbb pump 111. And this H level int. / BA and int. The Vbb pump 111 is operated by the clock signal CLK2 synchronized with / CAS, and the substrate voltage Vbb is supplied to the bank B2.

  As described above, since each bank has a Vbb pump, even if the switching from the bank to another bank is shorter than the response time of the Vbb pump, the stable Vbb level is maintained regardless of the number of operating banks. An internal voltage supply circuit capable of supplying a voltage to a bank based on an input of a column address signal can be provided.

(3) Embodiment 3
FIG. 4 is a block diagram showing a configuration of the semiconductor memory device 400 according to the third embodiment of the present invention. Referring to FIG. 4, semiconductor memory device 400 includes memory cell array 113 divided into two banks B1 and B2, ext. / RAS int. RAS buffer circuit 103 for converting to / RAS, RAS buffer circuit 103, int. / RAS generating clock signal CLK2 synchronized with RAS, ext. Int. BA, int. Address buffer 107 for outputting / BA and Vpp pumps 409 and 411 for generating boosted voltage Vpp are included.

  The output node of the RAS buffer circuit 103 is connected to the input node of the clock generation circuit 105, and the output node of the clock generation circuit 105 is connected to the Vpp pumps 409 and 411. Of the two output nodes of the address buffer 107, int. The output node from which BA is output is sent to the bank B1 in the memory cell array 113 and the Vpp pump 409, int. The output node from which / BA is output is connected to the bank B 2 and the Vpp pump 411 in the memory cell array 113. Vpp output nodes N2 for outputting Vbb of Vpp pumps 209 and 411 are both connected to banks B1 and B2.

  When there are a plurality of banks, each of the output nodes of the address buffer 107 is connected to a bank corresponding to the internal bank address signal output from the output node.

  In FIG. 4, ext. / RAS int. The signal is converted into / RAS and output to the clock generation circuit 105. In the clock generation circuit 105, the int. / RAS based on int. A clock signal CLK1 synchronized with / RAS is generated. The clock signal CLK1 is input to the Vpp pumps 409 and 411.

  On the other hand, ext. When BA is input, the int. BA is supplied to the Vpp pump 409, int. / BA is output to the Vpp pump 411. These int. BA, int. In response to / BA, Vpp pump 409 or 411 operates.

  FIG. 5 is a circuit diagram showing an example of the Vpp pump 409 (, 411) of FIG. Referring to FIG. 5, Vpp pump 409 (, 411) includes an AND gate 501, a capacitor Cp, and NMOS transistors 505 and 507.

  The output node of the AND gate 501 is connected to one electrode of the capacitor Cp. The source electrode and gate electrode of the NMOS transistor 507 are connected to the Vcc power source. The source electrode and gate electrode of the NMOS transistor 505 are connected to the drain electrode of the NMOS transistor 507 and the other electrode of the capacitor Cp. The drain electrode of NMOS transistor 505 is connected to Vpp output node N2 for outputting boosted voltage Vpp.

  The AND gate 501 receives the clock signal CLK1 generated by the clock generation circuit 105 and the internal bank address signal from the address buffer 107 (int.BA for the Vpp pump 409 and int./BA for the Vpp pump 411). Entered.

  The internal bank address signal (int.BA or int./BA) is input to the AND gate 501 and int. When the clock signal CLK1 changes from L level to H level in synchronization with / RAS, the output of the AND gate 501 changes from L level to H level, and the voltage of the other electrode of the capacitor Cp changes from Vcc-Vthn to 2Vcc-Vthn (= Vpp). ) To generate a boosted voltage Vpp. Here, Vcc is the power supply voltage level, and Vthn is the threshold voltage of the NMOS transistor.

  That is, when bank B1 is activated, ext. BA becomes H level and is input to the address buffer 103. The int. BA sends Vpp pump 409 to L level int. / BA is output to the Vpp pump 411. And int. The Vpp pump 409 operates in response to the clock signal CLK1 synchronized with / RAS, and the boosted voltage Vpp is supplied to the bank B1.

  When bank B2 is activated, ext. BA becomes L level and is input to the address buffer 107. The int. BA is connected to the Vpp pump 409 at the H level int. / BA is output to the Vpp pump 411. And int. The Vpp pump 411 is operated by the clock signal CLK1 synchronized with / RAS, and the boosted voltage Vpp is supplied to the bank B2.

  As described above, since each bank has a Vpp pump, even if the switching from the bank to another bank becomes shorter than the response time of the Vpp pump, the stable Vpp level is maintained regardless of the number of operating banks. An internal voltage supply circuit capable of supplying a voltage to a bank based on an input of a row address signal can be provided.

(4) Embodiment 4
FIG. 6 is a block diagram showing a configuration of the semiconductor memory device 900 according to the fourth embodiment of the present invention. In the third embodiment, ext. Although the operation of the Vpp pump is synchronized with RAS (int./RAS), in this embodiment, ext. The Vpp pump operates in synchronization with / CAS (int./CAS).

  6, semiconductor memory device 900 includes a memory cell array 113 divided into two banks B1 and B2, a CAS buffer circuit 303, an int. Clock generation circuit 305 for generating a clock signal CLK2 synchronized with / CAS, ext. Int. BA, int. Address buffer 107 that outputs / BA and Vpp pumps 409 and 411 that generate substrate voltage Vpp are included.

  The output node of the CAS buffer circuit 303 is connected to the input node of the clock generation circuit 305, and the output node of the clock generation circuit 305 is connected to the Vpp pumps 409 and 411. Of the two output nodes of the address buffer 107, int. The output node from which BA is output is sent to the bank B1 in the memory cell array 113 and the Vpp pump 409, int. The output node from which / BA is output is connected to the bank B2 in the memory cell array 113 and the Vpp pump 411. A Vpp output node N2 for outputting Vpp of each of the Vpp pumps 409 and 411 is connected to the banks B1 and B2.

  When there are a plurality of banks, each of the output nodes of the address buffer 107 is connected to a bank corresponding to the internal bank address that it outputs.

  In FIG. 6, the CAS buffer circuit 303 is inputted from the outside. ext / CAS is int. / CAS, int. / CAS is output to the clock generation circuit 305. In the clock generation circuit 305, the int. / CAS based on int. A clock signal CLK2 synchronized with / CAS is generated and input to Vpp pumps 409 and 411.

  On the other hand, ext. When BA is input, the int. BA is supplied to the Vpp pump 409, int. / BA is sent to the Vpp pump 411. These int. BA, signal int. In response to / BA, Vpp pump 409 or 111 operates.

  The Vpp pump 409 (, 411) is the same as that shown in FIG.

  int. BA, int. / BA is input to the NAND gate 201, int. When the clock signal CLK2 changes from L level to H level in synchronization with / CAS, the output of the NAND gate 201 changes from H level to L level, and the voltage of the other electrode of the capacitor Cp changes from Vcc-Vthn to 2Vcc-Vthn (= Vpp). ) To generate a boosted voltage Vpp.

  That is, when bank B1 is activated, ext. BA becomes H level and is input to the address buffer 107. The int. BA sends Vpp pump 409 to L level int. / BA is output to the Vpp pump 411. And this H level int. BA and int. The Vpp pump 409 operates in response to the clock signal CLK2 synchronized with / CAS, and the boosted voltage Vpp is supplied to the bank B1.

  When bank B1 is activated, ext. BA becomes L level and is input to the address buffer 107. The int. BA is connected to the Vpp pump 409 at the H level int. / BA is output to the Vpp pump 411. And this H level int. / BA and int. The Vpp pump 411 operates in response to the clock signal CLK2 synchronized with / CAS, and the boosted voltage Vpp is supplied to the bank B2.

  As described above, since each bank has a Vbb pump, even if the switching from the bank to another bank is shorter than the response time of the Vbb pump, the stable Vbb level is maintained regardless of the number of operating banks. An internal voltage supply circuit capable of supplying a voltage to a bank based on an input of a column address signal can be provided.

(5) Embodiment 5
FIG. 7 is a block diagram showing a configuration of the semiconductor memory device 600 according to the fourth embodiment of the present invention. Referring to FIG. 7, semiconductor memory device 600 includes a memory cell array 113 divided into two banks B1 and B2, ext. / RAS int. RAS buffer circuit 103 for converting to / RAS, int. / RAS generating clock signal CLK1 synchronized with RAS, ext. Int. BA, int. / BA output address buffer 107, internal power supply voltage int. VDC (voltage down converter) circuits 609 and 611 for generating Vcc.

  The output node of the RAS buffer circuit 103 is connected to the input node of the clock generation circuit 105, and the output node of the clock generation circuit 105 is connected to the VDC circuits 609 and 611. Of the two output nodes of the address buffer 107, int. The output node to which BA is output is sent to the bank B1 in the memory cell array 113 and the VDC circuit 609, int. The output node from which / BA is output is connected to the bank B2 in the memory cell array 113 and the VDC circuit 611. Each of the VDC circuits 609 and 611 has an int. Int. For outputting Vcc. Vcc output node N3 is connected to banks B1 and B2.

  When there are a plurality of banks, each of the output nodes of the address buffer 107 is connected to a bank corresponding to the internal bank address that it outputs.

  In FIG. 7, the RAS buffer circuit 103 uses ext. / RAS is int. The signal is converted into / RAS and output to the clock generation circuit 105. In the clock generation circuit 105, the int. A clock signal CLK1 synchronized with / RAS is generated. The clock signal CLK1 is input to the VDC circuits 609 and 611.

  On the other hand, ext. When BA is input, the address buffer 107 stores int. BA to the VDC circuit 609, int. / BA is output to the VDC circuit 611. These int. BA, int. VDC circuits 609 and 611 operate in response to / BA.

FIG. 8 is a diagram illustrating an example of the VDC circuit 609 (, 611) of FIG.
Referring to FIG. 8, VDC circuit 609 (611) includes an AND gate 501, a current mirror type width circuit 701, and a PMOS transistor 703.

  The differential width circuit 701 further includes NMOS transistors 1000, 1001, 1002, and PMOS transistors 1003, 1004.

  In the VDC circuit 609 (, 611), the source electrode of the PMOS transistor 703 is ext. The drain electrode is connected to int. The gate electrode is connected to the output node of the differential amplifier 701. The gate electrode is connected to the Vcc output node N3.

  The AND gate 501 receives the clock signal CLK1 output from the clock generation circuit 105 and the internal bank address signal (int.BA or int.BA) output from the address buffer 107, and its output node is The NMOS transistor 1000 in the differential amplifier circuit 701 is connected to the gate electrode.

  A preset reference voltage Vref is input to the gate electrode of the NMOS transistor 1001. The output node of the differential amplifier circuit 701 is connected to the gate electrode of the PMOS transistor 703. When an L level voltage is applied, the external power supply voltage ext. Internal power supply voltage int. Vcc is supplied from the drain electrode of the PMOS transistor 703 to int. This is supplied to the Vcc output node N3. This internal power supply voltage int. Vcc is fed back to the NMOS transistor 1002 in the differential amplifier circuit 701 and tries to have the same potential as the reference voltage Vref. The NMOS transistor 1000 is turned on when both the clock signal CLK1 input to the AND gate 501 and the internal bank address signal are at the H level. Therefore, the VDC circuit 609 (, 611) is activated and operates when the NMOS transistor 1000 is turned on.

  That is, when bank B1 is activated, ext. BA becomes H level and is input to the address buffer 107. The int. BA is in the VDC circuit 609 and the L level int. / BA is output to the VDC circuit 611. And this H level int. BA and int. VDC circuit 609 operates in response to clock signal CLK1 synchronized with / RAS, and internal power supply voltage int. Vcc is supplied.

  When bank B2 is activated, ext. BA becomes L level and is input to the address buffer 107. The int. BA is in the VDC circuit 609 and the H level int. / BA is output to the VDC circuit 611. And int. VDC circuit 609 operates in response to clock signal CLK1 synchronized with / RAS, and internal power supply voltage int. Vcc is supplied.

  As described above, since each bank has a VDC circuit, even if the switching from the bank to another bank is shorter than the response time of the VDC circuit, a stable internal power supply voltage is maintained regardless of the number of operating banks. Can be supplied to the bank based on the input of the row address signal.

(6) Embodiment 6
FIG. 9 is a block diagram showing a configuration of the semiconductor memory device 800 according to the fifth embodiment of the present invention. The semiconductor memory device 400 according to the fourth embodiment includes ext. Although the operation of the VDC pump is synchronized with RAS (int./RAS), this embodiment is ext. The VDC circuit operates in synchronization with CAS ((int./CAS).

  Referring to FIG. 9, semiconductor memory device 800 includes a memory cell array 113 divided into two banks B1 and B2, ext. / RAS int. CAS buffer 303 for converting to / RAS, int. A clock generation circuit 305 that generates a clock signal CLK2 synchronized with CAS; Int. BA, int. / BA output address buffer 107, internal power supply voltage int. VDC circuits 609 and 611 for generating Vcc.

  The output node of the CAS buffer circuit 303 is connected to the input node of the clock generation circuit 305, and the output node of the clock generation circuit 305 is connected to the VDC circuits 609 and 611. Of the two output nodes of the address buffer 107, int. The output node to which BA is output is sent to the bank B1 in the memory cell array 113 and the VDC circuit 609, int. The output node from which / BA is output is connected to the bank B2 in the memory cell array 113 and the VDC circuit 611. Each of the VDC circuits 609 and 611 is int. Int. For outputting Vcc. Vcc output node N3 is connected to banks B1 and B2.

The VDC circuits 609 and 611 are the same as those shown in FIG.
When there are a plurality of banks, each of the output nodes of the address buffer 107 is connected to a bank corresponding to the internal bank address that it outputs.

  In FIG. 9, the CAS buffer circuit 303 uses ext. / CAS is int. / CAS and is output to the clock generation circuit 305. In the clock generation circuit 305, the int. / CAS based on int. Clock signal CLK2 synchronized with / RAS is generated. This clock signal CLK2 is input to the Vpp pumps 609 and 611.

  On the other hand, ext. When BA is input, the address buffer 107 stores int. BA to the VDC circuit 609, int. / BA is output to the VDC circuit 611. These int. BA, int. VDC circuits 609 and 611 operate in response to / BA.

  That is, when bank B1 is activated, ext. BA becomes H level and is input to the address buffer 107. The int. BA is in the VDC circuit 609 and the L level int. / BA is output to the VDC circuit 611. And int. VDC circuit 609 operates in response to clock signal CLK2 synchronized with / CAS, and internal power supply voltage int. Vcc is supplied.

  When bank B2 is activated, ext. BA becomes L level and is input to the address buffer 107. The int. BA is in the VDC circuit 609 and the H level int. / BA is output to the VDC circuit 611. And int. VDC circuit 611 operates in response to clock signal CLK2 synchronized with / CAS, and internal power supply voltage int. Vcc is supplied.

  As described above, since each bank has a VDC circuit, a stable internal power supply voltage can be obtained regardless of the number of operating banks even when switching from the bank to another bank is shorter than the response time of the VDC circuit. An internal voltage supply circuit that can supply a bank based on the input of a column address signal can be provided.

(7) Embodiment 7
FIG. 10 is a block diagram showing a configuration of the semiconductor memory device 1000 according to the seventh embodiment of the present invention. Referring to FIG. 10, semiconductor memory device 1000 includes RAS buffer 103, address buffer 107, memory cell array 113 divided into a plurality of banks, and int. A VDC circuit 1001 for supplying Vcc and an activation signal generation circuit 1003 for generating an activation signal for activating the VDC circuit 1001 are provided.

  Hereinafter, for simplicity, the case where the memory cell array 113 is divided into two banks B1 and B2 will be described. Bank B1 is int. Activated when BA is at L level, bank B2 is int. It is activated when BA is at H level.

  Memory cell array 113 is connected to address buffer 107 and internal power supply voltage output node (hereinafter referred to as int.Vcc node) N3 of VDC circuit 1001. The activation signal generation circuit 1003 is connected to the address buffer 107 and the RAS buffer circuit 103. The VDC circuit 1001 is connected to the activation signal generation circuit 1003.

  The activation signal generation circuit 1003 receives a clock signal CLK3 and a precharge signal / PRE for precharging an inactivated bank from the outside. / RAS is input. Based on these signals, activation signal generation circuit 1003 outputs activation signals / ACT1, / ACT2 for activating VDC circuit 1001.

  11 and 12 are timing charts showing activation signals generated by the activation signal generation circuit 1003 in the semiconductor memory device 1000 of FIG.

  FIG. 11 is a timing chart when the banks B1 and B2 are activated separately. On the other hand, FIG. 12 is a timing chart when the banks B1 and B2 are simultaneously activated. First, the operation of the activation signal generation circuit 1003 will be described with reference to FIG.

  At the rising edge of the clock signal CLK3 at time t0, the L.S. / RAS and the address buffer 107 from the L level int. When BA is taken into activation signal generation circuit 1003, activation signal / ACT1 attains an L level. On the other hand, activation signal / ACT2 remains constant at the H level.

  At the rising edge of the clock signal CLK3 at time t1, the L level int. / RAS, H level int. When BA and precharge signal / PRE for precharging the bank from the outside are taken into activation signal generation circuit 103, bank B1 is deactivated, and activation signal / ACT1 becomes H level, Access to bank B1 is completed and precharging is performed.

  Further, at the rising edge of the clock signal CLK3 at the time t2, the int. / RAS and H level int. When BA (that is, L level int./BA) is taken into activation signal generation circuit 1003, activation signal / ACT2 becomes L level. On the other hand, activation signal / ACT1 remains constant at the H level.

  At the rising edge of clock signal CLK3 at time t4, L level int. / RAS, address buffer 107 is at L level int. When precharge signal / PRE is taken into activation signal generation circuit 1003 from BA and the outside, bank B2 is deactivated, activation signal / ACT2 becomes H level, and access to bank B2 is completed. Precharge is performed.

Next, the operation of the activation signal generation circuit 1003 will be described with reference to FIG.
At the falling edge of the clock signal CLK3 at time t0, the RAS buffer circuit 103 outputs an int. / RAS and the address buffer 107 from the L level int. When BA is taken into activation signal generation circuit 1003, bank B1 is activated and activation signal / ACT1 attains an L level.

  Subsequently, at the falling edge of the clock signal CLK3 at time t1, the RAS buffer circuit 103 sets the L level int. / RAS and address buffer 107 from H level int. When BA is taken into activation signal generation circuit 1003, bank B2 is activated and activation signal / ACT2 attains an L level.

  When banks B1 and B2 are activated at the same time, the number of circuits that operate to access memory cells is larger than when access is made in only one bank. Therefore, a VDC circuit as shown below that operates in accordance with the activation signals / ACT1, / ACT2 is provided.

  FIG. 13 is a circuit diagram showing a VDC circuit 1300 which is an example of the VDC circuit 1001 of FIG. Referring to FIG. 13, VDC circuit 1300 is activated by an activation signal / ACT1 and int. The internal power supply voltage output circuit 1301 for outputting Vcc and the activation signal / ACT2 are activated by int. And an internal power supply voltage output circuit 1303 for outputting Vcc. The internal power supply voltage output circuit 1301 and the internal power supply voltage output circuit 1303 have the same circuit configuration.

  The internal power supply voltage output circuit 1301 includes a differential amplifier 1305, PMOS transistors 1307 and 1309, and an inverter 1311.

  The differential amplifier 1305 further includes PMOS transistors 1313 and 1314 and NMOS transistors 1315 to 1317.

  The reference voltage Vref is applied to the inverting input terminal of the differential amplifier, and the int. The voltage of the Vcc output node N3 is fed back, and the output terminal is connected to the gate electrode of the PMOS transistor 1307 and the drain electrode of the PMOS transistor 1309. The source electrode of the PMOS transistor 1307 is ext. The drain electrode is connected to the internal power supply voltage output node N1.

  The source electrode of the PMOS transistor 1313 is ext. Connected to Vcc, the gate electrode is connected to the gate electrode and drain electrode of the PMOS transistor 1314, and the drain electrode is connected to the output terminal. The source electrode of the PMOS transistor 1314 is ext. Connected to Vcc. The reference voltage Vref is input to the gate electrode of the NMOS transistor 1315, and the source electrode is connected to the drain electrode of the NMOS transistor 1317. The gate electrode of the NMOS transistor 1316 is connected to the internal power supply voltage output node N 1, and the source electrode is connected to the drain electrode of the NMOS transistor 1317. The drain electrode of the NMOS transistor 1317 is grounded, and the activation signal / ACT1 is input to the gate electrode via the inverter.

  The output node of internal power supply voltage output circuit 1301 and the output node of internal power supply voltage output circuit 1303 are int. Vcc output node N3 and int. The Vcc output node N3 is connected to the memory cell array 113.

  When the bank B1 is not activated, the activation signal / ACT1 is at the H level, and the NMOS transistor 1317 in the differential amplifier 1305 is on. Therefore, the differential amplifier 1305 does not operate, and the PMOS transistor 1309 Is turned on, the ext .. through the PMOS transistor 1309 is connected to the gate electrode of the PMOS transistor 1307. Since Vcc is applied and the PMOS transistor 1307 is off, int. Vcc output node N3 receives int. Vcc is not issued.

  When the bank B1 is activated and the activation signal / ACT1 becomes L level, the NMOS transistor 1317 in the differential amplifier 1305 is turned on and the differential amplifier 1305 operates. Further, the PMOS transistor 1309 is turned off, and the gate electrode of the PMOS transistor 1307 is ext. Vcc is not applied, and the voltage of the output terminal of the differential amplifier 1305 is applied. The PMOS transistor 1307 is controlled by this voltage. Based on Vcc, int. Vcc is int. Output to Vcc output node N3.

  Similarly to the internal power supply voltage output circuit 1301, the internal power supply voltage output circuit 1303 has the activation signal / ACT2 at the H level, the NMOS transistor 1317 is turned off, and the PMOS transistor 1309 is turned on when the bank B2 is not activated. On, int. Vcc output node N3 receives int. When Vcc is not output and bank B2 is activated, activation signal / ACT2 becomes L level, and ext. Based on Vcc, int. Vcc is int. Output to Vcc output node N3.

  Therefore, in semiconductor memory device 1300 according to the seventh embodiment of the present invention, since the VDC circuit has an internal power supply voltage output circuit for each bank, switching from one bank to another bank is the response time of the internal power supply voltage output circuit. Even if it becomes shorter, it is possible to stably supply the internal power supply voltage to the bank.

  When a plurality of banks are activated simultaneously, the internal power supply voltage output circuit corresponding to each bank operates, so that the internal power supply voltage supply capability of the VDC circuit is improved and a stable internal power supply voltage is supplied. Is possible.

(8) Embodiment 8
The semiconductor memory device according to the eighth embodiment of the present invention is obtained by replacing the VDC circuit 1001 in the semiconductor memory device 1000 according to the seventh embodiment shown in FIG. 10 with a VDC circuit 1400 shown in FIG.

  Also in this embodiment, for simplicity, the case where the memory cell array 113 is divided into two banks B1 and B2 will be described.

  FIG. 14 is a circuit diagram showing a VDC circuit 1400 included in the semiconductor memory device according to the eighth embodiment of the present invention. Referring to FIG. 14, VDC circuit 1400 includes a current mirror type differential amplifier 1305, a NOR circuit 1406, an int. Voltage output circuits 1415 and 1416 for outputting a voltage to the Vcc output node N3.

  The differential amplifier 1305 further includes PMOS transistors 1413 and 1414 and NMOS transistors 1315 to 1317.

  The voltage output circuit 1415 further includes PMOS transistors 1407 and 1408, and the voltage output circuit 1416 further includes PMOS transistors 1409 and 1410.

  The voltage generation circuit 1415 supplies int. Vcc is a circuit for outputting Vcc, and the voltage generation circuit 1416 supplies int. This is a circuit for outputting Vcc.

  In the differential amplifier 1305, the source electrode of the PMOS transistor 1313 is ext. The drain electrode is connected to the output terminal, and the gate electrode is connected to the gate electrode and the drain electrode of the PMOS transistor 1314. The source electrode of the PMOS transistor 1314 is ext. Connected to Vcc. The drain electrode of the NMOS transistor 1315 is connected to the output terminal, and the reference voltage Vref is applied to the gate electrode. The drain electrode of the NMOS transistor 1316 is connected to the drain electrode of the NMOS transistor 1317, the source electrode is connected to the drain electrode of the NMOS transistor 1317, and the gate electrode is int. Vcc output node N3 is connected. The source electrode of the NMOS transistor 1317 is grounded, and the gate electrode is connected to the output node of the NOR circuit 1406. An activation signal / ACT1 is input to one input node of the NOR circuit 1406, and an activation / ACT2 is input to the other input node.

  In the voltage output circuit 1415, the source electrode of the PMOS transistor 1407 is ext. The drain electrode is connected to the Vcc, the drain electrode is connected to the source electrode of the PMOS transistor 1408, and the activation signal / ACT1 is input to the gate electrode. The drain electrode of the PMOS transistor 1408 is int. Connected to the Vcc output node N3, the gate electrode is connected to the output terminal of the differential amplifier 1305.

  In the voltage output circuit 1416, the source electrode of the PMOS transistor 1409 is ext. Connected to Vcc, the drain electrode is connected to the source electrode of the PMOS transistor 1410, and the activation signal / ACT2 is input to the gate electrode. The drain electrode of the PMOS transistor 1410 is int. It is connected to the Vcc output node N3 and is connected to the output terminal of the gate electrode differential amplifier 1305.

  When both banks B1 and B2 are not activated, activation signals / ACT1 and ACT2 are both at H level, so that the output of NOR circuit 1406 is at L level, and NMOS transistor 1317 in differential amplifier 1305 is off. In this state, the differential amplifier 1305 does not operate. Since the PMOS transistors 1407 and 1409 are also off, int. Vcc output node N3 has int. Vcc is not output.

  When only one bank, for example, bank B1, is activated, activation signal / ACT1 is at L level and / ACT2 is at H level, so that the output of NOR circuit 1406 is at L level, and NMOS transistor 1317 has The differential amplifier 1305 is turned on and operates. Further, since the PMOS transistor 1407 is turned on, ext .. is transmitted via the PMOS transistor 1408 controlled by the output of the differential amplifier 1305. Int. For supplying to the bank B1 based on Vcc. Vcc is int. Generated at Vcc output node N3.

  When only bank B2 is activated, activation signal / ACT2 becomes L level and activation signal / ACT1 becomes H level, NMOS transistor 1317 and PMOS transistor 1409 are turned on, and ext. Int. For supplying to the bank B2 via the PMOS transistor 1410 controlled by the output of the differential amplifier 1305 based on Vcc. Vcc is int. Generated at the Vcc output node.

  Further, when both banks B1 and B2 are activated, activation signals / ACT1 and / ACT2 both become L level, NMOS transistor 1317 and two PMOS transistors 1407 and 1409 are turned on, and the differential amplifier Through the PMOS transistors 1408 and 1410 controlled by the output of 1305. Int. For supplying the banks B1 and B2 to the Vcc output node N3. Vcc is generated.

  Therefore, when both banks are activated, int. Is compared to when only one bank is activated. Since the supply capacity of Vcc is improved, stable int. Vcc can be supplied.

  As described above, the semiconductor memory device according to the eighth embodiment of the present invention is int. Since the Vcc supply capacity changes, the int. Vcc can be supplied.

  In the case where the memory cell array is divided into a plurality of banks, the voltage operated by the activation signal and the output of the differential amplifier 1305 is the same as the voltage generation circuits 1415 and 1416 provided corresponding to the banks B1 and B2. The generation circuit may be connected to the internal voltage output node N3.

  FIG. 15 is a circuit diagram showing a VDC circuit 1500 which is an improved example of the VDC circuit 1400 of FIG.

  Referring to FIG. 15, VDC circuit 1500 is obtained by replacing NOR circuit 1406 and NMOS transistor 1317 of VDC circuit 1400 of FIG. 14 with NMOS transistors 1501 and 1502 and inverters 1503 and 1504.

  The drain electrodes of the NMOS transistors 1501 and 1502 are connected to the source electrode of the NMOS transistor 1315, and a ground voltage is applied to the source electrodes. An activation signal / ACT1 is input to the inverter 1503, and the output of the inverter 1503 is applied to the gate electrode of the NMOS transistor 1501. The activation signal / ACT2 is input to the inverter 1504, and the output of the inverter 1504 is applied to the gate electrode of the NMOS transistor 1502.

  For example, when bank B1 is activated, activation signal / ACT1 becomes L level, NMOS transistor 1501 is turned on, and differential amplifier 1305 has a predetermined voltage gain determined by NMOS transistor 1501.

  When bank B2 is activated, activation signal / ACT2 becomes L level, NMOS transistor 1502 is turned on, and differential amplifier 1305 has a predetermined voltage gain determined by NMOS transistor 1502.

  When both banks B1 and B2 are activated, activation signals / ACT1 and / ACT2 both become L level and NMOS transistors 1501 and 1502 are turned on, so that differential amplifier 1305 includes NMOS transistors 1501 and 1502. Is a predetermined voltage gain determined by. In addition, the voltage gain at this time is larger than that when only one bank is activated.

  As described above, if VDC circuit 1500 is used in the semiconductor memory device according to the eighth embodiment of the present invention, in addition to the effect of using VDC circuit 1400, the differential amplifier corresponding to the activated bank is used. Since the voltage gain can be changed, int. It becomes possible to adjust the change in the supply capacity of Vcc.

(9) Embodiment 9
Next, a plurality of banks in the memory cell array are grouped to form several groups, and VDC circuits corresponding to these groups are int. An example in which Vcc is supplied is shown below. Here, a case where the memory cell array is divided into four banks will be described as an example.

  FIG. 16 is a block diagram showing a configuration of main part 1600 of the semiconductor memory device according to the ninth embodiment of the present invention. The semiconductor memory device according to the ninth embodiment includes the RAS buffer 103, the address buffer 107, and the activation signal generation circuit 1003 (not shown) as in the semiconductor memory device 1000 of FIG. 10 according to the seventh embodiment. Activation signals / ACT1 to / ACT4 are output by activation signal generation circuit 1003.

  Referring to FIG. 16, main portion 1600 of the semiconductor memory device includes memory cell array 113 divided into four banks B1 to B4, and int. A VDC circuit 1610 for supplying Vcc and AND circuits 1605 and 1607 are provided.

  VDC circuit 1610 further includes internal power supply voltage output circuits 1601 and 1603. VDC circuit 1610 provided with internal power supply voltage output circuits 1601 and 1603 is a circuit similar to VDC circuit 1300 provided with internal voltage output circuits 1301 and 1303 in FIG. 13 of the seventh embodiment.

Banks B1 and B2 are group G1, and banks B3 and B4 are group G2.
One input node of AND circuit 1605 receives an activation signal / ACT1 that becomes L level when bank B1 is activated, and the other input node receives L when bank B2 is activated. The activation signal / ACT2 to be level is input. One input node of AND circuit 1607 receives activation signal / ACT3 that is at L level when bank B3 is activated, and the other input node receives L when bank B4 is activated. The activation signal / ACT4 to be level is input.

  When at least one of the banks B1 and B2 in the group G1 is activated, the control signal / ACTG1 output from the AND circuit 1605 becomes L level. Internal power supply voltage output circuit 1601 is exactly the same as the circuit in which this control signal / ACTG1 is input to internal power supply voltage output circuit 1301 in FIG. 13 instead of activation signal / ACT1, so that control signal / ACTG1 is at the L level. At int. Vcc is generated and supplied to banks B1 and B2. At that time, the banks B3 and B4 are precharged.

  When at least one of the banks B3 and B4 in the group G2 is activated, the control signal / ACTG2 output from the AND circuit 1607 becomes L level. Internal power supply voltage output circuit 1603 is exactly the same as the circuit in which this control signal / ACTG2 is input to internal power supply voltage output circuit 1301 of FIG. 13 instead of activation signal / ACT1, so that control signal / ACTG2 is at the L level. At int. Vcc is generated and supplied to banks B3 and B4. At that time, the banks B1 and B2 are precharged.

  Therefore, in the semiconductor memory device according to the ninth embodiment of the present invention, a plurality of banks are divided into several groups, and an internal voltage output circuit is provided for each group. Even if the switching to the internal bank becomes shorter than the response time of the internal power supply voltage output circuit, it is possible to supply a stable internal power supply voltage.

  Further, when the number of bank divisions in the memory cell array is large, even if the bank to be accessed is changed, it is not necessary to switch the internal power supply voltage output circuit within the same group, so that a stable internal power supply voltage is supplied. It is possible.

(10) Embodiment 10
FIG. 17 is a block diagram showing a configuration of main part 1700 of the semiconductor memory device according to the tenth embodiment of the present invention. Here, a case where the memory cell array is divided into eight banks B1 to B8 will be described.

  Referring to FIG. 17, main portion 1700 of the semiconductor memory device of the tenth embodiment is divided into eight banks B1 to B8, and includes memory cell array 113, VDC circuits 1701 and 1703, and AND circuits 1605 to 1608. .

  VDC circuits 1701 and 1703 are the same circuits as VDC circuit 1400 of FIG. 14 or VDC circuit 1500 of FIG.

Banks B1 to B4 are group G1, and banks B5 to B8 are group G2.
Activation signals / ACT1- / ACT8 are at L level when banks B1-B8 are activated, respectively.

  The activation signal / ACT1 is input to one input node of the AND circuit 1605, the activation signal / ACT2 is input to the other input node, and its output node is connected to one input node of the VDC circuit 1701. Yes. An activation signal / ACT3 is input to one input node of AND circuit 1606, activation signal / ACT4 is input to the other input node, and its output node is connected to the other input node of VDC circuit 1701. Yes.

  The activation signal / ACT5 is input to one input node of the AND circuit 1607, the activation signal / ACT6 is input to the other input node, and its output node is connected to one input node of the VDC circuit 1703. Yes. An activation signal / ACT7 is input to one input node of AND circuit 1608, activation signal / ACT8 is input to the other input node, and its output node is connected to the other input node of VDC circuit 1703. Yes.

  The output node of the VDC circuit 1701 and the output node of the VDC circuit 1703 are int. Connected to the Vcc output node N3 and connected to the memory cell array 113.

  When at least one of the banks B1 and B2 is activated, the control signal / ACTG11 output from the AND circuit 1605 becomes L level. When at least one of banks B3 and B4 is activated, control signal / ACTG12 output from AND circuit 1606 is at L level.

  VDC circuit 1701 has the same control signals / ACTG11 and / ACTG12 as the circuit input in place of activation signals / ACT1 and ACT2 to VDC circuit 1400 of FIG. When at least one of / ACTG11 and / ACTG12 is at L level, int. Vcc is generated and supplied to the activated bank among the banks B1 to B4. At that time, the other banks are precharged. Further, when both control signal / ACTG11 and control signal / ACTG12 are at the L level (that is, when at least one of banks B1 and B2 and at least one of banks B3 and B4 are activated), the eighth embodiment. Int. Vcc supply capability is improved.

  The group G2 is the same as in the case of the group G1, and when at least one of the banks B5 and B6 is activated, the control signal / ACTG21 output from the AND circuit 1607 becomes L level, and at least one of the banks B7 and B8 Is activated, the control signal / ACTG22 output from the AND circuit 1608 is at the L level.

  The VDC circuit 1703 controls the control signals / ACTG21 and / ACTG22 because they are exactly the same as the circuits input in place of the activation signals / ACT1 and / ACT2 to the VDC circuit 1400 of FIG. When at least one of the signals / ACTG21 and / ACTG22 is at L level, int. Vcc is generated and supplied to the activated bank among the banks B5 to B8. At that time, the other banks are precharged.

  Further, when both control signal / ACTG21 and control signal / ACTG22 are at the L level (that is, when at least one of banks B5 and B6 and at least one of banks B7 and B8 is activated), the eighth embodiment. Int. Vcc supply capability is improved.

  As described above, the semiconductor memory device according to the tenth embodiment of the present invention has a stable internal power supply even when switching from a bank in one group to a bank in another group is shorter than the response time of the VDC circuit. It is possible to supply a voltage. Further, when the number of bank divisions in the memory cell array is large, even if the bank to be accessed is changed, it is not necessary to switch the VDC circuit within the same group, so it is possible to supply a stable internal power supply voltage. It is.

  Furthermore, as in the case of the semiconductor memory device of the eighth embodiment, the internal power supply voltage supply capability of the VDC circuit can be improved according to the number of activated banks.

  Here, as the VDC circuits 1701 and 1703, a circuit similar to the VDC circuit 1500 in FIG. 15 can be used.

(11) Embodiment 11
The int. Of the VDC circuit corresponds to the number of activated banks. An example in which the Vcc supply capability is changed will be described below.

  FIG. 18 is a block diagram showing a configuration of a semiconductor memory device 1800 according to the eleventh embodiment of the present invention.

  Referring to FIG. 18, semiconductor memory device 1800 counts memory cell array 113 divided into four banks B1 and B2, address buffer 107, activation signal generation circuit 103, and the number of activated banks. Counting circuit 1803 and a VDC circuit 1801.

  The memory cell array 113 includes the address buffer 107 and the int. Connected to Vcc output node N3. The activation signal generation circuit 103 is connected to the address buffer 107. Count circuit 1803 is connected to the output node of activation signal generation circuit 103. The VDC circuit 1801 is connected to the output node of the count circuit 1803.

Here, as an example, a case where the banks B1 and B3 are activated will be described.
As described in FIG. 10 of the seventh embodiment, int. / RAS, clock signal CLK3, and int. In response to BA, in activation signal generation circuit 103, L level activation signals / ACT1, / ACT3 corresponding to banks B1, B3 activated, and H level activation signals / ACT2, / ACT4 Are output.

  The count circuit 1803 counts 2 as the number of banks to be activated by the input L level activation signals / ACT1, / ACT3. Count circuit 1803 outputs control signals / CNT1, / CNT2 lowered to L level in correspondence with the number of banks 2 to VDC circuit 1801, and when the number of activated banks is 1, Only CNT1 falls to L level, control signals / CNT1- / CNT3 fall to L level in the case of three, and all control signals / CNT1- / CNT4 fall to L level in the case of four It is done.

  The VDC circuit 1801 has a sufficient number of int. So that Vcc can be supplied. Vcc supply capability is improved.

  FIG. 19 is a circuit diagram showing a VDC circuit 1900 which is an example of the VDC circuit 1801 in FIG.

  Referring to FIG. 19, VDC circuit 1900 includes differential amplifier 1305, NOR circuit 1901, ext. Based on Vcc. Voltage generating circuits 1921 to 1924 for generating and supplying a voltage to Vcc output node N3 are provided.

  The differential amplifier 1305 is the same as the differential amplifier 1305 shown in FIG. 13 and the like, and the output node of the NOR circuit 1901 is connected to the gate electrode of the NMOS transistor 1317 in the differential amplifier 1305.

  The voltage generation circuit 1921 includes PMOS transistors 1903 and 1904, the voltage generation circuit 1922 includes PMOS transistors 1905 and 1906, the voltage generation circuit 1923 includes PMOS transistors 1907 and 1908, and the voltage generation circuit 1924 includes PMOS transistors 1909 and 1910.

  In the voltage generation circuit 1921, the source electrode of the PMOS transistor 1903 is connected to the external power supply node, the drain electrode is connected to the source electrode of the PMOS transistor 1903, and the control signal / CNT1 is input to the gate electrode. The drain electrode of the PMOS transistor 1904 is int. Connected to the Vcc output node N3, the gate electrode is connected to the output node of the differential amplifier 1305.

  In the voltage generation circuit 1922, the source electrode of the PMOS transistor 1905 is connected to the external power supply node, the drain electrode is connected to the source electrode of the PMOS transistor 1905, and the control signal / CNT2 is input to the gate electrode. The drain electrode of the PMOS transistor 1906 is int. Connected to the Vcc output node N3, the gate electrode is connected to the output node of the differential amplifier 1305.

  In the voltage generation circuit 1923, the source electrode of the PMOS transistor 1907 is connected to the external power supply node, the drain electrode is connected to the source electrode of the PMOS transistor 1907, and the control signal / CNT3 is input to the gate electrode. The drain electrode of the PMOS transistor 1908 is int. Connected to the Vcc output node N3, the gate electrode is connected to the output node of the differential amplifier 1305.

  In the voltage generation circuit 1924, the source electrode of the PMOS transistor 1909 is connected to the external power supply node, the drain electrode is connected to the source electrode of the PMOS transistor 1909, and the control signal / CNT4 is input to the gate electrode. The drain electrode of the PMOS transistor 1910 is int. Connected to the Vcc output node N3, the gate electrode is connected to the output node of the differential amplifier 1305.

  Control signals / CNT1 to / CNT4 are input to the NOR circuit 1901. That is, if any one of the banks is activated, the output of the NOR circuit 1901 becomes L level, and the differential amplifier 1305 operates.

  When there are two activated banks as in the above example, the control signals / CNT1, / CNT2 are at L level, / CNT3,. Since CNT4 is at the H level, the PMOS transistors 1903 and 1905 are turned on in the voltage generating circuits 1921 and 1922, and the int. Vcc is int. This is supplied to Vcc output node N3. In the voltage generation circuits 1923 and 1924, since the PMOS transistors 1907 and 1909 are off, no voltage is supplied from the voltage generation circuits 1923 and 1924.

  As described above, the semiconductor memory device 1800 according to the eleventh embodiment of the present invention corresponds to the number of int. Since the supply capability of Vcc changes, a stable internal power supply voltage can be supplied even if the number of banks to be accessed is changed.

  The VDC circuit 1801 in the above example is a circuit applied so that the VDC circuit 1400 of FIG. 14 in the eighth embodiment corresponds to four banks and is operated by the control signals / CNT1 to / CNT4 instead of the activation signals. Similarly, the VDC circuit 1500 of FIG. 15 and the internal power supply circuit 1300 of FIG. 13 of the seventh embodiment are applied, or the semiconductor memory device 1600 of FIG. 16 of the ninth embodiment and the tenth embodiment. 17 using the grouping of the control signals / CNT1 to / CNT4, a suitable int. From the VDC circuit according to the range of the number of banks. It is also possible to supply Vcc, and in addition to the effects of the above-described eleventh embodiment, the same effects as those of the above-described embodiments can be obtained.

(12) Embodiment 12
FIG. 20 is a circuit diagram showing a configuration of semiconductor memory device 2000 according to the twelfth embodiment of the present invention. Here, a case where the memory cell array is divided into two banks will be described as an example.

  Referring to FIG. 20, semiconductor memory device 2000 includes memory cell array 113 divided into two banks B 1 and B 2, and banks B 1 and B 2 in memory cell array 113 with int. Internal power supply voltage output circuits 1301 and 1303 for supplying Vcc, int. Internal power supply lines 2001B1 and 2001B2 for supplying Vcc, ground lines 2003B1 and 2003B2 for supplying a ground voltage to the memory cell array, and a decoupling capacitor 2020 are provided.

  Bank B1 further includes a plurality of memory cells MCn, a plurality of word lines WLn and a plurality of bit line pairs BLn, / BLn, and a plurality of sense amplifiers SAn.

  Internal power supply line 2001B1 is connected to int. Connected to the Vcc output node N3 and connected to a plurality of sense amplifiers SAn in the bank B1. A ground voltage is applied to the 2003B1 through the decoupling capacitor 2020. Memory cell MCn is connected to word line WLn and bit line pair BLn, / BLn, and each of bit line pair BLn, / BLn is connected to a sense amplifier.

  Similarly, the internal power supply line 2001B2 includes the int. Connected to the Vcc output node N3 and connected to a plurality of sense amplifiers SAn in the bank B2. The ground line 2003B2 is connected to the ground line 2003B1 outside the memory cell array 113, and a ground voltage is applied via the decoupling capacitor 2020. Memory cell MCn in bank B2 is also connected to word line WLn and bit line pair BLn, / BLn, and is connected to sense amplifier SAn.

  Here, the internal power supply lines 2001B1 and 2001B2 are not electrically connected to each other inside and outside the memory cell array 113. The ground lines 2003B1 and 2003B2 are also not connected in the memory cell array 113.

  Internal power supply voltage output circuits 1301 and 1303 are exactly the same as internal power supply voltage output circuits 1301 and 1303 of FIG. 13 of the seventh embodiment.

  The internal power supply voltage output circuit 1301 operates in response to the activation signal / ACT1 that becomes L level when the bank B1 is activated. Vcc is supplied to bank B1 via 2001B1. When the bank B2 is activated, the internal power supply voltage output circuit 1303 is operated by the activation signal / ACT2 which becomes L level, and the int. Vcc is supplied to bank B2 via 2001B2.

  In bank B1, internal power supply line 2001B1 is connected to a plurality of sense amplifiers SAn. When data is read from accessed memory cell MCn, the read voltage on bit line pair BLn, / BLn is amplified by sense amplifier SAn. Is done. At this time, current is consumed by the sense amplifier SAn, and if the internal power supply lines 2001B1 and 2001B2 and the ground lines 2003B1 and 2003B2 are electrically connected inside the memory cell array 113, noise will appear in the data read voltage. .

  However, if the internal power supply line and the ground line are completely separated for each bank in the memory cell array 113 as described above, noise is not easily transmitted to other banks.

  Therefore, the semiconductor memory device 2000 according to the twelfth embodiment of the present invention can almost eliminate the occurrence of malfunction caused by the generated noise being transmitted to other activated banks.

(13) Embodiment 13
FIG. 21 is a circuit diagram showing a semiconductor memory device 2100 according to the thirteenth embodiment of the present invention. Referring to FIG. 21, semiconductor memory device 2100 includes memory cell array 113 divided into two banks B1 and B2, VDC circuit 2101 provided corresponding to banks B1 and B2, and int. Internal power supply lines 2001B1 and 2001B2 for supplying Vcc, ground lines 2003B1 and 2003B2 for supplying a ground voltage to the memory cell array 113, and decoupling capacitors 2020 and 2021 are provided.

  Each of banks B1 and B2 includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit line pairs, and a plurality of sense amplifiers for amplifying data read or written in these memory cells. And SAn. Since these connection relationships are the same as those of the semiconductor memory device 2000 of the twelfth embodiment, illustration and description thereof are omitted.

  The VDC circuit 2101 is a circuit similar to either the VDC circuit 1300 of FIG. 13 of the seventh embodiment, the VDC circuit 1400 of FIG. 14 of the eighth embodiment, or the VDC circuit 1500 of FIG.

  The VDC circuit 2101 receives an activation signal / ACT1 that becomes L level when the bank B1 is activated and an activation signal / ACT2 that becomes L level when the bank B2 is activated. Vcc output node N3 is connected to internal power supply lines 2001B1 and 2001B2. Internal power supply lines 2001B1 and 2001B2 are not electrically connected to each other inside memory cell array 113, but are connected again outside memory cell array 113, and the connection node is connected to one electrode of decoupling capacitor 2021. A constant voltage such as a ground voltage or a power supply voltage is applied to the other electrode of the decoupling capacitor 2021.

  The ground lines 2003B1 and 2003B2 are electrically disconnected inside the memory cell array 113 and connected outside the memory cell array 113, as in the case of the semiconductor memory device 2000 of FIG. The decoupling capacitor 2020 is connected to one electrode. The other electrode of the decoupling capacitor 2020 is given a constant voltage such as a ground voltage or a power supply voltage.

  The ground voltage lines 2001B1 and 2001B2 are ideally separated outside the memory cell array 113, but even when this is not possible, the read on the internal power supply lines 2001B1 and 2001B2 can be performed by connecting the decoupling capacitor 2021. Since most of the voltage noise is absorbed by the decoupling capacitor 2021, it is possible to reduce the noise.

  Also in the ground lines 2003B1 and 2003B2, noise on the line is reduced by the decoupling capacitor 2020.

  As described above, in the semiconductor memory device 2100 of the thirteenth embodiment of the present invention, in addition to the effects of the semiconductor memory device of the seventh or eighth embodiment, the internal power supply line and the ground line are connected outside the memory cell array. However, it is possible to prevent the noise on the line during the operation of the sense amplifier or the like from being transmitted to other accessing banks and malfunctioning.

(14) Embodiment 14
FIG. 22 is a circuit diagram showing a semiconductor memory device 2200 according to the fourteenth embodiment of the present invention. Referring to FIG. 22, semiconductor memory device 2200 is similar to semiconductor memory device 1600 of FIG. 16 of the ninth embodiment, in the same manner as semiconductor memory device 2100 of FIG. 21 of the thirteenth embodiment. A decoupling capacitor for reduction is connected.

  Internal power supply lines from the internal power supply voltage output circuits 1601 and 1603 are connected to the banks B1 to B4 in the memory cell array 113 int. The internal power supply lines 2001B1 to 2001B4 for supplying Vcc are branched, and the internal power supply lines 2001B1 to 2001B4 are not electrically connected to each other inside the memory cell array 113 and are electrically connected outside the memory cell array 113. . The ground lines 2003B1 to 2003B4 for supplying a ground voltage to the banks B1 to B4 in the memory cell array 113 are also electrically disconnected from each other inside the memory cell array 113 and electrically connected outside the memory cell array 113. Yes.

  One electrode of a decoupling capacitor 2021 for reducing noise is connected to a connection node outside the memory cell array 113 for the internal power supply lines 2021B1 to 2021B4, and a connection node outside the memory cell array 113 for the ground lines 2003B1 to 2003B4. Is connected to one electrode of a decoupling capacitor 2020 for noise reduction.

  A constant voltage such as a ground voltage or a power supply voltage is applied to the other electrode of the decoupling capacitor 2021. Therefore, similarly to the semiconductor memory device of the thirteenth embodiment, noise on the internal power supply line can be reduced by this decoupling capacitor 2021.

  A constant voltage such as a ground voltage or a power supply voltage is applied to the other electrode of the decoupling capacitor 2020. Therefore, as in the case of the semiconductor memory device of the thirteenth embodiment, the decoupling capacitor 2021 can reduce noise on the ground line.

  For example, when one of the banks B1 and B2 is activated, the internal power supply voltage output circuit 1601 is connected via the corresponding internal power supply line among the internal power supply lines 2001B1 and 2001B2. Vcc is supplied to the corresponding bank. Alternatively, when one of the banks B3 and B4 is activated, the internal power supply voltage output circuit 1603 is connected via the corresponding internal power supply line among the internal power supply lines 2001B3 and 2001B4 to int. Vcc is supplied to the corresponding bank. At this time, since the internal power supply lines 2001B1 to 2001B4 are not electrically connected to each other, the decoupling capacitor 2021 can reduce noise due to the banks.

  Further, when there are a plurality of banks, it is possible to reduce noise interference of data read voltages between groups by providing four banks as one group and providing one circuit per group.

  As described above, in the semiconductor memory device 2200 according to the fourteenth embodiment of the present invention, in addition to the effects of the semiconductor memory device according to the ninth embodiment, the bank or group of banks in which noise such as when the sense amplifier operates is being accessed is different. It is possible to prevent malfunctions from being transmitted.

(15) Embodiment 15
FIG. 23 is a block diagram showing a semiconductor memory device 2300 according to the fifteenth embodiment of the present invention. The semiconductor memory device 2300 is obtained by applying the semiconductor memory device 2100 of the thirteenth embodiment to the semiconductor memory device 1700 of the tenth embodiment.

  That is, int. Internal power supply lines 2001B1 to 2001B8 for supplying Vcc and ground lines 2003B1 to 2003B8 for supplying ground voltage are not electrically connected to each other inside memory cell array 113. Further, outside the memory cell array 113, the internal power supply lines 2021B to 2021B4 in the banks B1 to B4 of the group G1 are connected outside the memory cell 113 and connected to the decoupling capacitor 2021G1. Internal power supply lines 2021G5 to 2021G8 in the banks B5 to B8 of the group G2 are connected outside the memory cell 113 and connected to the decoupling capacitor 2021G2.

  The ground lines 2003B1 to 2003B8 in each bank of each group are connected outside the memory cell 113 and connected to the decoupling capacitors 2020G1 and 2020G2.

  A constant voltage such as a ground voltage or a power supply voltage is applied to the counter electrodes of the decoupling capacitors 2020G1, 2020G2, 2021G1, and 2021G2.

  Therefore, as in the case of the semiconductor memory device of the thirteenth or fourteenth embodiment, noise on the line is absorbed by the decoupling capacitor, so that interference of data read voltage noise between banks and between groups is reduced. It becomes possible.

  As described above, in the semiconductor memory device according to the fourteenth embodiment of the present invention, in addition to the effect of the semiconductor memory device of FIG. It is possible to prevent malfunctions from being transmitted to the group.

(16) Embodiment 16
FIG. 24 is a circuit diagram showing a Vpp pump in the semiconductor memory device according to the sixteenth embodiment of the present invention. Referring to FIG. 24, Vpp pump 2400 includes pump clock signal CLK1 and internal bank address signal int. The AND circuit 501 to which BA is input is replaced with an inverter 2401 to which an activation signal / ACT (activation signals such as / ACT1, / ACT2 are collectively referred to as / ACT) is input.

  The Vpp pump 2400 includes the internal power supply voltage output circuits 1301 and 1303 of FIG. 13 of the seventh embodiment, the internal power supply voltage output circuits 1601 and 1603 of FIG. 16 of the ninth embodiment, and the VDC circuit 1301 of the twelfth embodiment. , 1303, the VDC circuit 2101 of the thirteenth embodiment, the internal power supply voltage output circuits 1601 and 1603 of the fourteenth embodiment, and the like when the boosted voltage Vpp is supplied to each bank in the memory cell array 113. The same effect as the embodiment can be obtained. However, VDC circuit 2101 of the thirteenth embodiment includes two Vpp pumps 2400 (one corresponding to each bank).

(17) Embodiment 17
FIG. 25 is a circuit diagram showing a Vbb pump in the semiconductor memory device according to the seventeenth embodiment of the present invention. Referring to FIG. 25, Vbb pump 2500 is similar to Vbb pump 209 in FIG. 2 except that pump clock signal CLK1 and internal bank address signal int. The AND circuit 501 to which BA is input is deleted, and the activation signal / ACT is input to one electrode of the capacitor Cp.

  The Vbb pump 2500 includes the internal power supply voltage output circuits 1301 and 1303 of FIG. 13 of the seventh embodiment, the internal power supply voltage output circuits 1601 and 1603 of FIG. 16 of the ninth embodiment, and the VDC circuit 1301 of the twelfth embodiment. , 1303, the VDC circuit 2101 of the thirteenth embodiment, the internal power supply voltage output circuits 1601 and 1603 of the fourteenth embodiment, and the like when the substrate voltage Vbb is supplied to each bank in the memory cell array 113. The same effect as the embodiment can be obtained. However, VDC circuit 2101 of the thirteenth embodiment includes two Vbb pumps 2500 (one corresponding to each bank).

100, 300, 400, 600, 800, 900, 1000, 1800, 2000, 2100, 2200, 2300 Semiconductor memory device, 103 RAS buffer circuit, 303
CAS buffer circuit, 105, 305 clock signal generation circuit, 107 address buffer, 109, 111, 2500 Vbb pump, 409, 411, 2400 Vpp pump, 609, 611, 1001, 1300, 1400, 1500, 1610, 1701, 1703 1801, 1900, 2101 VDC circuit, 1301, 1303, 1601, 1603 internal voltage output circuit, 113 memory cell array, B1-B8 bank, N3 internal voltage output node, 2001B1-2001B8 internal power supply line, 2003B1-2003B8 ground line, 2020, 2020G1, 2021, 2021G2 Decoupling capacitors.

Claims (1)

First to second N banks each including a circuit including a memory cell array having a plurality of memory cells and a plurality of sense amplifiers for sensing data of these memory cells;
A first PMOS transistor having one electrode to which an external power supply voltage supplied from the outside is input and the other electrode that outputs a first internal power supply voltage obtained by stepping down the external power supply voltage; and the first internal power supply And a first current that outputs a voltage to the gate electrode of the first PMOS transistor in accordance with a comparison result between the first internal power supply voltage and the internal step-down voltage. And a mirror-type amplifier circuit, and the first to N-th external bank address signals indicating the selection of the first to N-th banks given from the outside are used to activate the first A first internal step-down circuit that outputs the internal power supply voltage of
A second PMOS transistor having one electrode to which the external power supply voltage is input and the other electrode that outputs a second internal power supply voltage obtained by stepping down the external power supply voltage; the second internal power supply voltage; A second current mirror type amplifier that receives a step-down voltage and outputs a voltage to the gate electrode of the second PMOS transistor in accordance with a comparison result between the second internal power supply voltage and the internal step-down voltage. A signal activated in response to any of the (N + 1) th to 2Nth external bank address signals indicating the selection of the (N + 1) th to 2Nth banks provided from the outside. A second internal step-down voltage circuit for outputting two internal power supply voltages;
A plurality of sense amplifiers of the corresponding memory array, extending from outside the memory cell array region into the memory cell array region and wired in the memory cell array region corresponding to the first to Nth banks. Even if at least any of the first to Nth external bank address signals is activated, a plurality of first wirings to which the internal power supply voltage is supplied in response to the activation And extending from outside the memory cell array region into the memory cell array region, wired in the memory cell array region corresponding to the (N + 1) th to 2Nth banks, and supplying the internal power supply voltage to a plurality of corresponding memory arrays. Even if any of the (N + 1) th to (2N) th external bank address signals is activated, this active amplifier is activated. Depending on the reduction, and a third wiring, wherein the internal power supply voltage is connected a plurality of second wirings and the plurality of first wiring supplied outside the memory cell array area,
A fourth wiring connecting the plurality of second wirings outside the memory cell array region;
A semiconductor memory device in which the third wiring and the fourth wiring are disconnected.

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