JP2009253819A - Solid-state image sensor and driving method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS-type image sensor for reducing the influence that parasitic resistance between pixels exerts upon a blackening correction potential. <P>SOLUTION: In a CMOS-type image sensor comprising a pixel 1 that includes a photo-diode 11, an FD section 16, a reset transistor 13, an amplification transistor 14 and a selection transistor 15, a pixel 1b connected to the same vertical signal line 26 as an output pixel 1a, that outputs an electric signal detected by the FD section 16a, and disposed at a position spaced apart from the output pixel 1a by a predetermined distance is defined as a correction pixel, a potential Vref is applied to an FD section 16b of the correction pixel, and a selection transistor 15b of the correction pixel 1b is brought into a conducting state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a driving method thereof. Specifically, the present invention relates to a solid-state imaging device capable of suppressing the blackening phenomenon and a driving method thereof.

  2. Description of the Related Art Solid-state imaging devices such as CMOS (Complementary Metal Oxide Semiconductor) type image sensors have recently been used for imaging devices mounted on various portable terminal devices such as mobile phones, and image input devices for imaging devices such as digital still cameras and digital video cameras. Widely used as (imaging device) (see, for example, Patent Document 1).

  FIG. 6 is a schematic diagram for explaining a CMOS type image sensor. The CMOS type image sensor includes a pixel array unit 202 in which a large number of pixels 201 having photoelectric conversion elements are arranged in a matrix, and each pixel array unit. A vertical scanning circuit 203 that controls the shutter operation and readout operation of each pixel by selecting pixels row by row, and signals from the pixel array unit are read out row by row, and predetermined signal processing (for example, CDS processing) is performed for each column. Column signal processing unit 204 for performing (processing for removing fixed pattern noise caused by variations in threshold values of pixel transistors), AGC (auto gain control) processing, analog-digital conversion processing, and the like, and a signal of the column signal processing unit 1 A horizontal scanning circuit 206 that selects and leads to the horizontal signal line 205 one by one, and a signal output from the horizontal signal line to an intended output form Over a data signal processing section 207 for performing data conversion, the timing generator 208 supplies various pulse signals required for the operation of each unit based on the reference clock.

  Here, each pixel 201 in the pixel array section includes four transistors, a transfer transistor 102, a reset transistor 103, an amplification transistor 104, and a selection transistor 105, in addition to the photoelectric conversion element (for example, photodiode) 101, as shown in FIG. The circuit configuration includes a transistor. Here, a circuit example using n-channel MOS transistors as these transistors 102 to 105 is shown.

  The transfer transistor 102 is connected between the cathode electrode of the photodiode 101 and the FD (floating diffusion) unit 106, and the gate electrode is connected to the transfer control line 111 to which the transfer gate pulse TG is applied. In the reset transistor 103, a drain electrode is connected to the power source Vdd, a source electrode is connected to the FD unit 106, and a gate electrode is connected to a reset control line 112 to which a reset pulse RS is applied.

  In the amplification transistor 104, a gate electrode is connected to the FD portion 106, a drain electrode is connected to the power supply Vdd, and a source electrode is connected to the drain electrode of the selection transistor 105. The selection transistor 105 has a gate electrode connected to a selection control line 113 to which a selection pulse SEL is applied and a source electrode connected to a vertical signal line 216. The vertical signal line is connected to a constant current source 217 that supplies a constant current to the vertical signal line, and is also connected to a column signal processing unit.

  FIG. 8 is a schematic diagram showing a cross-sectional structure of a pixel portion excluding the amplification transistor 104 and the selection transistor 105.

N-type diffusion regions 132, 133, and 134 are formed in the surface layer portion of the p-type substrate 131. In addition, on the p-type substrate 131, a gate electrode 135 is provided above the space between the n-type diffusion region 132 and the n-type diffusion region 133, and above the space between the n-type diffusion region 133 and the n-type diffusion region 134. Each of the gate electrodes 136 is formed via a gate oxide film (SiO ₂ ) (not shown).

  In correspondence with FIG. 7, the photodiode 101 is formed by a pn junction between a p-type substrate 131 and an n-type diffusion region 132. The transfer transistor 102 is formed by an n-type diffusion region 132 and an n-type diffusion region 133 and a gate electrode 135 therebetween. The reset transistor 103 is formed by an n-type diffusion region 133 and an n-type diffusion region 134 and a gate electrode 136 therebetween.

  The n-type diffusion region 133 becomes the FD portion 106 and is electrically connected to the gate electrode of the amplification transistor 104. A power supply potential Vdd is applied to the n-type diffusion region 134 which becomes the drain region of the reset transistor 103. The upper surface of the p-type substrate 131 excluding the photodiode 101 is covered with a light shielding layer 137.

  Next, the circuit operation of the pixel 201 will be described using the waveform diagram of FIG. 9 based on the cross-sectional view of FIG.

  As shown in FIG. 8, when the photodiode 101 is irradiated with light, a pair of electrons (−) and holes (+) is induced according to the intensity of light (photoelectric conversion). In FIG. 9, the selection pulse SEL is applied to the gate electrode of the selection transistor 105 at the time T <b> 1, and the reset pulse RS is simultaneously applied to the gate electrode of the reset transistor 103. As a result, the reset transistor 103 becomes conductive, and the FD portion 106 is reset to the power supply potential Vdd at time T2.

  When the FD unit 106 is reset, the potential of the FD unit 106 at the time of reset is output to the signal line 216 through the amplification transistor 104 as the reset level Vn. This reset level corresponds to a noise component specific to the pixel 201. The reset pulse RS is in an active (“H” level) state only for a predetermined period (time T1 to T3). The FD unit 106 maintains the reset state even after the reset pulse RS transitions from the active state to the inactive (“L” level) state. The period in this reset state is the reset period.

  Next, the transfer gate pulse TG is applied to the gate electrode of the transfer transistor 102 at time T4 while the selection signal SEL remains active. Then, the transfer transistor 102 becomes conductive, photoelectrically converted by the photodiode 101, and the accumulated signal charge is transferred to the FD unit 106. As a result, the potential of the FD portion 106 changes according to the amount of signal charges (time T4 to T5). The potential of the FD unit 106 at this time is output as a signal level Vs to the signal line 216 through the amplification transistor 104 (signal reading period). The difference RSI1 between the signal level Vs and the reset level Vn becomes a pure pixel signal level from which noise components are removed.

  Usually, when a bright object is imaged, more charge is accumulated in the photodiode 101 during the reset period than when a dark object is imaged, so the level difference RSI1 on the vertical signal line 216 is larger.

(Generation mechanism of blackening phenomenon)
By the way, in the CMOS image sensor having the above-described configuration, when very strong light such as sunlight is incident on the pixel 201, a phenomenon that the brightest part sinks black, so-called blackening phenomenon occurs.

  The generation mechanism of this blackening phenomenon is demonstrated using FIG.10 and FIG.11. FIG. 10 is a schematic diagram for explaining the mechanism of occurrence of the blackening phenomenon, and has a structure substantially similar to FIG. FIG. 11 is a waveform diagram during the blackening phenomenon.

  In the reset period, similarly to the case of FIG. 8, the selection pulse SEL is applied to the gate electrode of the selection transistor 105 at the time T1 ′, and at the same time, the reset pulse RS is applied to the gate electrode of the reset transistor 103. As a result, the reset transistor 103 is turned on, and the FD unit 106 is reset to the power supply potential Vdd at time T2 ′. The potential of the FD unit 106 at the time of reset is output to the signal line 216 via the amplification transistor 104 as the reset level Vn.

  However, as shown in FIG. 10, when the photodiode 101 is irradiated with very strong light such as sunlight, the pn junction formed by the p-type substrate 131 and the n-type diffusion region 132 is connected to the pn junction portion shown in FIG. In comparison with, a larger number of electron (-) and hole (+) pairs are induced. As a result, excessive electrons subjected to photoelectric conversion overflow from the photodiode 101. Therefore, even though the transfer gate pulse is in an inactive state, excess electrons jump over the transfer transistor 102 and reach the FD unit 106. For this reason, the potential of the FD section 106 is lowered, and as a result, the potential of the vertical signal line 216 is lowered (T2 ′ to T4 ′).

  Similarly, if the transfer gate pulse TG is applied to the gate electrode of the transfer transistor 102 at time T4 ′ while the selection signal SEL remains in the active state in the signal readout period, the transfer transistor 102 becomes conductive, and the photo The signal charge photoelectrically converted by the diode 101 and transferred is transferred to the FD unit 106. As a result, the potential of the FD unit 106 is output to the vertical signal line 216 through the amplification transistor 104 as the signal level Vs.

  At this time, as a result of excess electrons leaking out during the reset period as described above, as is apparent from FIG. 11, the potential of the vertical signal line 216 is lower than when the reset pulse RS is applied. As a result, the potential difference RSI2 in the signal readout period is lowered despite the strong light irradiation.

  That is, as shown in FIG. 12, normally, the difference Vs−Vn between the signal level potential Vs in the signal readout period and the reset level potential Vn in the reset period is output as a pure pixel signal level, and the amount of incident light is constant. If it exceeds B, the signal level Vs is saturated, and a constant pixel signal level is output. Then, when the incident light quantity exceeds a predetermined light quantity C that is larger than the light quantity B, the reset level Vn changes due to excess electrons leaking from the photodiode 101 as described above. As a result, the difference Vs−Vn becomes small despite intense light being irradiated. For this reason, a blackening phenomenon that appears black despite the fact that it is very bright occurs.

In order to avoid such a blackening phenomenon, as shown in FIG. 13, a blackening auxiliary circuit 150 is connected to the vertical signal line, and correction is performed so that the reset level Vn does not decrease excessively.
Specifically, the blackening correction circuit 150 includes a correction transistor 151 and a control switch 152. One end of the control switch is connected to the vertical signal line 216, and the other end is connected to the source electrode of the correction transistor. Then, the power source Vdd is connected to the drain electrode of the correction transistor, and a predetermined potential (Vref) is applied to the gate electrode of the correction transistor so that the reset level Vn is not excessively lowered.

Hereinafter, avoidance of the blackening phenomenon by the blackening correction circuit will be described. Here, symbol X in FIG. 13 represents a pixel that performs signal readout, and current I _{1 in} FIG. 13 represents a current that flows between the drain and source of the selection transistor 105 in the pixel that performs signal readout. A current I ₂ indicates a current flowing between the drain and source of the correction transistor 151 in the blackening correction circuit.

First, when the blackening correction circuit is not connected and no current flows between the drain and the source of the correction transistor 151 in the blackening correction circuit, the current I ₂ = 0, so that the current I ₁ Will always remain constant. Then, when very strong light is applied to a pixel that reads out a signal, the potential of the FD portion 106 in the pixel that reads out the signal is lowered, and the potential of the FD portion 106 is lowered. The potential applied to the gate electrode is lowered. Although the potential applied to the gate electrode of the amplifying transistor 104 is lowered, the current flowing between the drain and source of the amplifying transistor 104 needs to be kept constant, so that the potential on the source side of the amplifying transistor 104 is lowered. Will be. This is the cause of the blackening phenomenon.

On the other hand, when a blackening correction circuit is connected and a current flows between the drain and source of the correction transistor 151 in the blackening correction circuit, the sum of the currents I ₁ and I ₂ is always constant. Will be kept. Then, when very strong light is irradiated to the pixel that reads out the signal, as described above, the potential of the FD portion 106 in the pixel that reads out the signal decreases, and the potential of the FD portion 106 decreases. The potential applied to the gate electrode of the amplification transistor 104 is lowered. Here, reduced potential applied to the gate electrode of the amplification transistor 104, the source side potential of the amplification transistor 104 is lowered, the drain of the correcting transistor 151 - to the potential difference between the source increases, current I ₂ As a result of the increase, decrease in the potential on the source side of the amplification transistor 104 can be mitigated. As a result, the blackening phenomenon can be avoided.

JP 10-1226697 A

As described above, conventionally, correction is performed so that the reset level Vn is not excessively lowered by connecting a blackening correction circuit to a vertical signal line. When paying attention to the pixel column, the distance from the pixel to the blackening correction circuit differs depending on the position where the pixel is arranged, and therefore the wiring resistance of the vertical signal line differs for each pixel.
For example, n pixels are connected to each vertical signal line, and the area between the vertical signal line where the blackening correction circuit is connected and the vertical signal line where the pixel in the first row is connected. The wiring resistance of the vertical signal line is R0, and the vertical distance from the position of the vertical signal line to which the pixel in the i-th row is connected to the position of the vertical signal line to which the pixel in the (i + 1) -th row is connected. When the wiring resistance of the signal line is Ri, the potential of the pixels in the first row is transferred to the blackening correction circuit through the resistance of R0, and the pixel of the second row passes through the resistance of [R0 + R1]. Is transferred to the blackening correction circuit via the resistance of [R0 + R1 + R2 +... + R (n−1)], and so on. Differences in wiring resistance of vertical signal lines occur for each row in which pixels are arranged) .

Note that if a difference occurs in the wiring resistance of the vertical signal line for each pixel, a difference in voltage drop occurs for each pixel.
That is, the drain of the amplification transistor in the pixel performing a signal read - and the current flowing between the source and I _1, R0 × I ₁ of the voltage to the pixel of the first row is potential blackening correction circuit is transferred drop occurs, the pixels of the second line to the [R0 + R1] × occur a voltage drop of I ₁ is the potential to blackening correction circuit is transferred, ..., the n-th row of pixels blackening correction circuit potential becomes [R0 + R1 + ··· + R (n-1)] the voltage drop × _{I 1} occurs until transferred to.

If there is a difference in voltage drop until the potential is transferred to the blackening correction circuit for each pixel (each row in which the pixel is arranged), the correction potential by the blackening correction circuit is changed for each pixel (pixel is arranged). For each line).
For example, even if the potentials at point A and point B in FIG. 13 are equal, the voltage drop that occurs until the potential is transferred from point A to point D and the potential is transferred from point B to point D. Since the generated voltage drops are different, the potential for correcting blackening is different.

  The present invention was devised in view of the above points, and an object thereof is to provide a solid-state imaging device capable of reducing the influence of parasitic resistance between pixels on the blackening correction potential and a driving method thereof. It is what.

  In order to achieve the above object, in a solid-state imaging device according to the present invention, a photoelectric conversion element, a detection node for detecting an electric signal obtained by the photoelectric conversion element, and an electric signal detected by the detection node A pixel array unit in which pixels having output transistors for output are arranged in a matrix, a signal line wired for each pixel column of the pixel array unit, and a constant current source for supplying a constant current to the signal line One end of the output transistor is connected to the signal line via a switching element, a first predetermined potential is applied to the other end of the output transistor, and a gate of the output transistor is connected to the detection node. In the solid-state imaging device, the pixel is connected to the same signal line as the output pixel that outputs the electrical signal detected by the detection node among the pixels, and is connected to the output pixel. The pixel arranged at a distance is set as a correction pixel, a second predetermined potential is applied to a detection node of the correction pixel, and the switching element connected to the output transistor of the correction pixel is in a conductive state. I am doing.

  In order to achieve the above object, in the solid-state imaging device driving method according to the present invention, a photoelectric conversion element, a detection node for detecting an electric signal obtained by the photoelectric conversion element, and detection by the detection node A pixel array unit in which pixels having output transistors for outputting the electrical signals are arranged in a matrix, a signal line wired for each pixel column of the pixel array unit, and supplying a constant current to the signal line A constant current source, one end of the output transistor is connected to the signal line via a switching element, a first predetermined potential is applied to the other end of the output transistor, and the gate of the output transistor is the detection Connected to a node and connected to the same signal line as an output pixel that outputs an electrical signal detected by a detection node among the pixels, and a predetermined distance from the output pixel. A solid-state imaging device driving method using the pixel arranged at a separated position as a correction pixel, and before outputting an electrical signal detected by the detection node of the output pixel, the detection node of the correction pixel And a step of applying a predetermined potential of 2 and bringing the switching element connected to the output transistor of the correction pixel into a conductive state.

  Here, the correction pixel is arranged at a position separated from the output pixel by a predetermined distance, and the distance from the output pixel to the correction pixel is always substantially constant regardless of the position where the pixel is arranged. Differences in signal line resistance are unlikely to occur.

  In addition, the second predetermined potential is applied to the detection node of the correction pixel, and the switching element connected to the output transistor of the correction pixel is in a conductive state, which makes it very similar to the conventional blackening correction circuit. Even when intense light is irradiated to the output pixel, correction can be performed so that the reset level does not decrease excessively.

  Further, the correction pixel may be singular or plural. That is, for example, only a pixel arranged at a position separated from the output pixel by a distance d may be used as a correction pixel, or a pixel arranged at a position separated by a distance d1 from the output pixel and a distance d2 from the output pixel. Both of the pixels arranged at the positions may be corrected pixels. Here, when very strong light is irradiated to the correction pixel, the potential of the detection node of the correction pixel is lowered, and sufficient correction cannot be performed. It is more preferable.

  If the output pixel is not irradiated with very strong light, it is not necessary to perform correction to avoid the blackening phenomenon in the first place. Therefore, even if the correction pixel is irradiated with very strong light, there is a problem. Must not.

  The solid-state imaging device according to the present invention includes a photoelectric conversion element, a detection node that detects an electric signal obtained by the photoelectric conversion element, and an output transistor that outputs the electric signal detected by the detection node. A pixel array section in which pixels are arranged in a matrix, a signal line wired for each pixel column of the pixel array section, and a constant current source for supplying a constant current to the signal line, and one end of the output transistor Is connected to the signal line via a switching element, a first predetermined potential is applied to the other end of the output transistor, and the gate of the output transistor is connected to the detection node in the solid-state imaging device. Among the other pixels connected to the same signal line as the output pixel that outputs the electrical signal detected by the detection node, as the correction pixel, With the second predetermined potential is applied to the output node, the output transistor and connected to said switching elements of the correction pixel forms a conductive state.

  In the solid-state imaging device driving method according to the present invention, a photoelectric conversion element, a detection node for detecting an electric signal obtained by the photoelectric conversion element, and an output transistor for outputting the electric signal detected by the detection node A pixel array section in which pixels having the above are arranged in a matrix, a signal line wired for each pixel column of the pixel array section, and a constant current source for supplying a constant current to the signal line, the output One end of the transistor is connected to the signal line via a switching element, a first predetermined potential is applied to the other end of the output transistor, the gate of the output transistor is connected to the detection node, A solid-state imaging device driving method in which all other pixels connected to the same signal line as an output pixel that outputs an electrical signal detected by a detection node are correction pixels. Thus, before outputting the electrical signal detected by the detection node of the output pixel, a second predetermined potential is applied to the detection node of the correction pixel and the switching element connected to the output transistor of the correction pixel A step of bringing the conductive state into a conductive state.

  Here, since all the pixels other than the output pixel are the correction pixels, correction for avoiding the blackening phenomenon can be performed more sufficiently. That is, as described above, when the correction pixel is irradiated with very strong light, the potential of the detection node of the correction pixel is lowered, and it is considered that sufficient correction cannot be performed. By making all the pixels other than the output pixels correction pixels so as to maximize the number of pixels, correction for avoiding the blackening phenomenon can be performed more sufficiently.

  In the solid-state imaging device and the driving method thereof according to the present invention, the influence of parasitic resistance between pixels on the blackening correction potential can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining a CMOS image sensor which is an example of a solid-state imaging device to which the present invention is applied. In the CMOS image sensor shown here, a large number of pixels 1 having photoelectric conversion elements are arranged in a matrix. The pixel array unit 2 arranged in the vertical direction, the vertical scanning circuit 3 for selecting each pixel of the pixel array unit one row at a time and controlling the shutter operation and readout operation of each pixel, and the signal from the pixel array unit for one row Read the data one by one and perform predetermined signal processing for each column (for example, CDS processing (processing for removing fixed pattern noise caused by variations in threshold values of pixel transistors), AGC (auto gain control) processing, analog-digital conversion processing, etc.) The column signal processing unit 4 to be performed, the horizontal scanning circuit 6 for selecting the signals of the column signal processing unit one by one and leading them to the horizontal signal line 5, and the horizontal signal line Having a data signal processing unit 7 for performing data conversion output form intended, the timing generator 8 supplies various pulse signals required for the operation of each unit based on the reference clock to issue.

  Here, as shown in FIG. 2, each pixel 1 (1a, 1b, 1c) in the pixel array section has a transfer transistor 12 (in addition to the photoelectric conversion element (for example, photodiode) 11 (11a, 11b, 11c). 12a, 12b, 12c), a reset transistor 13 (13a, 13b, 13c), an amplifying transistor 14 (14a, 14b, 14c), and a selection transistor 15 (15a, 15b, 15c). Yes. In the present embodiment, a circuit example using n-channel MOS transistors as the transistors 12 to 15 is shown.

The transfer transistor 12 is connected between the cathode electrode of the photodiode 11 and the FD (floating diffusion) portion 16 (16a, 16b, 16c), and is subjected to transfer control to which a transfer gate pulse TG (TGa, TGb, TGc) is applied. A gate electrode is connected to the line 21 (21a, 21b, 21c). The reset transistor 13 has a reset control line to which a drain electrode is applied to the potential V _SEL (V _SEL a, V _SEL b, V _SEL c), a source electrode is applied to the FD unit 16, and a reset pulse RS (RSa, RSb, RSc) is applied. The gate electrodes are respectively connected to 22 (22a, 22b, 22c).

In the amplification transistor 14, the gate electrode is connected to the FD portion 16, the drain electrode is connected to the potential V _SEL , and the source electrode is connected to the drain electrode of the selection transistor 15. The selection transistor 15 has a gate electrode connected to a selection control line 23 (23a, 23b, 23c) to which a selection pulse SEL (SELa, SELb, SELc) is applied, and a source electrode connected to a vertical signal line 26. The vertical signal line is connected to a constant current source 27 that supplies a constant current to the vertical signal line, and is also connected to a column signal processing unit.

  The FD unit 16 is an example of a detection node, the amplification transistor 14 is an example of an output transistor, and the selection transistor 15 is an example of a switching element.

  Hereinafter, a driving method of the CMOS type image sensor configured as described above will be described with reference to a timing chart of each pulse shown in FIG. That is, an example of a driving method of a CMOS image sensor which is an example of a driving method of a solid-state imaging device to which the present invention is applied will be described. In the following description, the output pixel is denoted by reference numeral 1a, the correction pixel is denoted by reference numeral 1b, and the pixel that does not correspond to either the output pixel or the correction pixel is denoted by reference numeral 1c. In the initial state, the transfer gate pulse TG (TGa, TGb, TGc), the reset pulse RS (RSa, RSb, RSc) and the selection pulse SEL (SELa, SELb, SELc) are all low level (hereinafter referred to as “L level”). In the following description, it is assumed that the FD portion 16b of the correction pixel 1b is set to a predetermined potential Vref for blackening correction.

In the CMOS image sensor driving method, first, the selection pixel SELb is set to a high level (hereinafter referred to as “H level”) at the timing indicated by the symbol t1, and the selection transistor 15b is turned on, whereby the correction pixel 1b is turned on. It is electrically connected to the vertical signal line 26. At this time, the potential V _SEL b applied to the drain electrode of the amplification transistor 14b is set to the power supply potential Vdd.

Further, at the timing indicated by the symbol t1, in order to reset the potential of the FD unit 16a of the output pixel 1a, the reset pulse RSa is set to H level and the reset transistor 13a is turned on, whereby the potential V _SEL a is applied to the FD unit 16a. (= Power supply potential Vdd) is applied. At the same time, the selection pulse SELa is set to H level to turn on the selection transistor 15a, thereby reading the reset potential (reset level potential Vn) of the FD portion 16a.

  Subsequently, the transfer gate pulse TGa is set to H level to turn on the transfer transistor 12a, thereby reading the potential (signal level potential Vs) of the FD portion 16a corresponding to the signal amount obtained by the photodiode 11a.

  The reset pulse RSa is set to the L level at the timing indicated by the symbol t2 without waiting for the completion of the read period of the reset level potential Vn, so that the reset transistor 13a is turned off, and the selection pulse SELb is also in the signal level potential Vs read period. Without waiting for completion, the selection transistor 15a is made non-conductive at the L level at the timing indicated by the symbol t3.

Next, the potential V _SEL a applied to the drain electrode of the amplification transistor 15a at the timing indicated by the symbol t4 after the completion of the signal level potential Vs readout period is set to the predetermined potential Vref for blackening correction. At the timing indicated by t5, the reset pulse RSa is set to H level to bring the reset transistor 13a into a conductive state, whereby the FD portion 16a is set to the predetermined potential Vref for blackening correction.

  Thereafter, the reset pulse RSa is set to the L level at the timing indicated by the symbol t6 to set the reset transistor 13a to the non-conductive state, and the selection pulse SELa is set to the L level to set the selection transistor 15a to the non-conductive state at the timing indicated by the symbol t7 The readout of the pixel 1a is finished.

  When the pixel indicated by reference numeral 1b is read after the reading of the pixel indicated by reference numeral 1a, that is, when the output pixel is a pixel indicated by reference numeral 1b, the correction pixel is defined as a pixel indicated by reference numeral 1c. The same method as described above is performed.

In the present embodiment, the reset with the drain electrode and the drain electrode of the amplifying transistor 14 of the transistor 13 is connected to the potential _{V SEL,} 2 value of a predetermined potential Vref for the potential _{V SEL} power supply potential Vdd and blackening correction However, the potential V _SEL does not necessarily have a binary value, and as shown in FIGS. 4A and 4B, the supply source of the power supply potential Vdd is used. The supply source of the predetermined potential Vref for blackening correction may be divided.

  In this embodiment, the case where a single pixel is made to function as a correction pixel is described as an example. However, a plurality of pixels may be made to function as correction pixels, and all pixels other than output pixels may be made to function. These pixels may function as correction pixels.

  In the above CMOS type image sensor, the physical distance between the output pixel and the correction pixel can be kept constant. Therefore, the wiring resistance of the vertical signal line from the output pixel to the correction pixel is reduced regardless of the position where the pixel is arranged. Can be kept constant. Therefore, it is possible to always keep the blackening correction level constant regardless of the position where the pixel is arranged.

  Further, in the above CMOS image sensor, it is possible to avoid the blackening phenomenon with the same pixel structure as the conventional pixel structure. If only the point that the physical distance between the output pixel and the correction pixel is kept constant is taken into consideration, it is considered that the problem can also be solved by forming a blackening correction circuit 150 for each pixel as shown in FIG. However, when the blackening correction circuit 150 is separately formed for each pixel, the CMOS type image sensor chip is increased in size, so that this method is not necessarily appropriate.

  In the above-described CMOS image sensor, one photoelectric conversion element, one detection node for detecting an electric signal obtained by the photoelectric conversion element, and one output transistor for outputting the electric signal detected by the detection node However, a pixel configured by connecting a plurality of photoelectric conversion elements and a plurality of transfer transistors to the detection node as shown in FIG. 14 may be used.

It is a schematic diagram for demonstrating the CMOS type image sensor which is an example of the solid-state image sensor to which this invention is applied. It is a schematic diagram for demonstrating a pixel array part. It is a figure which shows the timing chart of each pulse. It is a schematic diagram for demonstrating the modification (1) of the CMOS type image sensor which is an example of the solid-state image sensor to which this invention is applied. It is a schematic diagram for demonstrating the modification (2) of the CMOS type image sensor which is an example of the solid-state image sensor to which this invention is applied. It is a schematic diagram for demonstrating the improvement method of another blackening phenomenon. It is a schematic diagram for demonstrating a CMOS type image sensor. It is a schematic diagram for demonstrating a pixel array part. It is a schematic diagram which shows the cross-section of a pixel part. It is a wave form chart for explaining circuit operation of a pixel. It is a schematic diagram for demonstrating the generation | occurrence | production mechanism of a blackening phenomenon. It is a wave form diagram for demonstrating the generation | occurrence | production mechanism of a blackening phenomenon. It is a graph for demonstrating a blackening phenomenon. It is a schematic diagram for demonstrating a blackening correction circuit. It is a schematic diagram for demonstrating the pixel comprised from the some photoelectric conversion element and the some transfer transistor.

Explanation of symbols

1 pixel 2 pixel array unit 3 vertical scanning circuit 4 column signal processing unit 5 horizontal signal line 6 horizontal scanning circuit 7 data signal processing unit 8 timing generator 11 photoelectric conversion element 12 transfer transistor 13 reset transistor 14 amplification transistor 15 selection transistor 16 FD unit 21 Transfer control line 22 Reset control line 23 Selective fishing boat 26 Vertical signal line 27 Constant current source

Claims (4)

A pixel array unit in which pixels having a photoelectric conversion element, a detection node that detects an electric signal obtained by the photoelectric conversion element, and an output transistor that outputs the electric signal detected by the detection node are arranged in a matrix When,
A signal line wired for each pixel column of the pixel array unit;
A constant current source for supplying a constant current to the signal line,
One end of the output transistor is connected to the signal line through a switching element, a first predetermined potential is applied to the other end of the output transistor, and the gate of the output transistor is connected to the detection node. In the element
The pixel connected to the same signal line as the output pixel that outputs the electrical signal detected by the detection node among the pixels, and the pixel disposed at a predetermined distance from the output pixel is a correction pixel,
A solid-state imaging device, wherein a second predetermined potential is applied to a detection node of the correction pixel, and the switching element connected to the output transistor of the correction pixel is in a conductive state. A pixel array unit in which pixels having a photoelectric conversion element, a detection node that detects an electric signal obtained by the photoelectric conversion element, and an output transistor that outputs the electric signal detected by the detection node are arranged in a matrix When,
A signal line wired for each pixel column of the pixel array unit;
A constant current source for supplying a constant current to the signal line,
One end of the output transistor is connected to the signal line through a switching element, a first predetermined potential is applied to the other end of the output transistor, and the gate of the output transistor is connected to the detection node. In the element
Among the pixels, all other pixels connected to the same signal line as an output pixel that outputs an electrical signal detected by a detection node are used as correction pixels,
A solid-state imaging device, wherein a second predetermined potential is applied to a detection node of the correction pixel, and the switching element connected to the output transistor of the correction pixel is in a conductive state. A pixel array unit in which pixels having a photoelectric conversion element, a detection node that detects an electric signal obtained by the photoelectric conversion element, and an output transistor that outputs the electric signal detected by the detection node are arranged in a matrix When,
A signal line wired for each pixel column of the pixel array unit;
A constant current source for supplying a constant current to the signal line,
One end of the output transistor is connected to the signal line via a switching element, a first predetermined potential is applied to the other end of the output transistor, a gate of the output transistor is connected to the detection node,
Among the pixels, the pixel that is connected to the same signal line as the output pixel that outputs the electrical signal detected by the detection node and that is disposed at a predetermined distance from the output pixel is used as a correction pixel. A method for driving a solid-state imaging device,
Before outputting the electrical signal detected by the detection node of the output pixel, a second predetermined potential is applied to the detection node of the correction pixel and the switching element connected to the output transistor of the correction pixel is turned on. A method for driving a solid-state imaging device. A pixel array unit in which pixels having a photoelectric conversion element, a detection node that detects an electric signal obtained by the photoelectric conversion element, and an output transistor that outputs the electric signal detected by the detection node are arranged in a matrix When,
A signal line wired for each pixel column of the pixel array unit;
A constant current source for supplying a constant current to the signal line,
One end of the output transistor is connected to the signal line via a switching element, a first predetermined potential is applied to the other end of the output transistor, a gate of the output transistor is connected to the detection node,
A driving method of a solid-state imaging device, in which all other pixels connected to the same signal line as an output pixel that outputs an electrical signal detected by a detection node among the pixels are correction pixels,
Before outputting the electrical signal detected by the detection node of the output pixel, a second predetermined potential is applied to the detection node of the correction pixel and the switching element connected to the output transistor of the correction pixel is turned on. A method for driving a solid-state imaging device.

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