JP2009253387A - Chroma key processing apparatus and chroma key processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high quality chroma key processing even for a dual link. <P>SOLUTION: Each of first and second chroma key processing portions 20A and 20B comprises a chroma key circuit and an auto chroma key determination circuit. A chroma value is determined in parallel by way of each of the chroma key determination circuits, and chroma key processing is started from an identical image frame, respectively. A chroma value determined by the chroma key determination circuit of the first auto chroma key processing portion 20A is supplied to the chroma key determination circuit of the second auto chroma key processing portion 20B through a channel as a common chroma value. Chroma key processing is started from the identical image frame using the common chroma value, with each chroma key circuit of the first and the second chroma key processing portions 20A and 20B. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a chroma key processing apparatus and a chroma key processing method for processing an image, and more particularly to a chroma key processing apparatus and a chroma key processing method corresponding to a dual link.

  2. Description of the Related Art Conventionally, in television broadcasting stations and video editing sites, a special effect called keying has been applied using a video synthesizer called an effect switcher. Keying is designated by a key source signal (a video signal that designates a portion having a signal level equal to or higher than a predetermined threshold as a region to superimpose a video) in a background video (main video signal constituting a screen). This is a process of superimposing a key fill signal (a video signal superimposed as a foreground on a background video) on an area.

  The chroma key processing is processing for synthesizing (replacing) a foreground video signal (key fill) in an area that matches a specified chroma (color) component in a target video signal.

  In the auto-chroma key operation, the operator specifies a partial area of the target video signal on the image while viewing the image, and automatically specifies the specified chroma (color) based on the color value of the partial area. It is an operation that decides automatically.

  For example, the color is determined by averaging the color values of the pixels in the specified partial area. Since the color determination process reads and calculates the value of the video signal, it must be performed by a circuit added to the circuit processing the video signal. This circuit is called an auto chroma key determination circuit.

  In 3G-SDI, the physical layer standard such as signal amplitude and signal rise / fall time is standardized by SMPTE 424M, and the data format and mapping are standardized by SMPTE 425M. .

  The data format and mapping method defined in SMPTE425M include HD-SDI double speed (1080p50 / 59.94 / 60), but 12-bit transmission or dual link HD-SDI. Convert 3G-SDI to 2G HD-SDI and convert 3G-SDI to 3G-SDI. SMPTE 424M defines electrical specifications for serial transmission. Further, a rule for combining two data streams into one data stream is defined. The standardized items are amplitude, rise / fall time, rise / fall time difference, DC offset, return loss, etc., as in SD-SDI and HD-SDI.

Japanese Patent Laid-Open No. 2000-197072 JP 2007-13466 A

  By the way, there is a limit to the signal processing speed of the elements (devices) constituting the circuit, and it is impossible to perform higher speed processing, or elements that are more expensive (price more than twice) are required.

  By using a dual link, it is only necessary to prepare two cheap elements for the system, resulting in a low cost.

  In addition, since a circuit that performs high-speed processing has a problem specific to a high-frequency circuit, it is difficult to design the circuit itself.

  For this reason, a substrate with half the processing speed is easier to design and consequently cheaper.

  In addition, there are two types of signal formats for video signals that differ only in whether they are interlaced or progressive, and a circuit for processing interlaced video signals is operated in a dual link format. Can process progressive video signals.

  For this reason, since the same apparatus and board | substrate can be used with two types of signal formats according to the use at the time of operation, it is economical.

  In terms of manufacturing, it is economical because it can be used for two types of signal formats by manufacturing only one type of circuit / substrate.

  Conventionally, in the dual link, the auto / chroma key determination circuit is a part of the above processing circuit, so that two systems are provided.

  And since it is a dual link, it is controlled exactly the same and operates in parallel.

  An object of the present invention is to realize high-quality chroma key processing even in a dual link in view of the above-described conventional situation.

  Other objects of the present invention and specific advantages obtained by the present invention will become more apparent from the description of embodiments described below.

  In the dual link, an input video signal is divided into two signals of even-numbered scan lines and odd-numbered scan lines, and the two signals are processed in parallel using two processing circuits having the same configuration. The outputs of the two processing circuits can be integrated into one video signal for output. The two processing circuits are easy to create if the conventional interlace method is used as it is. Therefore, if the even number and odd number of the interlace field are reversed with the two processing circuits and operated, the two processing circuits are left as they are. Even lines and odd lines can always be processed. The control of the two processing circuits is basically the same, but the final output video signal is changed by devising the control according to the processing contents in consideration of whether the scanning line to be handled is even or odd. Raise quality.

  That is, the present invention is a dual-link chroma key processing device including two image processing circuits each including a chroma key circuit and an auto / chroma key determination circuit, and a communication path connecting the two image processing circuits. The chroma value determined by the auto-chroma key determination circuit of one image processing circuit is supplied to the chroma key circuit on the other image processing circuit via the communication path, and the one image processing circuit and the other image processing circuit Control is performed to make the same image frame for starting chroma key processing.

  Further, the present invention is a chroma key processing method corresponding to dual link, wherein the chroma value is determined in parallel by each auto chroma key determination circuit of two image processing circuits each having a chroma key circuit and an auto chroma key determination circuit. The chroma key processing is started from the same image frame, and the chroma value determined by the auto / chroma key determination circuit of one image processing circuit is supplied as a common chroma value to the chroma key circuit on the other image processing circuit via the communication path. Then, the chroma key processing using the common chroma value is started from the same image frame by the chroma key circuits of the two image processing circuits.

  In the present invention, chroma values are determined in parallel by each auto-chroma key determination circuit of two image processing circuits each having a chroma key circuit and an auto-chroma key determination circuit, and chroma key processing is started from the same image frame. The chroma value determined by the auto-chroma key determination circuit of the image processing circuit is supplied as a common chroma value to the chroma key circuit on the other image processing circuit via the communication path, and is transmitted by each chroma key circuit of the two image processing circuits. By starting the chroma key processing using the common chroma value from the same image frame, high quality chroma key processing can be realized even in the dual link, and the quality of the final output image can be improved. In addition, when the chroma key process is started, a phenomenon in which the process start timing is different for each scanning line of the image can be prevented, flicker is eliminated, and the quality is improved. Furthermore, the delay until the chroma key process is started can be minimized, and the quality can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Needless to say, the present invention is not limited to the following examples, and can be arbitrarily changed without departing from the gist of the present invention.

  In the present invention, as shown in FIG. 1, for example, the first chroma key processing unit 20A and the second chroma key processing unit 20B perform chroma key processing on an image signal supplied by a dual link from the image reproducing device 1 or the imaging device 2. Thus, the present invention is applied to the effect switcher device 100 in the image processing system 5 that outputs to the monitor devices 3 and 4 by a dual link.

  In FIG. 1, an outline of how input / output connections are made so that the first chroma key processing unit 20A processes the link A side and the second chroma key processing unit 20B processes the link B side is illustrated. Yes. Further, the second chroma key processing unit 20B is linked to the control of the first chroma key processing unit 20A except for the operation that characterizes the present invention described below, and is indicated by a link arrow. Yes.

  For example, as shown in FIG. 2, the effect switcher device 100 includes a matrix switcher unit 10 that selects video signals input to input lines L1 to L9, and a video signal input to the input lines L1 to L9. The first image processing unit 20A supplied via the unit 10, the second image processing unit 20B supplied with the video signals input to the input lines L1 to L9 via the matrix switcher unit 10, A main unit 40 including a control unit 30 to be controlled and a selection input unit 60 connected to the control unit 30 of the main unit 40 via a communication path 50 are provided. In the following, in order to explain the features of the present invention, the image processing unit will be also referred to as a chroma key processing unit in order to focus on the chroma key processing.

  In the effect switcher device 100, a video signal serving as a key source signal or a key fill signal is input to the input lines L1 to L9 by a dual link method.

  The matrix switcher unit 10 is connected to a key source signal selection input bus 11A that supplies one of the video signals input to the input lines L1 to L9 as a key source signal to the first chroma key processing unit 20A. And a key source intersection array 12A composed of switches. The matrix switcher unit 10 is connected to a key fill signal selection input bus 13A that supplies one of the video signals input to the input lines L1 to L9 as a key fill signal to the first chroma key processing unit 20A. 14A, a key fill intersection row 14A comprising switches is provided. Further, the matrix switcher unit 10 selects a first background signal which supplies one of the video signals input to the input lines L1 to L9 as the first background signal to the first chroma key processing unit 20A. A first background intersection row 16A including switches connected to the input bus 15A is provided. The matrix switcher unit 10 also selects a second background signal that supplies one of the video signals input to the input lines L1 to L9 as the second background signal to the first chroma key processing unit 20A. A second background intersection array 18A comprising switches connected to the input bus 17A is provided. Further, the matrix switcher unit 10 supplies a key source signal selection input bus 11B for supplying one of the video signals input to the input lines L1 to L9 as a key source signal to the second chroma key processing unit 20B. A key source intersection array 12B composed of connected switches is provided. The matrix switcher unit 10 is connected to a key fill signal selection input bus 13B that supplies one of the video signals input to the input lines L1 to L9 as a key fill signal to the second chroma key processing unit 20B. A key fill intersection row 14B comprising the switches. The matrix switcher unit 10 also selects a first background signal that supplies one of the video signals input to the input lines L1 to L9 as the first background signal to the second chroma key processing unit 20B. A first background intersection row 16B comprising switches connected to the input bus 15B is provided. Further, the matrix switcher unit 10 selects a second background signal that supplies one of the video signals input to the input lines L1 to L9 as the second background signal to the second chroma key processing unit 20B. A second background intersection array 18B comprising switches connected to the input bus 17B is provided.

  The first image processing unit 20A includes a key processing circuit 21A and a composition circuit 22A.

  The key processing circuit 21A is connected to the key source signal selection input bus 11A and the key fill signal selection input bus 13A. In the key processing circuit 21A, the key source signal and key fill signal selected from the video signals input to the input lines L1 to L9 are sent via the key source signal selection input bus 11A and the key fill signal selection input bus 13A. Is input. The key processing circuit 21A performs a process of generating a key signal corresponding to the control signal from the control unit 30 based on the input key source signal. Details will be described later. The key processing circuit 21A supplies the key signal and the key fill signal to the synthesis circuit 22A.

  The synthesis circuit 22A is connected to the key processing circuit 21A, and is connected to the first background signal selection input bus 15A and the second background signal selection input bus 17A. The synthesizing circuit 22A receives the key signal and the key fill signal from the key processing circuit 21A. Further, in this combining circuit 22A, the first background signal and the second background signal selected from the video signals input to the input lines L1 to L9 are the first background signal selection input bus 15A and the first background signal. 2 background signal selection input bus 17A. The synthesizing circuit 22A performs keying processing for synthesizing the key fill signal by replacing the area indicated by the key signal supplied from the key processing circuit 21A with the first background signal or the second background signal.

  The second image processing unit 20B has the same configuration and function as the image processing unit 20A.

  The key processing circuit 21A includes an auto / chroma key determination circuit 23A, a chroma key circuit 24A, and a key fill signal processing circuit 25A, as shown in FIGS. 3A and 3B, for example. The key processing circuit 21B is configured similarly to the key processing circuit 21A, and includes an auto / chroma key determination circuit 23B, a chroma key circuit 24B, and a key fill signal processing circuit 25B.

  In the configuration example shown in FIG. 3A, the auto / chroma key determination circuit 23A (23B) controls the key source signal input from the key source signal selection input bus 11A (11B) under the control of the control unit 30. The chroma value of the pixel in the position range on the designated screen is acquired. The plurality of chroma values are averaged and used for chroma key processing. The averaging process may be performed by a hardware circuit, or an average value may be obtained by software with a built-in microcomputer.

  The chroma key circuit 24A (24B) is a range in which a key source signal input from the key source signal selection input bus 11A (11B) is the same as the designated chroma value or a difference from the designated chroma value is set. For the pixels inside, the key source value is set to a small value (zero) so that the background can be seen, and for other areas, the key source value is set to a large value (1) so that the key fill signal can be seen. Output to the signal line.

  The key fill signal processing circuit 25A (25B) receives the key signal from the key signal line and the key fill signal from the key fill signal selection input bus 13A (13B), and processes the key fill signal so as to improve the keying image quality. Since this is not related to the feature of the present invention, detailed description is omitted.

  The key signal line and the processing key fill signal line are connected to the synthesis circuit 22A (22B).

  The configuration example shown in FIG. 3B is a configuration in which the key fill signal from the key fill signal selection input bus 13A (13B) is connected to the auto / chroma key determination circuit 23A (23B). Normally, in chroma key processing, the same image signal is used for the key source signal and the key fill signal, so that the same function can be achieved in this configuration as well.

  The structure of the key processing circuit 21B is exactly the same as that described with reference to FIGS.

  In the above description, the key signal is binary, and it has been described that the background signal or the key fill signal is specified. More specifically, the key signal indicates density instead of binary, and the key fill signal is superimposed on the background signal. Concentration is shown in multiple values. Therefore, it is also possible to perform image processing having a portion where the key fill signal looks translucent while the background is visible.

  In the case of chroma key processing, it is often more effective to eliminate the semi-transparent portion. When creating a semi-transparent portion, for example, for a pixel whose deviation from the specified chroma value is small (difference is within a set range), the density is determined according to the deviation (difference). Then, the chroma key circuit 24A (24B) is caused to function.

  Further, the control unit 30 includes a microcomputer, generates a control signal corresponding to the selection input signal given from the selection input unit 60 via the communication path 50, and generates the matrix via the control line 35. Each operation of the switcher unit 10, the first chroma key processing unit 20A, and the second chroma key processing unit 20B is controlled.

  The selection input unit 60 includes a microcomputer 65 to which a button arrangement unit 61, a keyboard 62, a pointing device 63 such as a mouse, a graphical display 64, and the like are connected. When input selection is operated with the button of the button arrangement unit 61, the matrix switcher unit 10 of the main unit operates so as to select a pair of inputs on the A side and the B side, respectively. For example, when the input L1 is the link A side of the first image signal and the input L2 is the link B side of the first image signal, if the selection of the first image signal is operated with respect to the first background, The operation of selecting L1 in the first background intersection row 16A and selecting L2 in the second background intersection row 16B is performed. The same operation is performed for other input pairs and intersection sequences. Note that when an interlaced image is handled by the same device, such a paired switching is not performed, and only a one-to-one correspondence with the operation is performed.

  The synthesizing circuit 22A also receives background signals from the first background signal selection input bus 15A and the second background signal selection input bus 17A, and outputs any background signal according to an instruction from the selection input unit 60. Either two background signals are synthesized by a synthesis method that is used or instructed at a designated ratio to obtain a combined background signal used for keying processing. The above ratio is manually instructed by the fader lever of the selection input unit, or in the case of automatic transition (automatic progression) operation, it changes with time and is controlled to switch from one background signal to the other background signal. The The above synthesis method is, for example, as a mix, weighted addition of two background signals for each pixel at the above ratio (for example, if the ratio is 30%, a value obtained by multiplying the value of the first background signal by 0.3; The value obtained by multiplying the value of the second background signal by 0.7 is added). Alternatively, as another synthesis method, the second background signal is keyed to the first background signal by a wipe key signal supplied from a wipe key waveform generation circuit (WKG: Wipe Key Generator) 26A in FIG. Perform the process of overlapping with. The key signal generated by the wipe key waveform generation circuit 6 changes with the above ratio. If automatic transition is performed, the key signal is generated so as to determine the boundary line of the wipe using the time t of progress as an input parameter. If it is not automatic transition, the indicated ratio is used instead of t.

  The above is the same for the synthesis circuit 22B.

  In the effect switcher device 100, the selection input unit 60 communicates with the control unit 30 of the main unit 40 via the communication path 50, and an operator views an image of a partial area of a target video signal. However, by specifying on the image, the auto-chroma key operation for determining the specified chroma (color) based on the color value of the partial area is executed as follows.

  Here, an example of a communication sequence of chroma key processing executed in the effect switcher device 100 is shown in FIG.

  In the chroma key processing communication sequence shown in FIG. 4, when the effect switcher device 100 designates a sampling range from the control unit 30 and instructs the first chroma key processing unit 20A to perform the chroma key processing, the first switch is used. The chroma key processing unit 20A determines a chroma value in the sampling range, and transmits the determined chroma value to the second chroma key processing unit 20B. Then, the first chroma key processing unit 20A starts chroma key processing using the determined chroma value, and the second chroma key processing unit 20B starts chroma key processing using the received chroma value.

  That is, for example, as shown in the flowchart of FIG. 5A, the first chroma key processing unit 20A is configured such that the auto / chroma key determination circuit 23A first designates a color sampling position in the screen from the control unit 30. Is received (step S1), and then the chroma value at the designated position (range) is acquired by hardware (step S2), and the average value of the chroma values is determined (step S3). Then, the auto chroma key determination circuit 23A of the first chroma key processing unit 20A transmits the average value of the determined chroma values to the second chroma key processing unit 20B (step S4), and then waits for a specified field. (Step S5) The average value of the determined chroma values is given to the chroma key circuit 24A as a chroma key signal to start chroma key processing (step S6).

  Then, as shown in the flowchart of FIG. 5B, the second chroma key processing unit 20B calculates the average value of chroma values determined from the auto / chroma key determination circuit 23A of the first chroma key processing unit 20A. When it is received (step S11), it waits for a specified field (step S12), gives the average value of the received chroma values to the chroma key circuit 24B as a chroma key signal, and starts chroma key processing (step S13). It should be noted that the numerical value of this specified field is the average value of chroma values from the chroma key processing unit 20A compared with the numerical value of the specified field described in the description of step S5 in the flowchart shown in FIG. The number of fields required for transmission to the chroma key processing unit 20B is small. In other words, the chroma key processing unit 20A, which is the transmission source, waits extra for the number of fields required for transmission, and the timing for starting the chroma key processing is the chroma key processing unit 20A (step S6) and the chroma key processing unit 20B (step S13). ) And the same timing.

  FIG. 6 shows another example of the communication sequence of chroma key processing executed in the effect switcher device 100.

  In the chroma key processing communication sequence shown in FIG. 6, when the sampling range is designated from the control unit 30 and the chroma key processing is instructed to the first chroma key processing unit 20A, the first chroma key processing unit 20A The determined chroma value is determined, and the determined chroma value is transmitted to the control unit 30. Upon receipt of the chroma value from the first chroma key processing unit 20A, the control unit 30 transmits the chroma value to the first chroma key processing unit 20A to instruct the start of chroma key processing, and the second chroma key. The chroma value is transmitted to the processing unit 20B to instruct the start of chroma key processing. Then, the first chroma key processing unit 20A and the second chroma key processing unit 20B wait for a sync interrupt and simultaneously start chroma key processing using the received chroma value.

  That is, for example, as shown in the flowchart of FIG. 7A, the first chroma key processing unit 20A is configured such that the auto / chroma key determination circuit 23A first designates a color sampling position in the screen from the control unit 30. (Step S21), then, the chroma value at the specified position (range) is acquired by hardware (step S22), the average value of the chroma values is determined (step S23), and the average of the determined chroma values is determined. The value is transmitted to the control unit 30 (step S24). The chroma key circuit 24A of the first chroma key processing unit 20A waits for a chroma key instruction from the control unit 30 (step S25), receives the chroma key instruction and the chroma value from the control unit 30, and receives the next field. Then, the chroma key process is started (step S26).

  Then, as shown in the flowchart of FIG. 7B, the chroma key circuit 24B of the second chroma key processing unit 20B receives the chroma key instruction and the chroma value from the control unit 30 (step S31). The chroma key processing is started from the field (step S32). Since the frequency of communication is performed at least once for each field, the start of chroma key processing is not delayed more than necessary or the start timing is not shifted.

  Furthermore, FIG. 8 shows still another example of the communication sequence of chroma key processing executed in the effect switcher device 100.

  In the chroma key processing communication sequence shown in FIG. 8, the control unit 30 designates the sampling range and the chroma key processing is instructed to the first chroma key processing unit 20A and the second chroma key processing unit 20B, and the first One chroma key processing unit 20A and the second chroma key processing unit 20B determine a chroma value in the sampling range. Then, the first chroma key processing unit 20A transmits the determined chroma value to the control unit 30, waits for a sync interrupt, and starts chroma key processing using the determined chroma value. The second chroma key processing unit 20B waits for a sync interrupt and starts chroma key processing using the determined chroma value. Upon receipt of the chroma value from the first chroma key processing unit 20A, the control unit 30 transmits the chroma value to the first chroma key processing unit 20A to instruct the start of chroma key processing, and the second chroma key. The chroma value is transmitted to the processing unit 20B to instruct the start of chroma key processing. Then, the first chroma key processing unit 20A and the second chroma key processing unit 20B wait for a sync interrupt and simultaneously start chroma key processing using the received chroma value.

  In the chroma key process executed in accordance with the communication sequence of the chroma key process shown in FIG. 8, the state transition diagram as shown in FIG. 9 is the standby state (ST1), and the sampling process state for determining the chroma value in the sampling range ( ST2), a single chroma key operation state (ST3) using the determined chroma value, and a received value chroma key operation state (ST4) using the received chroma value.

  The state transition from the standby state (ST1) to the sampling processing state (ST2) occurs when a chroma key processing instruction specifying a sampling range is received, and the single chroma key operation state (ST3) from the sampling processing state (ST2). The state transition to) is generated by a sink interrupt. The state transition from the single chroma key operation state (ST3) to the received value chroma key operation state (ST4) is generated by receiving an instruction for chroma key processing, and the stand-by state from the single chroma key operation state (ST3). The state transition to (ST1) occurs when a chroma key process end instruction is received. Further, the state transition from the standby state (ST1) to the received value chroma key operation state (ST4) occurs when a chroma key processing instruction is received, and the received value chroma key operation state (ST4) the standby state (ST1). The state transition to) occurs when a chroma key process end instruction is received.

  In the above description, the case where a pair of chroma key processing circuits is described has been described. However, even when a single device includes a plurality of pairs of chroma key processing circuits, the operation described above is performed for each pair. Thus, high quality dual link chroma key processing can be realized.

  Similarly to the conventional effect switcher device, the chroma value determined by the auto-chroma key determination circuit is transmitted to the selection input unit and can be displayed on a graphical display or the like. In this case, the chroma value to be transmitted to the selection input unit is finally a value used by both of the chroma key processing units of the pair, that is, a common value transmitted between the chroma key processing units. It is reasonable.

It is a block diagram which shows the structure of the image processing system of a dual link provided with the effect switcher apparatus to which this invention is applied. It is a block diagram which shows the structure of the said effect switcher apparatus. It is a block diagram which shows the structural example of a key processing circuit. It is a sequence diagram which shows an example of the communication sequence of the chroma key process performed in the said effect switcher apparatus. It is a flowchart which shows operation | movement of the 1st chroma key process part of the said effect switcher apparatus, and a 2nd chroma key process part, when performing the chroma key process according to the sequence shown in FIG. It is a sequence diagram which shows another example of the communication sequence of the chroma key process performed in the said effect switcher apparatus. 7 is a flowchart showing operations of a first chroma key processing unit and a second chroma key processing unit of the effect switcher device when performing chroma key processing according to the sequence shown in FIG. 6. It is a sequence diagram which shows another example of the communication sequence of the chroma key process performed in the said effect switcher apparatus. FIG. 9 is a state transition diagram of the first chroma key processing unit and the second chroma key processing unit of the effect switcher device when performing chroma key processing according to the sequence shown in FIG. 8.

Explanation of symbols

  L1-L9 input line, 10 matrix switcher section, 11A, 11B key source signal selection input bus, 12A, 12B key source intersection row, 13A, 13B key fill signal selection input bus, 14A, 14B key fill intersection row, 15A, 15B 1st Background signal selection input bus, 16A, 16B first background intersection point sequence, 17A, 17B second background signal selection input bus, 18A, 18B second background intersection point sequence, 20A first chroma key processing unit, 20B second Chroma key processing unit, 21A, 21B key processing circuit, 22A, 22B synthesis circuit, 23A, 23B auto chroma key determination circuit, 24A, 24B chroma key circuit, 30 control unit, 35 control line, 40 main unit, 50 communication path, 60 Selection input part, 61 Button arrangement part, 62 Keyboard, 63 Pointing device, 64 graphical display, 100 effect switcher device

Claims (4)

Two image processing circuits each having a chroma key circuit and an auto chroma key determination circuit;
A communication path connecting the two image processing circuits,
The chroma value determined by the auto-chroma key determination circuit of one image processing circuit is supplied to the chroma key circuit on the other image processing circuit via the communication path, and the one image processing circuit and the other image processing circuit A chroma key processing device corresponding to a dual link that performs the same control of image frames for starting chroma key processing. A control unit for controlling each operation of the two image processing circuits;
2. A chroma key processing apparatus according to claim 1, wherein a chroma value determined by an auto chroma key determining circuit of said one image processing circuit is supplied to a chroma key circuit on said other image processing circuit via said control unit.   3. The control unit according to claim 2, wherein when the chroma value determined by the auto chroma key determination circuit of the one image processing circuit is received, the control unit transmits the received chroma value to the two image processing circuits to start chroma key processing. Chroma key processing device. Chroma values are determined in parallel by each auto-chroma key determination circuit of two image processing circuits each having a chroma key circuit and an auto-chroma key determination circuit.
Start chroma key processing from the same image frame,
The chroma value determined by the auto-chroma key determination circuit of one image processing circuit is supplied as a common chroma value to the chroma key circuit on the image processing circuit via the communication path,
A chroma key processing method corresponding to a dual link in which the chroma key processing of the common chroma value is started from the same image frame by the chroma key circuits of the two image processing circuits.

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