JP2009253121A - Horizontal semiconductor device having trench gate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a horizontal semiconductor device which simultaneously achieves reduction of ON-state resistance and improvement of ESD resistance. <P>SOLUTION: The horizontal semiconductor device 10 having a trench gate 40 includes: a first body contact region 21; a source region 23; a second body contact region 24; and a drain region 26. The first body contact region 21, the source region 23, the second body contact region 24, and the drain region 26 are arranged in this order along one direction of a surface layer part of a semiconductor layer 20. The source region 23 and the drain region 26 are formed to positions deeper than the second body contact area 24. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a lateral semiconductor device having a trench gate. The present invention also relates to a method for manufacturing the lateral semiconductor device.

  The horizontal semiconductor device is used in, for example, an in-vehicle power converter. The characteristics required for this type of lateral semiconductor device are not only low on-resistance (or on-voltage) but also high ESD (Electro-Static Discharge) resistance. An example of a lateral semiconductor device with improved ESD tolerance is disclosed in Patent Document 1.

FIG. 15 schematically shows a cross-sectional view of an example of the horizontal semiconductor device 200 disclosed in Patent Document 1. In FIG. The lateral semiconductor device 200 includes a p-type body region 222, an n ⁺ -type source region 223, a p ⁺ -type body contact region 224, an n-type drift region 225, and an n-type provided in the surface layer portion of the semiconductor layer 220. ^{A +} type drain region 226 is provided. The semiconductor region 227 is a remaining portion of each of the semiconductor regions 222, 223, 224, 225, and 226 provided in the surface layer portion of the semiconductor layer 220. The source region 223 and the body contact region 224 are electrically connected to the source electrode. The drain region 226 is electrically connected to the drain electrode.

  A broken line 240 in the drawing indicates a range where the trench gate exists in the depth direction of the drawing. The trench gate 240 extends from the surface of the semiconductor layer 220 toward the deep part. The trench gate 240 faces the body region 222 in the semiconductor layer 220. 234 in the figure is a field oxide film, and 232 is a field plate electrode.

  When a positive voltage is applied to the trench gate, an inversion layer is formed in the body region 222 facing the trench gate 240. Electrons injected from the source region 223 flow toward the drift region 225 and the drain region 226 via the inversion layer.

  The lateral semiconductor device 200 is characterized in that a body contact region 224 is provided between the source region 223 and the drain region 226. When a high surge voltage such as ESD is applied, an impact ionization phenomenon occurs in the lateral semiconductor device 200, and holes are generated in the semiconductor layer 220. The impact ionization phenomenon often occurs in the vicinity of the right edge 240a of the bottom surface of the trench gate 240. For this reason, when the body contact region 224 is provided at the above position, holes generated by the impact ionization phenomenon are smoothly discharged to the body contact region 224. For this reason, a phenomenon in which a parasitic npn transistor including the source region 223, the body region 222, and the drift region 225 is turned on is suppressed. The horizontal semiconductor device 200 has a high ESD tolerance.

JP 2004-214611 A

  However, in the lateral semiconductor device 200 of FIG. 15, the source region 223 and the drain region 226 are provided in a shallow region of the surface layer portion of the semiconductor layer 220. For this reason, most of the current tends to flow through the surface layer portion of the semiconductor layer 220. However, a body contact region 224 is provided between the source region 223 and the drain region 226. Since the impurity concentration of the body contact region 224 is high, no inversion layer is formed in the body contact region 224. For this reason, in the horizontal semiconductor device 200, most of the current tends to flow through the surface layer portion of the semiconductor layer 220, but the current contact path is narrowed by the body contact region 224 provided between the source region 223 and the drain region 226. It is done. The semiconductor device 200 has a problem of high on-resistance.

  An object of the present invention is to provide a lateral semiconductor device that simultaneously achieves a reduction in on-resistance and an improvement in ESD tolerance.

  A lateral semiconductor device having a trench gate disclosed in this specification includes a first well region, a second well region, a first semiconductor region, a second semiconductor region, and a contact region. The first well region is provided in the surface layer portion of the semiconductor layer and is of the first conductivity type. The second well region is provided in the surface layer portion of the semiconductor layer, is adjacent to the first well region, and is of the second conductivity type. The first semiconductor region is provided in the surface layer portion of the semiconductor layer, is separated from the second well region by the first well region, is connected to the first main electrode, and is of the second conductivity type. The second semiconductor region is provided in a surface layer portion of the semiconductor layer, is separated from the first well region by the second well region, is connected to the second main electrode, and has an impurity concentration higher than that of the second well region. Is the second conductivity type having a high concentration. The contact region is a surface layer portion of the semiconductor layer and is provided in the first well region, is connected to the first main electrode, and has a first conductivity type having a higher impurity concentration than the first well region. is there. The trench gate has a gate insulating film and a gate electrode covered with the gate insulating film, and faces the first well region that separates the first semiconductor region and the second well region. The contact region has at least a first contact region and a second contact region. The first contact region, the first semiconductor region, the second contact region, and the second semiconductor region are arranged in this order along the surface direction of the semiconductor layer along one direction. Further, the first semiconductor region and the second semiconductor region are formed to a position deeper than the second contact region.

In the lateral semiconductor device, the first semiconductor region is connected to the first main electrode, and the second semiconductor region is connected to the second main electrode. For this reason, a current flows between the first semiconductor region and the second semiconductor region. In the lateral semiconductor device, the second contact region is provided between the first semiconductor region and the second semiconductor region. However, since the first semiconductor region and the second semiconductor region are formed deeper than the second contact region, a current conduction path between the first semiconductor region and the second semiconductor region is widely secured. . In the horizontal semiconductor device, the on-resistance is reduced.
Furthermore, in the horizontal semiconductor device, the first contact region, the first semiconductor region, the second contact region, and the second semiconductor region are arranged in this order along the surface layer portion of the semiconductor layer along one direction. The direction connecting the first semiconductor region and the second semiconductor region is the current conduction direction. That is, the first contact region and the second contact region are disposed on both sides of the first semiconductor region in the conduction direction. Since the first contact region and the second contact region are arranged along the conduction direction, carriers generated by the impact ionization phenomenon can be smoothly discharged to the first contact region and / or the second contact region.
In the lateral semiconductor device, (1) the first semiconductor region and the second semiconductor region are provided deep, (2) the first contact region and the second contact region are provided on both sides of the first semiconductor region, both It is characterized by combining. When the form (1) is adopted, the on-resistance can be reduced, but the current path becomes wide, so that the impact ionization phenomenon can occur in various places in the semiconductor layer. However, by adopting the form (2) at the same time, the generated holes can be smoothly discharged to the first contact region and / or the second contact region no matter where the impact ionization phenomenon occurs in the semiconductor layer. Can do. When the form (1) is adopted, the usefulness (2) is remarkably exhibited. The synergistic effect obtained by combining the above (1) and (2) is extremely useful.

  In the lateral semiconductor device disclosed in this specification, it is preferable that the depths of the first semiconductor region and the second semiconductor region be greater than or equal to the depth of the trench gate. Accordingly, carriers injected from the first semiconductor region can flow using the entire side surface of the trench gate. A wide current conduction path is ensured, and the on-resistance is further reduced.

  It is preferable that the first semiconductor region and the second semiconductor region have the same depth. When this form is adopted, the first semiconductor region and the second semiconductor region can be formed by a common manufacturing process. By creating the first semiconductor region and the second semiconductor region in a common manufacturing process, the number of manufacturing processes of the horizontal semiconductor device can be reduced.

  It is preferable that the first contact region is formed to a position deeper than the second contact region. The position where the first contact region is provided does not hinder the current conduction path. Therefore, if the first contact region is formed deeply, the ESD tolerance can be improved without affecting the on-resistance.

  According to the technology disclosed in this specification, it is possible to provide a lateral semiconductor device that can simultaneously achieve a reduction in on-resistance and an improvement in ESD tolerance.

The features of the technology disclosed in this specification will be summarized.
(First Feature) The source region and the drain region are formed deeper than the second body contact region. Preferably, the depth of the source region and the drain region is not less than twice the depth of the second body contact region.
(Second Feature) The first body contact region is formed deeper than the second body contact region. Preferably, the depth of the first body contact region is at least twice the depth of the second body contact region.
(Third Feature) The trench gate extends from the surface of the semiconductor layer toward the deep portion. Preferably, the depth of the trench gate is at least twice the depth of the second body contact region.
(Fourth Feature) A horizontal semiconductor device is formed in an active layer of an SOI substrate.

  Hereinafter, embodiments will be described in detail with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected about the common component, The description is abbreviate | omitted. In the following embodiments, silicon is used as a semiconductor material, but other semiconductor materials may be used. For example, a semiconductor material such as silicon carbide, gallium arsenide, or gallium nitride may be used. The techniques according to the following examples are also useful for other semiconductor materials. Moreover, even if the conductivity type (n-type, p-type) of each semiconductor region is reversed, the techniques according to the following examples can be reproduced. The technology according to the following embodiments is also useful for semiconductor devices other than MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), such as IGBTs (Insulated Gate Bipolar Transistors).

  FIG. 1 schematically shows a main part plan view of the horizontal semiconductor device 10. FIG. 2 schematically shows a longitudinal sectional view corresponding to the line II-II in FIG. FIG. 3 schematically shows a longitudinal sectional view corresponding to the line III-III in FIG. 1, the field oxide film 34 and the field plate electrode 32 on the semiconductor layer 20 shown in FIGS. 2 and 3 are omitted for convenience.

  The horizontal semiconductor device 10 is formed using a silicon single crystal semiconductor layer 20. The semiconductor layer 20 is an active layer of an SOI substrate, for example. Therefore, in the cross-sectional views of FIGS. 2 and 3, only the semiconductor layer 20 is illustrated, and the other semiconductor substrate and the buried insulating layer constituting the SOI substrate are omitted.

  The lateral semiconductor device 10 includes a p-type body region 22 (an example of a first well region) and an n-type drift region 25 (an example of a second well region) provided in the surface layer portion of the semiconductor layer 20. . The body region 22 and the drift region 25 are adjacent to each other. The body region 22 and the drift region 25 can be formed in the surface layer portion of the semiconductor layer 20 using, for example, an ion implantation technique. Alternatively, as will be described later, the body region 22 and the drift region 25 can be formed by utilizing thermal diffusion of impurities from doped polysilicon.

The lateral semiconductor device 10 further includes an n ⁺ -type source region 23 (an example of a first semiconductor region), a first body contact region 21, and a first body contact region 21 provided in the body region 22 as a surface layer portion of the semiconductor layer 20. Two body contact regions 24 are provided. Source region 23 is separated from drift region 25 by body region 22. Body contact regions 21 and 24 have a higher impurity concentration than body region 22. A broken line 24 </ b> D in FIG. 2 indicates the depth of the second body contact region 24. The source region 23 is formed deeper than the second body contact region 24. The source region 23, the first body contact region 21 and the second body contact region 24 are connected to the source electrode.

  The source region 23 and the body contact regions 21 and 24 are formed in the surface layer portion of the semiconductor layer 20 using, for example, an ion implantation technique. Alternatively, as will be described later, the source region 23 can be formed by utilizing thermal diffusion of impurities from doped polysilicon.

The lateral semiconductor device 10 further includes an n ⁺ -type drain region 26 which is a surface layer portion of the semiconductor layer 20 and is provided in the drift region 25. The drain region 26 is separated from the body region 22 by the drift region 25. The drain region 26 has a higher impurity concentration than the drift region 25. As shown in FIG. 2, the drain region 26 is also formed deeper than the second body contact region 24. The drain region 26 is connected to the drain electrode. As will be described later, the drain region 26 can be formed by forming a deep trench and then introducing impurities into the inner wall of the trench. Alternatively, the drain region 26 can be formed by filling the deep trench with doped polysilicon. The semiconductor region 27 is the remaining part of each semiconductor region provided in the surface layer portion of the semiconductor layer 20.

  The horizontal semiconductor device 10 further includes a trench gate 40. The trench gate 40 extends from the surface of the semiconductor layer 20 toward the deep part. The trench gate 40 has a gate insulating film 44 made of silicon oxide and a polysilicon gate electrode 42 covered with the gate insulating film 44. In FIG. 2, the range where the trench gate 40 exists in the depth direction of the drawing is indicated by a broken line. As shown in FIG. 2, the trench gate 40 faces a part of the body region 22 that separates the source region 23 and the drift region 25 in the semiconductor layer 20. 34 is a field oxide film, and 32 is a field plate electrode. The field plate electrode 32 is electrically connected to the gate electrode 42 of the trench gate 40.

  Next, the function and effect of the horizontal semiconductor device 10 will be examined using a comparative example. FIG. 4 is a longitudinal sectional view of three types of horizontal semiconductor devices that have been compared and studied. 4A shows the lateral semiconductor device 10 of this embodiment, FIG. 4B shows the lateral semiconductor device of the first comparative example, and FIG. 4C shows the lateral semiconductor device of the second comparative example. . In all three types of horizontal semiconductor devices, the depth of the trench gate 40 and the drain region 26 is 3 μm, and the depth of the source region 23 is 1 μm. The first comparative example of FIG. 4B is different from the horizontal semiconductor device 10 of this embodiment (FIG. 4A) in that the first contact region 21 is not provided. The second comparative example of FIG. 4C is different from the horizontal semiconductor device 10 of this embodiment (FIG. 4A) in that the second contact region 24 is not provided.

  FIG. 5 shows the relationship between the drain voltage and drain current of each of the three types of horizontal semiconductor devices. In the figure, (A) shows the result of the horizontal semiconductor device 10 of this example, (B) in the figure shows the result of the horizontal semiconductor device of the first comparative example, and (C) in the figure shows the horizontal type of the second comparative example. It is a result of a semiconductor device.

  Here, the snapback phenomenon will be described. The snap-back phenomenon refers to a phenomenon in which the drain voltage decreases in the source-drain breakdown voltage characteristics when the drain current further flows after reaching the breakdown voltage. That is, the snapback phenomenon refers to a phenomenon in which a point showing negative resistance appears. There is a substantially proportional relationship between the current value at the point where the snapback phenomenon occurs and the ESD tolerance. Therefore, the lateral semiconductor device having a high current value has a high ESD tolerance.

  As shown in FIG. 5, the current value at which the snapback phenomenon occurs is highest in this example (A), about 5 times that of the second comparative example and about 3.4 times that of the first comparative example. In particular, the present Example (A) has a remarkable result clearly different from the other Comparative Examples (B) and (C).

  The horizontal semiconductor device in FIG. 4C shows a general form that has been widely known. In the horizontal semiconductor device of this embodiment, the impact ionization phenomenon occurs in the vicinity of the right edge 40 a on the bottom surface of the trench gate 40. The generated holes move laterally in the body region 22 toward the first body contact region 21. Based on the product of the “hole current” and the “path resistance component”, the potential of the body region 22 rises, and the parasitic npn transistor including the source region 23, the body region 22, and the drift region 25 is turned on. The parasitic npn transistor is turned on near 46 in the figure. As a result, the snap-back phenomenon occurs at an early stage in the horizontal semiconductor device of FIG.

  In the lateral semiconductor device of FIG. 4B, the second body contact region 24 is provided between the source region 23 and the drain region 26. For this reason, holes generated by the impact ion phenomenon are discharged toward the second body contact region 24. For this reason, compared with the case of FIG. 4C, in the lateral semiconductor device of FIG. 4B, the path through which holes flow is short and the resistance component to the second body contact region 24 is small. Hard to turn on. As a result, as shown in FIG. 5, the horizontal semiconductor device of FIG. 4B has an increased current value causing a snapback phenomenon as compared with the horizontal semiconductor device of FIG. The tolerance is improved.

  The lateral semiconductor device 10 in FIG. 4A is characterized by including both the first body contact region 21 and the second body contact region 24. For this reason, the generated holes can be discharged to the first body contact region 21 or the second body contact region 24 through a short path. As described above, since the horizontal semiconductor device 10 in FIG. 4A can discharge holes through two paths, the resistance component of these paths becomes smaller, compared to other horizontal semiconductor devices, The current value at which the snapback phenomenon occurs is remarkably increased, and the ESD resistance is greatly improved.

  4A to 4C, the impact ionization phenomenon caused by the depth of the trench gate 40, the depth and concentration of the body region 22, and the depth and concentration of the drift region 25 is caused by the bottom surface of the trench gate 40. It may occur not only near the right edge of the image but also in various places. Wherever the impact ionization phenomenon occurs, with the structure of FIG. 4A, the distance to the first body contact region 21 or the second body contact region 24 can be shortened, and the ESD resistance is greatly improved. can do.

  That is, in the lateral semiconductor device 10 of this embodiment, (1) the source region 23 and the drain region 26 are deeply provided, and (2) the first body contact region 21 and the second body contact region 24 are arranged on both sides of the source region 23. It is characterized by being provided in the above and a combination of both. When the form (1) is adopted, the on-resistance can be reduced. In addition, by adopting the form (2) at the same time, the impacted ionization phenomenon occurs anywhere in the semiconductor layer 20, so that the generated holes are passed through the first body contact region 21 or the second body contact region 24 through a short path. Can be discharged. When the form (1) is adopted, the usefulness (2) is remarkably exhibited. The synergistic effect obtained by combining the above (1) and (2) is extremely useful.

(Modification 1)
FIG. 6 shows a modified horizontal semiconductor device 11. The lateral semiconductor device 11 is characterized in that the source region 123 is formed to a position deeper than the trench gate 40. In the horizontal semiconductor device 11, the source region 123 and the drain region 26 have the same depth. This form indicates that the source region 123 and the drain region 26 are formed by a common manufacturing process. The manufacturing process will be described later.

  As shown in FIG. 6, when the source region 123 is formed deeper than the trench gate 40, the potential injected from the source region 123 can flow using the entire side surface of the trench gate 40. . A wide current conduction path is ensured, and the on-resistance is further reduced.

(Modification 2)
FIG. 7 shows a modified horizontal semiconductor device 12. The lateral semiconductor device 12 is characterized in that the first body contact region 121 is formed to a position deeper than the second body contact region 24. In this example, the first body contact region 121 and the source region 123 have the same depth. Since the first body contact region 121 is not provided between the source region 123 and the drain region 26, it does not hinder the current conduction path. Therefore, even if the first body contact region 121 is formed deeply, the on-resistance is not affected. On the other hand, if the first body contact region 121 is formed deeply, holes generated by the impact ionization phenomenon are discharged from the first body contact region 121 at a shorter distance. If the first body contact region 121 is formed deeply, the ESD tolerance can be further improved without affecting the on-resistance.

(Manufacturing process of drain region 26)
FIG. 8 shows a process for manufacturing the drain region 26 of this embodiment. The drain region 26 of this embodiment is deeper than that of the prior art. The technique described below is preferably used.

  First, as shown in FIG. 8A, a BPSG (Boron Phosphor Silicate Glass) film 52 having an opening on the surface of the semiconductor layer 20 is formed. Further, a mask 53 that covers the BPSG film 52 and has an opening is formed. The opening width of the BPSG film 52 is wider than the opening width of the mask 53. Next, using the plasma etching technique, the semiconductor layer 20 exposed from the opening is removed, and the trench 54 is formed.

  Next, as shown in FIG. 8B, the mask 53 is removed. Next, phosphorus vapor phase diffusion is performed. As a result, as shown in FIG. 8B, phosphorus is introduced into the inner wall of the trench 54 and a high concentration region 55 is formed. In this example, the high concentration region 55 functions as the drain region 26 of the horizontal semiconductor devices 10, 11, 12 described above.

  Next, as shown in FIG. 8C, tungsten 56 is filled in the trench 54. Thereby, a drain region electrically connected to the drain electrode can be formed.

(Modification of manufacturing process of drain region 26)
The drain region 26 can also be formed by the manufacturing process shown in FIG. First, as shown in FIG. 9A, a mask 57 having an opening on the surface of the semiconductor layer 20 is formed. Next, using the plasma etching technique, the semiconductor layer 20 exposed from the opening is removed, and the trench 54 is formed.

  Next, as shown in FIG. 9B, the mask 57 is removed. Next, the trench 58 is filled with polysilicon 58 containing phosphorus at a high concentration. In this example, the polysilicon 58 functions as the drain region 26 of the lateral semiconductor devices 10, 11, and 12 described above.

(Manufacturing process of the source region 23)
FIG. 10 shows a process for manufacturing the source region 23 of this embodiment. The source region 23 of this embodiment is deeper than that of the prior art. The deep source region 23 preferably uses a multistage ion implantation technique.

  First, as shown in FIG. 10A, a mask 64 having an opening on the surface of the semiconductor layer 20 is formed. Next, an impurity is introduced into the semiconductor layer 20 through the opening of the mask 64 using an ion implantation technique. The peak of the introduced impurity concentration distribution is set at a deep position in the semiconductor layer 20. The introduced impurity forms a partial region 62.

  Next, as shown in FIG. 10B, an impurity is introduced into the semiconductor layer 20 through the opening of the mask 64 using an ion implantation technique. The peak of the introduced impurity concentration distribution is set at a position shallower than the previous time. The introduced impurity forms a partial region 63. The partial regions 62 and 63 function as the source region 23 of the lateral semiconductor devices 10, 11 and 12 described above.

(Simultaneous manufacturing process of source region 23 and body region 22)
FIG. 11 shows a process of simultaneously manufacturing the source region 23 and the body region 22 of the lateral semiconductor devices 10, 11, and 12 described above.
First, as shown in FIG. 11A, a trench 72 is formed in the surface layer portion of the semiconductor layer 20. The trench 72 can be formed using, for example, a dry etching technique.

  Next, as shown in FIG. 11B, the trench 72 is filled with polysilicon 74 containing boron and arsenic. In order to fill the polysilicon 74, for example, an evaporation technique or an epitaxial growth technique may be used.

  Next, as shown in FIG. 11C, the semiconductor layer 20 is heat-treated. The diffusion coefficient of boron is larger than that of arsenic. For this reason, as shown in FIG. 11C, the p-type diffusion region 78 is formed at a position far from the polysilicon 74 and the n-type diffusion region 76 is close to the polysilicon 74 based on the difference in diffusion coefficient. Formed in position. The p-type diffusion region 78 functions as the body region 22 of the lateral semiconductor devices 10, 11, and 12 described above, and the n-type diffusion region 76 functions as the source region 23.

  As shown in FIG. 12A, after the inner wall of the trench 72 is covered with the first polysilicon 74a containing arsenic by using a vapor deposition technique, the inside of the trench 72 as shown in FIG. Alternatively, the second polysilicon 74b containing boron may be filled. The impurities contained in the first polysilicon 74a and the second polysilicon 74b may be reversed.

  Next, as shown in FIG. 12C, the semiconductor layer 20 is heat-treated. Similarly, in this case, the p-type diffusion region 78 is formed at a position far from the polysilicons 74a and 74b and the n-type diffusion region 76 is formed at a position near the polysilicons 74a and 74b based on the difference in diffusion coefficient. Is done.

  Further, as shown in FIGS. 13A and 13B, after covering the first polysilicon 74a, a part 75 of the first polysilicon 74a covering the bottom surface of the trench 72 is removed, and the semiconductor layer is removed. 20 may be exposed at the bottom of the trench 72. In this case, as shown in FIG. 13C, the second polysilicon 74 b can be electrically connected to the n-type diffusion region 76. For this reason, the potential of the n-type diffusion region 76 can be stabilized throughout.

(Simultaneous manufacturing process of source region 22, body region 22 and drain region 26)
14A to 14D show a process of simultaneously manufacturing the source region 22, the body region 22, and the drain region 26 of the lateral semiconductor devices 10, 11, and 12 described above.

  First, as shown in FIG. 14A, the first trench 172 and the second trench 154 are formed in the surface layer portion of the semiconductor layer 20. The position where the first trench 172 is formed corresponds to the position of the source region 22 and the body region 22. The position where the second trench 154 is formed corresponds to the position of the drain region 26. The trench width 172W of the first trench 172 is larger than the trench width 154W of the second trench 154. The trench width 172W of the first trench 172 is preferably 1.5 times or more the trench width 154W of the second trench 154.

  Next, as shown in FIG. 14B, the inner wall of the first trench 172 is covered with the first polysilicon 82 containing arsenic by using a vapor deposition technique, and the first polysilicon 82 is filled in the second trench 154. To do. At this time, the first trench 172 is not completely filled with the first polysilicon 82 and the second trench 154 is completely filled with the first polysilicon 82. Here, the first polysilicon in the first trench 172 is denoted by reference numeral 82a, and the first polysilicon in the second trench 154 is denoted by reference numeral 84. Next, as shown in FIG. 14C, the first trench 172 is filled with the second polysilicon 82b containing boron.

  Next, as shown in FIG. 14D, the semiconductor layer 20 is heat-treated. A p-type diffusion region 87 and an n-type diffusion region 86 are formed around the first trench 172 based on the difference in diffusion coefficient. Only the n-type diffusion region 85 is formed around the second trench 154. Around the first trench 172, the p-type diffusion region 87 functions as the body region 22 of the lateral semiconductor devices 10, 11, and 12 described above, and the n-type diffusion region 86 functions as the source region 23. Around the second trench 154, the n-type diffusion region 85 functions as the drain region 26.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part top view of the horizontal type semiconductor device of a present Example is typically shown. The longitudinal cross-sectional view corresponding to the II-II line of FIG. 1 is shown typically. FIG. 2 schematically shows a longitudinal sectional view corresponding to the line III-III in FIG. 1. The form of the horizontal type semiconductor device examined comparatively is shown typically. The relationship between the drain voltage and the drain current of each of the lateral semiconductor devices that were compared and examined is shown. The principal part top view of the modification of the horizontal type | mold semiconductor device of a present Example is shown typically. The principal part top view of the modification of the horizontal type | mold semiconductor device of a present Example is shown typically. The manufacturing process of the drain region of a present Example is shown. The modification of the manufacturing process of the drain region of a present Example is shown. The manufacturing process of the source region of a present Example is shown. The simultaneous manufacturing process of the source region and the body region of this embodiment will be described. The modification of the simultaneous manufacturing process of the source region and the body region of the present embodiment will be shown. The modification of the simultaneous manufacturing process of the source region and the body region of this embodiment is shown The first stage of the simultaneous manufacturing process of the source region, the body region, and the drain region of this embodiment will be described. The second stage of the simultaneous manufacturing process of the source region, the body region, and the drain region of this embodiment will be described. A third stage of the simultaneous manufacturing process of the source region, the body region, and the drain region of the present embodiment will be described. A fourth stage of the simultaneous manufacturing process of the source region, the body region, and the drain region of this embodiment will be described. The principal part sectional drawing of the conventional horizontal semiconductor device is shown typically.

Explanation of symbols

20: Semiconductor layer 21, 121: First body contact region 22: Body region 23, 123: Source region 24: Second body contact region 25: Drift region 26: Drain region 27: Semiconductor region 32: Field plate electrode 34: Field Oxide film 40: trench gate 42: gate electrode 44: gate insulating film

Claims (8)

A lateral semiconductor device having a trench gate,
A first well region of a first conductivity type provided in a surface layer portion of the semiconductor layer;
A second well region of a second conductivity type provided in a surface layer portion of the semiconductor layer and adjacent to the first well region;
A first semiconductor region of a second conductivity type provided in a surface layer portion of the semiconductor layer, separated from the second well region by the first well region, and connected to the first main electrode;
A second layer is provided in the surface layer portion of the semiconductor layer, is separated from the first well region by the second well region, is connected to the second main electrode, and has a higher impurity concentration than the second well region. A conductive second semiconductor region;
A contact region of a first conductivity type, which is a surface layer portion of the semiconductor layer and provided in the first well region, connected to the first main electrode and having a higher impurity concentration than the first well region; With
The trench gate has a gate insulating film and a gate electrode covered with the gate insulating film, and faces the first well region that separates the first semiconductor region and the second well region,
The contact region has at least a first contact region and a second contact region;
The first contact region, the first semiconductor region, the second contact region, and the second semiconductor region are arranged in this order along the surface layer portion of the semiconductor layer,
A lateral semiconductor device in which a first semiconductor region and a second semiconductor region are formed deeper than a second contact region.   2. The lateral semiconductor device according to claim 1, wherein a depth of the first semiconductor region and the second semiconductor region is equal to or greater than a depth of the trench gate.   The lateral semiconductor device according to claim 1, wherein the first semiconductor region and the second semiconductor region have the same depth.   The lateral semiconductor device according to claim 1, wherein the first contact region is formed to a position deeper than the second contact region. A method of manufacturing the lateral semiconductor device according to claim 1, comprising:
A trench forming step of forming a first trench in a surface layer portion of the semiconductor layer;
A filling step of filling the first trench with an impurity supply portion including a first impurity of the first conductivity type and a second impurity of the second conductivity type;
A heat treatment step of heat treating the semiconductor layer,
The diffusion coefficient of the first impurity is larger than the diffusion coefficient of the second impurity. Accordingly, when the heat treatment process is performed, the first well region including the first impurity and the first impurity including the second impurity in the surface layer portion of the semiconductor layer. A manufacturing method in which a semiconductor region is formed, the first well region is formed at a position far from the first trench, and the first semiconductor region is formed at a position near the first trench. The impurity supply unit includes a first impurity supply unit including a first impurity and a second impurity supply unit including a second impurity;
The filling step is characterized in that either the first impurity supply unit or the second impurity supply unit covers the inner wall of the first trench and then fills the other into the first trench. Item 6. The manufacturing method according to Item 5.   In the filling step, after the inner wall of the first trench is covered with the first impurity supply part, a part of the first impurity supply part covering the bottom surface of the first trench is removed to remove the semiconductor layer The method according to claim 6, wherein the first impurity is exposed at a bottom surface of the first trench, and then the second impurity supply unit is filled in the first trench. The manufacturing method according to claim 6 or 7,
In the trench formation step, a second trench that is narrower than the first trench is also formed at a position that is a surface layer portion of the semiconductor layer and is separated from the first trench,
In the filling step, the first impurity supply part covers the inner wall of the first trench and the second impurity supply part is filled in the first trench after the first impurity supply part is filled in the second trench. Filled with
When the heat treatment step is performed, a second well region containing a second impurity is formed around the second trench in a surface layer portion of the semiconductor layer.

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