JP2009252954A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a favorable line pattern when microfabricating width dimensions of a line and a space using a sidewall imprint technology. <P>SOLUTION: A method of manufacturing a semiconductor device includes: a process which forms a sacrificial film 5 on a workpiece 4; a process which forms a resist film 6 in which a line and space pattern having a ratio of a line width and a space width on 1:1 basis has been patterned on the sacrificial film 5; a process which carries out the slimming of the resist film 6 and sets a line width dimension to one third of a space width dimension; a process which removes the resist film 6 after processing the sacrificial film 5 with the resist film 6 as a mask; a process which forms a sidewall film 9 on a sidewall of a line of a line and space pattern of the sacrificial film 5; a process which forms a frame-like protective pattern so as to surround a line pattern of the sidewall film 9 after removing the sacrificial film 5; and a process which processes the workpiece 4 with the line pattern and the protective pattern as masks. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device having a fine line and space pattern that exceeds the limits of lithography technology.

  A method of forming a fine line and space pattern below the resolution limit of lithography using a sidewall transfer technique (sidewall processing process) is known (see, for example, Patent Document 1).

With this sidewall transfer technology, it has become possible to form fine line-and-space patterns with line and space width dimensions of several tens of nanometers or less. However, since the pattern has become finer, (1) resist patterns (2) The outermost line of the gate electrode pattern and semiconductor substrate active area pattern formed by this sidewall transfer technology is destroyed by thermal contraction of the insulating film embedded on both sides of the line. The problem of being done has occurred.
JP 2007-150166 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device in which a good line pattern is formed when each width dimension of a line and a space is miniaturized using a sidewall transfer technique.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a sacrificial film on a workpiece, and a resist film patterned on the sacrificial film in a line-and-space pattern having a line width to space width ratio of 1: 1. Forming a line width dimension of the line-and-space pattern by slimming the resist film, and processing the sacrificial film using the resist film as a mask. Removing the resist film; forming a side wall film on a side wall portion of the processed line and space pattern of the sacrificial film; removing the sacrificial film; and a line made of the side wall film. Forming a frame-shaped protective pattern so as to surround the line pattern outside the pattern; and the line pattern and the protective pattern The in to mask, characterized in place and a step of processing the workpiece.

  ADVANTAGE OF THE INVENTION According to this invention, when each width dimension of a line and a space is refined | miniaturized using the side wall transfer technique, a favorable line pattern can be formed.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In this embodiment, a line and space pattern having a pitch that is ½ of the pitch of a line and space pattern (with the same line width and space width) formed using the sidewall transfer technique at the resolution limit of lithography. Thus, an element isolation trench is formed in the memory cell region of the semiconductor substrate.

  First, the line-and-space resist pattern 1 formed at the resolution limit of lithography has a shape as shown in FIG. The line and space pattern 1 is a pattern in which the width dimension d1 of the line 1a and the width dimension d2 of the space 1b are the same dimension (for example, about 40 to 80 nm).

  At both ends of each line 1a of the resist pattern 1, a connection pattern 1c having a width greater than a set dimension, for example, a width dimension of about 100 to 200 nm is provided. With this connection pattern 1c, the resist pattern 1 has a strip shape in which the ends of the lines 1a are connected and terminated. By the termination configuration of the end of the line 1a, even if the widths d1 and d2 of the line 1a and the space 1b are fine patterns of about several tens of nanometers, the end of the line 1a is prevented from falling. Can do.

  FIG. 3 shows a line and space pattern 2 formed on the resist pattern 1 of FIG. 2 by using a sidewall transfer technique. In the line and space pattern 2 shown in FIG. 3, the width dimension d3 of the line 2a and the width dimension d4 of the space 2b are the same, and the widths of the line 1a and the space 1b of the line and space pattern 1 are the same. It is a pattern having a dimension (for example, about 20 to 40 nm) that is ½ of the dimensions d1 and d2.

  Two ends of each line 2a of the line and space pattern 2 are connected to each other by a connection pattern 2c and terminated. The line 2a is formed in a frame shape by the connection pattern 2c. The line-and-space pattern 2 has a frame-like line pattern 2e surrounding the array portion 2d in which a plurality of frame-shaped lines 2a are formed. The width dimension of the frame-like line pattern 2e is the same as the width dimension d3 of the line 2a.

Further, as shown in FIG. 1, a protective pattern 3 having a width equal to or larger than a set dimension, for example, a width dimension of about several μm to 10 μm, is provided outside the frame-like line pattern 2e of the line and space pattern 2 of FIG. It is formed in a frame shape so as to surround the line pattern 2e. In the line and space pattern of FIG. 1, a line pattern 3a along the direction orthogonal to the line 2a of the protective pattern 3 and a line pattern 2e1 along the direction orthogonal to the line 2a of the frame-like line pattern 2e. When the distance between the line pattern 2e1 of the frame-like line pattern 2e and the connection pattern 2c at the end of the line 2a of the line and space pattern 2 is a,
0.8 <(a / b) <1.2
Is configured to hold. The distance a and the distance b are each set to less than about several μm. Furthermore, it is even more preferable that the distance a and the distance b are configured to be substantially equal, that is, configured so that a≈b.

  The distance between the line pattern 3b in the direction along the line 2a in the protective pattern 3 and the line pattern 2e2 in the direction along the line 2a in the frame-like line pattern 2e is h, and the frame-like line pattern 2e. When the distance between the line pattern 2e2 of the line 2 and the line 2a of the line and space pattern 2 is g (= d4), the distance g and the distance h are substantially equal, that is, g (= d3 ) ≈h is established. In this case, the distance g and the distance h are each set to about 20 to 40 nm.

  In the present embodiment, an active area region (line 2a) and an element isolation groove (space 2b) are formed in the memory cell region of the semiconductor substrate with the line and space pattern of FIG.

  Next, a manufacturing process in which the line and space pattern 2 is formed on the line and space pattern 1 by using the side wall transfer technique, and further, the protective pattern 3 is formed and the element isolation groove is formed in the semiconductor substrate will be described with reference to FIG. It will be described with reference to FIG.

  First, as shown in FIG. 4, a sacrificial film 5 made of a polysilicon film or an amorphous silicon film is formed on the semiconductor substrate 4. Subsequently, after a resist film 6 is formed on the sacrificial film 5, the resist film 6 is patterned by a lithography technique so that the width dimension d1 of the line 1a and the width dimension d2 of the space 1b are the same dimension (ratio of the line width to the space width). Is a one-to-one line-and-space resist pattern 1.

  The width dimension d1 (d2) of the line 1a (and space 1b) of the resist pattern 1 is the width dimension of the line 2a (and space 2b) of the line-and-space pattern 2 (see FIG. 9) finally formed as a mask material. It is twice as large as d3 (d4). In other words, the line-and-space pattern 2 having the line 2a (and space 2b) having a width ½ of the width dimension d1 (d2) of the line 1a (and space 1b) of the resist pattern 1 formed here is finally obtained. To form. The top view of the line and space pattern 1 formed here is the pattern shown in FIG.

  Next, as shown in FIG. 5, the resist film 6 of FIG. 4 is processed by using the slimming technique, and the width dimension c1 of the resist film 7a is 1/2 of the width dimension d1 of the resist film 6 before slimming. A line and space pattern 7 is formed in which the width dimension c1 of 7a is 1/3 of the width dimension c2 of the space 7b.

  Subsequently, as shown in FIG. 6, the sacrificial film 5 is processed by the RIE method using the resist film 6 (line and space pattern 7) of FIG. 5 as a mask, and the resist film 6 is removed by ashing. In this case, the sacrificial film 5 is processed so as to maintain a relationship in which the dimension c1 of the line width 8a of the line-and-space pattern 8 is 1/3 of the width dimension c2 of the space 8b.

  Next, as shown in FIG. 7, on the processed sacrificial film 5 (line and space pattern 8) of FIG. It is formed by the CVD method. The thickness of the sidewall film 9 is the same as the width c1 of the line 8a of the line and space pattern 8 of the sacrificial film 5. That is, the film thickness (sidewall film thickness) dimension f of the side wall film 9 formed on the side wall portion of the line 8a of the line and space pattern 8 of the sacrificial film 5 is the same as the width dimension c1 of the line 8a of the sacrificial film 5. Configure to be

  Thereafter, as shown in FIG. 8, the sidewall film 9 is etched back, and the sidewall film 9 a is left only on the sidewall portion of the line 8 a of the line and space pattern 8 of the sacrificial film 5. Subsequently, as shown in FIG. 9, the sacrificial film 5 (the line 8a of the line and space pattern 8) sandwiched between the side wall films 9a is removed. As a result, the line and space pattern 2 made of the sidewall film 9 a is formed on the semiconductor substrate 4. The top view of the line and space pattern 2 formed here is the pattern shown in FIG.

  In the line and space pattern 2 shown in FIG. 9, the width dimension d3 of the line 2a and the width dimension d4 of the space 2b are the same. Furthermore, the width dimension d3 (d3) of the line 2a (space 2b) of the line and space pattern 2 is the width dimension of the line 1a (space 1b) of the line and space pattern 1 (see FIGS. 2 and 4) formed by lithography. It becomes 1/2 of d1 (d2).

  Next, as shown in FIG. 10, after forming a resist film 11 on the semiconductor substrate 4, the resist film 11 is patterned by lithography, so that the frame-shaped protective pattern 3 is formed outside the line and space pattern 2. Form. The top view of the protective pattern 3 formed here is the pattern shown in FIG. Although the protective pattern 3 is composed of a resist film, it may be composed of another film.

  Next, using the line and space pattern 2 and the protection pattern 3 of FIG. 10 as mask materials, element isolation grooves 4b, 4d, and 4f are formed in the semiconductor substrate 4 by the RIE method as shown in FIG. 11, and active areas 4a and 4c are formed. 4e is divided.

  In the present embodiment having such a configuration, protection of a set width that forms a frame so as to surround the frame-like line pattern 2e outside the frame-like line pattern 2e of the sidewall film 9a formed by using the sidewall transfer technique. Since the pattern 3 is formed and the element isolation groove 4b is formed in the semiconductor substrate 4, the active area 4e of the semiconductor substrate 4 corresponding to the frame-like line pattern 2e is not isolated. Therefore, the element isolation trench 4d between the active area 4e of the semiconductor substrate 4 corresponding to the frame-shaped line pattern 2e and the active area 4a of the semiconductor substrate 4 corresponding to the line 2a of the line-and-space pattern 2, and the active area When an insulating film is deposited in the element isolation trench 4f between 4e and the active area 4c of the semiconductor substrate 4 corresponding to the protection pattern 12, the volume of the insulating film can be made the same on both sides of the active area 4e.

  In this configuration, when the insulating film is deposited and then subjected to heat treatment, the insulating film is thermally contracted. However, since the insulating films on both sides of the active area 4e have the same volume, a stress difference is almost generated. This prevents the active area 4e from being destroyed. Further, according to the above embodiment, since the insulating film having a large area does not exist beside the active area 4e, the insulating film is formed by chemical mechanical polishing (hereinafter referred to as CMP) used when forming the insulating film. It is possible to prevent so-called dishing in which local depressions are generated.

  In particular, in the above embodiment, as shown in FIG. 1, a line pattern 3a along the direction orthogonal to the line 2a of the protective pattern 3 formed so as to surround the frame-shaped line pattern 2e, and the frame-shaped line pattern 2e. The distance between the line pattern 2e1 along the direction orthogonal to the line 2a is b, and the line pattern 2e1 of the frame-like line pattern 2e and the connection pattern 2c at the end of the line 2a of the line-and-space pattern 2 When the distance between them is a, the distance a and the distance b are substantially equal, so the volume difference between the insulating films on both sides of the active area corresponding to the frame-like line pattern 2e1 can be greatly reduced, and the active The stress difference applied to the area can be greatly reduced, and the active area can be prevented from being destroyed.

In general, the greater the volume of the insulating film, the greater the stress applied to the active area.
0.8 <(a / b) <1.2
As long as the configuration satisfies the above, destruction of the active area can be prevented. Moreover, since the distance a and the distance b are each set to be less than about several μm, dishing can be suppressed.

  In the embodiment, the distance between the line pattern 3b in the direction along the line 2a in the protective pattern 3 and the line pattern 2e2 in the direction along the line 2a in the frame-like line pattern 2e is h, When the distance between the line pattern 2e2 of the frame-like line pattern 2e and the line 2a of the line-and-space pattern 2 is g (= d3), the distance g and the distance h are substantially equal, and each is about 20 to 40 nm. Set to. Therefore, the active area corresponding to the line pattern 2e2 of the frame-like line pattern 2e can be prevented from being destroyed and dishing can be suppressed.

  Moreover, you may change the shape of the protection pattern 3 like the 2nd Embodiment of this invention shown in FIG. That is, in the second embodiment, a plurality of frames arranged intermittently (intermittently) at a set interval so as to surround the outer periphery of the frame-like line 2e of the line-and-space pattern 2 are formed. The protection pattern 3 was configured with the individual partial protection patterns 13. Even if the plurality of partial protection patterns 13 form grooves in the semiconductor substrate, the active area can be sufficiently protected.

  The configuration of the second embodiment other than that described above is the same as the configuration of the first embodiment. Therefore, also in the second embodiment, substantially the same operational effects as in the first embodiment can be obtained.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.

  In the above-described embodiment, the resist film 6 is slimmed to form the sacrificial film (core material) 5 having the width dimension C1, but instead, the resist film 6 is not slimmed and the sacrificial film 5 is left with the width dimension d1. After etching, the sacrificial film 5 may be slimmed to the width dimension C1 by dry etching or wet etching.

Further, the width dimension of the sacrificial film 5 and the width dimension of the side wall film 9a described in the present embodiment may be formed with some errors in consideration of processing conversion differences and the like.
In the above embodiment, the line and space pattern 2 is formed by the side wall film 9a. Instead, the side wall film 9a is removed to leave the core material (the line 8a of the sacrificial film 5). You may comprise. Specifically, in the state shown in FIG. 8, a film made of the same material as the line 8a of the sacrificial film 5 (or a material having a sufficient etching selection ratio with the side wall film 9a) is embedded in the space of the side wall film 9a. When the buried material film is etched back and then the sidewall film 9a is removed, the line and space pattern 2 is formed by the line 8a of the sacrificial film 5 and the line of the buried material film.

  In the above embodiment, the present invention is applied to the configuration in which the element isolation trench is formed on the semiconductor substrate. However, the present invention is not limited to this, and the gate electrode on the semiconductor substrate is formed in a line and space pattern. The present invention may be applied to a configuration or a configuration in which a wiring layer such as a bit line is formed in a line and space pattern on an interlayer insulating film formed on a semiconductor substrate. That is, as a workpiece, a conductive film for a gate electrode or a conductive film for an interlayer wiring can be considered in addition to a semiconductor substrate.

The schematic top view of the line and space pattern which shows the 1st Embodiment of this invention Top view of line and space pattern formed by lithography technology Top view of line and space pattern formed using sidewall transfer technology Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic cross-sectional view at one stage of the manufacturing process (Part 5) Schematic sectional view at one stage of the manufacturing process (No. 6) Schematic cross-sectional view at one stage of the manufacturing process (Part 7) Schematic cross-sectional view at one stage of the manufacturing process (No. 8) FIG. 1 equivalent diagram showing a second embodiment of the present invention

Explanation of symbols

  In the drawings, 1 is a resist pattern, 2 is a line and space pattern, 3 is a protective pattern, 4 is a semiconductor substrate, 5 is a sacrificial film, 6 is a resist film, 9 is a sidewall film, and 11 is a resist film.

Claims (5)

Forming a sacrificial film on the workpiece;
Forming a resist film patterned on the sacrificial film in a line-and-space pattern having a line width to space width ratio of 1: 1;
Slimming the resist film to reduce the line width of the line and space pattern to 1/3 of the space width;
Processing the sacrificial film using the resist film as a mask, and then removing the resist film;
Forming a sidewall film on a sidewall portion of a line of the processed sacrificial film line and space pattern; and
Removing the sacrificial film;
Forming a frame-shaped protection pattern so as to surround the line pattern outside the line pattern made of the sidewall film;
A step of processing the workpiece using the line pattern and the protective pattern as a mask;
A method for manufacturing a semiconductor device, comprising: Forming a sacrificial film on the workpiece;
Forming a resist film patterned on the sacrificial film in a line-and-space pattern having a line width to space width ratio of 1: 1;
Processing the sacrificial film using the resist film as a mask;
Slimming the processed sacrificial film to reduce the line width dimension of the sacrificial film to one third of the space width dimension;
A step of forming a sidewall film on the sidewall portion of the sacrificial film after removing the resist film formed on the sacrificial film;
After removing the sacrificial film sandwiched between the sidewall films, forming a frame-shaped protective pattern so as to surround the line pattern outside the line pattern made of the sidewall film;
A step of processing the workpiece using the line pattern and the protective pattern made of the sidewall film as a mask;
A method for manufacturing a semiconductor device, comprising:   The workpiece is one of a semiconductor substrate, a gate electrode conductive film formed on the semiconductor substrate, and an interlayer wiring conductive film formed on an interlayer insulating film provided on the semiconductor substrate. A method of manufacturing a semiconductor device according to claim 1 or 2.   4. The method of manufacturing a semiconductor device according to claim 1, wherein the pattern made of a resist film formed on the sacrificial film has a connection pattern for connecting the line ends.   5. The semiconductor according to claim 4, wherein the line pattern formed of the sidewall film formed on the sidewall portion of the sacrificial film includes a plurality of frame-like line patterns and a frame pattern surrounding the plurality of line patterns. Device manufacturing method.

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